From 46bd96f8e954850405e60dc531552abbb7a10231 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 17 Dec 2020 10:45:06 -0700 Subject: [PATCH] [Testbench] Add carevel testbench for ccff test --- ...ccff_test_post_pnr_caravel_include_netlists.v | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_caravel_include_netlists.v diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_caravel_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_caravel_include_netlists.v new file mode 100644 index 0000000..ff84825 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_caravel_include_netlists.v @@ -0,0 +1,16 @@ +//------------------------------------------- +// A file to include all the dependency HDL codes +// required by Caravel gate-level netlists +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA bitstream sizes +`define FPGA_BITSTREAM_SIZE 78765 + +// Include caravel gate-level netlists +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_qlsofa_hd_rtl_include_netlists.v" + +// Include testbench files +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/dv/caravel/spiflash.v"