From d15e7db1beb1359cf148fb129d5e8d739822e3aa Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 9 Jun 2021 19:40:41 -0600 Subject: [PATCH 1/2] [Script] Update openfpga shell script due to the deprecation of 'write_verilog_testbench' --- .../FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga | 6 ++---- .../FPGA1212_SOFA_CHD_task/generate_testbench.openfpga | 6 ++---- .../FPGA1212_SOFA_HD_task/generate_testbench.openfpga | 6 ++---- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga index 1dcf136..49a224f 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga @@ -54,11 +54,9 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC \ +write_full_testbench --file ./SRC \ + --bitstream fabric_bitstream.bit --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ - --print_top_testbench \ - --print_preconfig_top_testbench \ - --print_simulation_ini ./SimulationDeck/simulation_deck.ini \ --explicit_port_mapping # Exclude signal initialization since it does not help simulator converge # due to the lack of reset pins for flip-flops diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga index 1318a22..59b4638 100644 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga +++ b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga @@ -53,11 +53,9 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC \ +write_full_testbench --file ./SRC \ + --bitstream fabric_bitstream.bit --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ - --print_top_testbench \ - --print_preconfig_top_testbench \ - --print_simulation_ini ./SimulationDeck/simulation_deck.ini \ --explicit_port_mapping # Exclude signal initialization since it does not help simulator converge # due to the lack of reset pins for flip-flops diff --git a/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga b/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga index 1318a22..59b4638 100644 --- a/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga +++ b/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga @@ -53,11 +53,9 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC \ +write_full_testbench --file ./SRC \ + --bitstream fabric_bitstream.bit --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ - --print_top_testbench \ - --print_preconfig_top_testbench \ - --print_simulation_ini ./SimulationDeck/simulation_deck.ini \ --explicit_port_mapping # Exclude signal initialization since it does not help simulator converge # due to the lack of reset pins for flip-flops From 56dd34da8612788684dc44e14874d83fe69f456e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 9 Jun 2021 19:43:28 -0600 Subject: [PATCH 2/2] [Script] Update script due to deprecation of 'write_verilog_testbench' --- .../generate_testbench.openfpga | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/generate_testbench.openfpga b/FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/generate_testbench.openfpga index a7f6eec..8ac671b 100644 --- a/FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/generate_testbench.openfpga +++ b/FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/generate_testbench.openfpga @@ -44,13 +44,10 @@ build_fabric_bitstream write_fabric_bitstream --format plain_text --file fabric_bitstream.bit write_fabric_bitstream --format xml --file fabric_bitstream.xml -write_verilog_testbench \ - --file ./SRC \ - --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ - --print_top_testbench \ - --print_preconfig_top_testbench \ - --print_simulation_ini ./SimulationDeck/simulation_deck.ini \ - --explicit_port_mapping +write_full_testbench --file ./SRC \ + --bitstream fabric_bitstream.bit + --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ + --explicit_port_mapping # Finish and exit OpenFPGA -exit \ No newline at end of file +exit