From 44a68c888d9b7b2b1c6b29e20baf4bc70e6c1a76 Mon Sep 17 00:00:00 2001
From: Tarachand Pagarani <tpagarani@quicklogic.com>
Date: Tue, 8 Dec 2020 11:17:31 -0800
Subject: [PATCH] remove dedicated VCC/GND tiles and pb_type

---
 ...routing_skywater130nm_fdhd_cc_openfpga.xml |  6 --
 ARCH/vpr_arch/ql_ap3_8x8_arch_vpr_routing.xml | 59 -------------------
 2 files changed, 65 deletions(-)

diff --git a/ARCH/openfpga_arch_template/ql_ap3_8x8_arch_vpr_routing_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/ql_ap3_8x8_arch_vpr_routing_skywater130nm_fdhd_cc_openfpga.xml
index 5256312..515fa04 100644
--- a/ARCH/openfpga_arch_template/ql_ap3_8x8_arch_vpr_routing_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/ql_ap3_8x8_arch_vpr_routing_skywater130nm_fdhd_cc_openfpga.xml
@@ -247,8 +247,6 @@
     <pb_type name="SUPER_LOGIC_CELL.LC[PHYSICAL].PHYSICAL.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
     <pb_type name="SUPER_LOGIC_CELL.LC[PHYSICAL].PHYSICAL.ff" circuit_model_name="sky130_fd_sc_hd__sdfxtp_1"/>
     <pb_type name="SUPER_LOGIC_CELL[default].LC[PHYSICAL].PHYSICAL[default].frac_logic[default].carry_follower" circuit_model_name="sky130_fd_sc_hd__mux2_1_wrapper"/>
-    <pb_type name="LOGIC_1[default].logic_1" circuit_model_name="LOGIC_VDD"/>
-    <pb_type name="LOGIC_0[default].gnd" circuit_model_name="LOGIC_GND"/>
     <!-- BEGIN Binding operating pb_types in mode 'ble4' -->
     <pb_type name="SUPER_LOGIC_CELL.LC[DEFAULT].DEFAULT.lut_part[VPR_LUT4].VPR_LUT4.lut_inst.lut" physical_pb_type_name="SUPER_LOGIC_CELL.LC[PHYSICAL].PHYSICAL.frac_logic.frac_lut4" mode_bits="0">
       <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
@@ -258,9 +256,5 @@
     <pb_type name="SUPER_LOGIC_CELL.LC[DEFAULT].DEFAULT.ff" physical_pb_type_name="SUPER_LOGIC_CELL.LC[PHYSICAL].PHYSICAL.ff"/>
     <!-- END Binding operating pb_types in mode 'ble4' -->
 
-    <!-- physical pb_type binding in complex block LOGIC1 -->
-    <pb_type name="LOGIC_1.logic_1" circuit_model_name="LOGIC_VDD"/> 
-    <!-- physical pb_type binding in complex block LOGIC0 -->
-    <pb_type name="LOGIC_0.gnd" circuit_model_name="LOGIC_GND"/> 
   </pb_type_annotations>
 </openfpga_architecture>
diff --git a/ARCH/vpr_arch/ql_ap3_8x8_arch_vpr_routing.xml b/ARCH/vpr_arch/ql_ap3_8x8_arch_vpr_routing.xml
index 72d7146..34545f3 100644
--- a/ARCH/vpr_arch/ql_ap3_8x8_arch_vpr_routing.xml
+++ b/ARCH/vpr_arch/ql_ap3_8x8_arch_vpr_routing.xml
@@ -37,18 +37,6 @@
                 <port name="cout"/>
             </output_ports>
         </model>
-        <model name="logic_1">
-            <input_ports/>
-            <output_ports>
-                <port name="a"/>
-            </output_ports>
-        </model>
-        <model name="logic_0">
-            <input_ports/>
-            <output_ports>
-                <port name="a"/>
-            </output_ports>
-        </model>
     </models>
     <tiles>
         <tile capacity="8" name="IO">
@@ -132,32 +120,6 @@
                 </site>
             </equivalent_sites>
         </tile>
-        <tile capacity="1" name="TL-VCC">
-            <switchbox_locations pattern="all"/>
-            <pinlocations pattern="custom">
-                <loc side="right">TL-VCC.VCC</loc>
-            </pinlocations>
-            <fc in_type="frac" in_val="0.20" out_type="frac" out_val="0.25"/>
-            <equivalent_sites>
-                <site pb_type="LOGIC_1" pin_mapping="custom">
-                    <direct from="TL-VCC.VCC" to="LOGIC_1.a"/>
-                </site>
-            </equivalent_sites>
-            <output name="VCC" num_pins="1"/>
-        </tile>
-        <tile capacity="1" name="TL-GND">
-            <switchbox_locations pattern="all"/>
-            <pinlocations pattern="custom">
-                <loc side="right">TL-GND.GND</loc>
-            </pinlocations>
-            <fc in_type="frac" in_val="0.20" out_type="frac" out_val="0.25"/>
-            <equivalent_sites>
-                <site pb_type="LOGIC_0" pin_mapping="custom">
-                    <direct from="TL-GND.GND" to="LOGIC_0.a"/>
-                </site>
-            </equivalent_sites>
-            <output name="GND" num_pins="1"/>
-        </tile>
     </tiles>
     <layout>
         <fixed_layout height="12" name="8x8" width="12">
@@ -173,9 +135,6 @@
             <region endx="W-3" endy="H-2" priority="20" startx="2" starty="H-2" type="IO"/>
             <!-- Right IOs -->
             <region endx="W-2" endy="H-3" priority="20" startx="W-2" starty="2" type="IO"/>
-            <!-- Const sources -->
-            <single priority="100" type="TL-VCC" x="1" y="1"/>
-            <single priority="100" type="TL-GND" x="1" y="H-2"/>
         </fixed_layout>
     </layout>
     <device>
@@ -549,24 +508,6 @@
                 <direct input="LC[7].FZ" name="SUPER_LOGIC_CELL-FZ[7]" output="SUPER_LOGIC_CELL.FZ[7]"/>
             </interconnect>
         </pb_type>
-        <pb_type name="LOGIC_1">
-            <output name="a" num_pins="1"/>
-            <pb_type blif_model=".subckt logic_1" name="logic_1" num_pb="1">
-                <output name="a" num_pins="1"/>
-            </pb_type>
-            <interconnect>
-                <direct input="logic_1.a" name="LOGIC_1-a" output="LOGIC_1.a"/>
-            </interconnect>
-        </pb_type>
-        <pb_type name="LOGIC_0">
-            <output name="a" num_pins="1"/>
-            <pb_type blif_model=".subckt logic_0" name="gnd" num_pb="1">
-                <output name="a" num_pins="1"/>
-            </pb_type>
-            <interconnect>
-                <direct input="gnd.a" name="LOGIC_0-a" output="LOGIC_0.a"/>
-            </interconnect>
-        </pb_type>
     </complexblocklist>
 </architecture>