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Fixed global signal

This commit is contained in:
Ganesh Gore 2023-03-01 21:32:43 -07:00
parent 28781e8762
commit 44a0f0d2c9
14 changed files with 841 additions and 557 deletions
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5
SOFA_A/CommonFiles/generate_global_signals_connectivity.py
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@ -27,6 +27,7 @@ def save_svg_with_background(svg, filename, show_markers=False):
scalex, scaley = 1.02, 1.02
tx, ty = -7.5, -7.3
tx, ty = 5.2, 5.2
tx, ty = -5.2, -5.2
# Add main group
main_group = [e for e in svg.elements if e.get_id() == "main"][0]
main_group["transform"] = f"scale({scalex},-{scaley}) translate({tx}, {ty})"
@ -48,8 +49,8 @@ def main():
"""
Main method to generate connection patterns
"""
GRID_W = FPGA_SIZE_X
GRID_H = FPGA_SIZE_Y
GRID_W = FPGA_SIZE_X + 1
GRID_H = FPGA_SIZE_Y + 1
# ==========================================================================
# reset and test_enable connection

984
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_top.v
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File diff suppressed because it is too large Load Diff

12
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_right_tile.v
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@ -9,7 +9,9 @@ module bottom_right_tile
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset,
prog_reset_top_in,
reset_top_in,
test_enable_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
@ -41,7 +43,9 @@ module bottom_right_tile
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset;
input prog_reset_top_in;
input reset_top_in;
input test_enable_top_in;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@ -82,6 +86,9 @@ module bottom_right_tile
wire isol_n;
wire prog_clk;
wire prog_reset;
wire prog_reset_top_in;
wire reset_top_in;
wire test_enable_top_in;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@ -99,6 +106,7 @@ module bottom_right_tile
wire top_width_0_height_0_subtile_2__pin_inpad_0_;
wire top_width_0_height_0_subtile_3__pin_inpad_0_;
assign prog_reset = prog_reset_top_in;
cbx_1__0_ cbx_8__0_
(
.ccff_head(ccff_head),

74
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/right_tile.v
View File

@ -12,9 +12,15 @@ module right_tile
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset,
reset,
test_enable,
prog_reset_bottom_in,
prog_reset_left_in,
prog_reset_top_in,
reset_bottom_in,
reset_right_in,
reset_top_in,
test_enable_bottom_in,
test_enable_right_in,
test_enable_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
@ -45,6 +51,11 @@ module right_tile
left_width_0_height_0_subtile_1__pin_inpad_0_,
left_width_0_height_0_subtile_2__pin_inpad_0_,
left_width_0_height_0_subtile_3__pin_inpad_0_,
prog_reset_bottom_out,
prog_reset_top_out,
reset_bottom_out,
reset_left_out,
reset_top_out,
right_width_0_height_0_subtile_0__pin_O_10_,
right_width_0_height_0_subtile_0__pin_O_11_,
right_width_0_height_0_subtile_0__pin_O_12_,
@ -53,6 +64,9 @@ module right_tile
right_width_0_height_0_subtile_0__pin_O_15_,
right_width_0_height_0_subtile_0__pin_O_8_,
right_width_0_height_0_subtile_0__pin_O_9_,
test_enable_bottom_out,
test_enable_left_out,
test_enable_top_out,
top_width_0_height_0_subtile_0__pin_O_0_,
top_width_0_height_0_subtile_0__pin_O_1_,
top_width_0_height_0_subtile_0__pin_O_2_,
@ -73,9 +87,15 @@ module right_tile
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset;
input reset;
input test_enable;
input prog_reset_bottom_in;
input prog_reset_left_in;
input prog_reset_top_in;
input reset_bottom_in;
input reset_right_in;
input reset_top_in;
input test_enable_bottom_in;
input test_enable_right_in;
input test_enable_top_in;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@ -106,6 +126,11 @@ module right_tile
output left_width_0_height_0_subtile_1__pin_inpad_0_;
output left_width_0_height_0_subtile_2__pin_inpad_0_;
output left_width_0_height_0_subtile_3__pin_inpad_0_;
output prog_reset_bottom_out;
output prog_reset_top_out;
output reset_bottom_out;
output reset_left_out;
output reset_top_out;
output right_width_0_height_0_subtile_0__pin_O_10_;
output right_width_0_height_0_subtile_0__pin_O_11_;
output right_width_0_height_0_subtile_0__pin_O_12_;
@ -114,6 +139,9 @@ module right_tile
output right_width_0_height_0_subtile_0__pin_O_15_;
output right_width_0_height_0_subtile_0__pin_O_8_;
output right_width_0_height_0_subtile_0__pin_O_9_;
output test_enable_bottom_out;
output test_enable_left_out;
output test_enable_top_out;
output top_width_0_height_0_subtile_0__pin_O_0_;
output top_width_0_height_0_subtile_0__pin_O_1_;
output top_width_0_height_0_subtile_0__pin_O_2_;
@ -187,7 +215,18 @@ module right_tile
wire left_width_0_height_0_subtile_3__pin_inpad_0_;
wire prog_clk;
wire prog_reset;
wire prog_reset_bottom_in;
wire prog_reset_bottom_out;
wire prog_reset_left_in;
wire prog_reset_top_in;
wire prog_reset_top_out;
wire reset;
wire reset_bottom_in;
wire reset_bottom_out;
wire reset_left_out;
wire reset_right_in;
wire reset_top_in;
wire reset_top_out;
wire right_width_0_height_0_subtile_0__pin_O_10_;
wire right_width_0_height_0_subtile_0__pin_O_11_;
wire right_width_0_height_0_subtile_0__pin_O_12_;
@ -197,6 +236,12 @@ module right_tile
wire right_width_0_height_0_subtile_0__pin_O_8_;
wire right_width_0_height_0_subtile_0__pin_O_9_;
wire test_enable;
wire test_enable_bottom_in;
wire test_enable_bottom_out;
wire test_enable_left_out;
wire test_enable_right_in;
wire test_enable_top_in;
wire test_enable_top_out;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@ -221,6 +266,23 @@ module right_tile
wire top_width_0_height_0_subtile_0__pin_reg_in_0_;
wire top_width_0_height_0_subtile_0__pin_sc_in_0_;
assign prog_reset = prog_reset_bottom_in;
assign prog_reset_top_in = prog_reset_left_in;
assign prog_reset_top_out = prog_reset;
assign prog_reset_bottom_in = prog_reset_top_in;
assign prog_reset_bottom_out = prog_reset_top_out;
assign reset = reset_bottom_in;
assign reset_top_out = reset_left_out;
assign reset_left_out = reset;
assign reset_top_in = reset_right_in;
assign reset_bottom_in = reset_top_in;
assign reset_bottom_out = reset_top_out;
assign test_enable = test_enable_bottom_in;
assign test_enable_top_out = test_enable_left_out;
assign test_enable_top_in = test_enable_right_in;
assign test_enable_left_out = test_enable;
assign test_enable_bottom_in = test_enable_top_in;
assign test_enable_bottom_out = test_enable_top_out;
cbx_1__1_ cbx_8__1_
(
.ccff_head(ccff_tail_2),

12
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_left_tile.v
View File

@ -9,7 +9,8 @@ module top_left_tile
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset,
prog_reset_bottom_in,
reset_bottom_in,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@ -22,6 +23,7 @@ module top_left_tile
right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
test_enable_bottom_in,
ccff_tail,
ccff_tail_0,
chanx_right_out,
@ -41,7 +43,8 @@ module top_left_tile
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset;
input prog_reset_bottom_in;
input reset_bottom_in;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -54,6 +57,7 @@ module top_left_tile
input right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
input right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
input right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
input test_enable_bottom_in;
output ccff_tail;
output ccff_tail_0;
output [29:0]chanx_right_out;
@ -81,6 +85,8 @@ module top_left_tile
wire isol_n;
wire prog_clk;
wire prog_reset;
wire prog_reset_bottom_in;
wire reset_bottom_in;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -97,7 +103,9 @@ module top_left_tile
wire right_width_0_height_0_subtile_1__pin_inpad_0_;
wire right_width_0_height_0_subtile_2__pin_inpad_0_;
wire right_width_0_height_0_subtile_3__pin_inpad_0_;
wire test_enable_bottom_in;
assign prog_reset = prog_reset_bottom_in;
cby_0__1_ cby_0__8_
(
.ccff_head_0(ccff_head_0),

18
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_right_tile.v
View File

@ -11,9 +11,9 @@ module top_right_tile
gfpga_pad_io_soc_in_0,
isol_n,
prog_clk,
prog_reset,
reset,
test_enable,
prog_reset_bottom_in,
reset_bottom_in,
test_enable_bottom_in,
top_width_0_height_0_subtile_0__pin_cin_0_,
top_width_0_height_0_subtile_0__pin_reg_in_0_,
top_width_0_height_0_subtile_0__pin_sc_in_0_,
@ -63,9 +63,9 @@ module top_right_tile
input [3:0]gfpga_pad_io_soc_in_0;
input isol_n;
input prog_clk;
input prog_reset;
input reset;
input test_enable;
input prog_reset_bottom_in;
input reset_bottom_in;
input test_enable_bottom_in;
input top_width_0_height_0_subtile_0__pin_cin_0_;
input top_width_0_height_0_subtile_0__pin_reg_in_0_;
input top_width_0_height_0_subtile_0__pin_sc_in_0_;
@ -173,7 +173,9 @@ module top_right_tile
wire left_width_0_height_0_subtile_3__pin_inpad_0_;
wire prog_clk;
wire prog_reset;
wire prog_reset_bottom_in;
wire reset;
wire reset_bottom_in;
wire right_width_0_height_0_subtile_0__pin_O_10_;
wire right_width_0_height_0_subtile_0__pin_O_11_;
wire right_width_0_height_0_subtile_0__pin_O_12_;
@ -183,6 +185,7 @@ module top_right_tile
wire right_width_0_height_0_subtile_0__pin_O_8_;
wire right_width_0_height_0_subtile_0__pin_O_9_;
wire test_enable;
wire test_enable_bottom_in;
wire top_width_0_height_0_subtile_0__pin_O_0_;
wire top_width_0_height_0_subtile_0__pin_O_1_;
wire top_width_0_height_0_subtile_0__pin_O_2_;
@ -195,6 +198,9 @@ module top_right_tile
wire top_width_0_height_0_subtile_0__pin_reg_in_0_;
wire top_width_0_height_0_subtile_0__pin_sc_in_0_;
assign prog_reset = prog_reset_bottom_in;
assign reset = reset_bottom_in;
assign test_enable = test_enable_bottom_in;
cbx_1__8_ cbx_8__8_
(
.ccff_head_0(ccff_tail_2),

18
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_tile.v
View File

@ -11,8 +11,8 @@ module top_tile
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset,
reset,
prog_reset_bottom_in,
reset_bottom_in,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@ -25,7 +25,7 @@ module top_tile
right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
test_enable,
test_enable_bottom_in,
top_width_0_height_0_subtile_0__pin_cin_0_,
top_width_0_height_0_subtile_0__pin_reg_in_0_,
top_width_0_height_0_subtile_0__pin_sc_in_0_,
@ -70,8 +70,8 @@ module top_tile
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset;
input reset;
input prog_reset_bottom_in;
input reset_bottom_in;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -84,7 +84,7 @@ module top_tile
input right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
input right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
input right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
input test_enable;
input test_enable_bottom_in;
input top_width_0_height_0_subtile_0__pin_cin_0_;
input top_width_0_height_0_subtile_0__pin_reg_in_0_;
input top_width_0_height_0_subtile_0__pin_sc_in_0_;
@ -181,7 +181,9 @@ module top_tile
wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
wire prog_clk;
wire prog_reset;
wire prog_reset_bottom_in;
wire reset;
wire reset_bottom_in;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -203,6 +205,7 @@ module top_tile
wire right_width_0_height_0_subtile_0__pin_O_8_;
wire right_width_0_height_0_subtile_0__pin_O_9_;
wire test_enable;
wire test_enable_bottom_in;
wire top_width_0_height_0_subtile_0__pin_O_0_;
wire top_width_0_height_0_subtile_0__pin_O_1_;
wire top_width_0_height_0_subtile_0__pin_O_2_;
@ -215,6 +218,9 @@ module top_tile
wire top_width_0_height_0_subtile_0__pin_reg_in_0_;
wire top_width_0_height_0_subtile_0__pin_sc_in_0_;
assign prog_reset = prog_reset_bottom_in;
assign reset = reset_bottom_in;
assign test_enable = test_enable_bottom_in;
cbx_1__8_ cbx_1__8_
(
.ccff_head_0(ccff_tail_2),

9
SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/prog_reset_ports.txt
View File

@ -3,6 +3,11 @@ Module | In | Out
Module | L R T B | L R T B
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
bottom_left_tile | - - 1 - | - - - -
bottom_right_tile | - - 1 - | - - - -
bottom_tile | - - 7 - | - - - -
left_tile | 1 - 3 3 | - 1 3 4
tile | 7 - 21 21 | - 6 21 28
left_tile | 1 - 3 3 | - 1 4 4
right_tile | 1 - 3 3 | - - 4 4
tile | 7 - 21 21 | - 7 28 28
top_left_tile | - - - 1 | - - - -
top_right_tile | - - - 1 | - - - -
top_tile | - - - 7 | - - - -

9
SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/reset_ports.txt
View File

@ -3,6 +3,11 @@ Module | In | Out
Module | L R T B | L R T B
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
bottom_left_tile | - - 1 - | - - - -
bottom_right_tile | - - 1 - | - - - -
bottom_tile | - - 7 - | - - - -
left_tile | - 1 3 3 | - - 3 4
tile | - 7 21 21 | 7 - 21 28
left_tile | - 1 3 3 | - - 4 4
right_tile | - 1 3 3 | 1 - 4 4
tile | - 7 21 21 | 7 - 28 28
top_left_tile | - - - 1 | - - - -
top_right_tile | - - - 1 | - - - -
top_tile | - - - 7 | - - - -

9
SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/test_enable_ports.txt
View File

@ -3,6 +3,11 @@ Module | In | Out
Module | L R T B | L R T B
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
bottom_left_tile | - - 1 - | - - - -
bottom_right_tile | - - 1 - | - - - -
bottom_tile | - - 7 - | - - - -
left_tile | - 1 3 3 | - - 3 4
tile | - 7 21 21 | 7 - 21 28
left_tile | - 1 3 3 | - - 4 4
right_tile | - 1 3 3 | 1 - 4 4
tile | - 7 21 21 | 7 - 28 28
top_left_tile | - - - 1 | - - - -
top_right_tile | - - - 1 | - - - -
top_tile | - - - 7 | - - - -

61
SOFA_A/FPGA88_SOFA_A/release/svg/config_enable_pattern.svg
View File

@ -730,7 +730,7 @@ symbol[id*="io_"] * { fill:#f8b155;}
<text alignment-baseline="middle" text-anchor="middle" transform="scale(1,-1)" x="131.0" y="-117.0">io_right_9__8_</text>
</g>
</g>
<g id="main" transform="scale(1.02,-1.02) translate(5.2, 5.2)">
<g id="main" transform="scale(1.02,-1.02) translate(-5.2, -5.2)">
<line class="connection top" stroke=" black" x1="0" x2="14" y1="69" y2="69"/>
<line class="connection same" stroke=" black" x1="14" x2="14" y1="69" y2="55"/>
<line class="connection same" stroke=" black" x1="14" x2="14" y1="55" y2="41"/>
@ -739,6 +739,7 @@ symbol[id*="io_"] * { fill:#f8b155;}
<line class="connection same" stroke=" black" x1="14" x2="14" y1="69" y2="83"/>
<line class="connection same" stroke=" black" x1="14" x2="14" y1="83" y2="97"/>
<line class="connection same" stroke=" black" x1="14" x2="14" y1="97" y2="110"/>
<line class="connection same" stroke=" black" x1="14" x2="14" y1="110" y2="124"/>
<line class="connection same" stroke=" black" x1="14" x2="28" y1="69" y2="69"/>
<line class="connection same" stroke=" black" x1="28" x2="28" y1="69" y2="55"/>
<line class="connection same" stroke=" black" x1="28" x2="28" y1="55" y2="41"/>
@ -747,6 +748,7 @@ symbol[id*="io_"] * { fill:#f8b155;}
<line class="connection same" stroke=" black" x1="28" x2="28" y1="69" y2="83"/>
<line class="connection same" stroke=" black" x1="28" x2="28" y1="83" y2="97"/>
<line class="connection same" stroke=" black" x1="28" x2="28" y1="97" y2="110"/>
<line class="connection same" stroke=" black" x1="28" x2="28" y1="110" y2="124"/>
<line class="connection same" stroke=" black" x1="28" x2="41" y1="69" y2="69"/>
<line class="connection same" stroke=" black" x1="41" x2="41" y1="69" y2="55"/>
<line class="connection same" stroke=" black" x1="41" x2="41" y1="55" y2="41"/>
@ -755,6 +757,7 @@ symbol[id*="io_"] * { fill:#f8b155;}
<line class="connection same" stroke=" black" x1="41" x2="41" y1="69" y2="83"/>
<line class="connection same" stroke=" black" x1="41" x2="41" y1="83" y2="97"/>
<line class="connection same" stroke=" black" x1="41" x2="41" y1="97" y2="110"/>
<line class="connection same" stroke=" black" x1="41" x2="41" y1="110" y2="124"/>
<line class="connection same" stroke=" black" x1="41" x2="55" y1="69" y2="69"/>
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SOFA_A/FPGA88_SOFA_A/release/svg/reset_pattern.svg
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<line class="connection same" stroke=" black" x1="83" x2="83" y1="83" y2="97"/>
<line class="connection same" stroke=" black" x1="83" x2="83" y1="97" y2="110"/>
<line class="connection same" stroke=" black" x1="83" x2="83" y1="110" y2="124"/>
<line class="connection same" stroke=" black" x1="83" x2="83" y1="69" y2="55"/>
<line class="connection same" stroke=" black" x1="83" x2="83" y1="55" y2="41"/>
<line class="connection same" stroke=" black" x1="83" x2="83" y1="41" y2="28"/>
@ -759,6 +771,7 @@ symbol[id*="io_"] * { fill:#f8b155;}
<line class="connection same" stroke=" black" x1="69" x2="69" y1="69" y2="83"/>
<line class="connection same" stroke=" black" x1="69" x2="69" y1="83" y2="97"/>
<line class="connection same" stroke=" black" x1="69" x2="69" y1="97" y2="110"/>
<line class="connection same" stroke=" black" x1="69" x2="69" y1="110" y2="124"/>
<line class="connection same" stroke=" black" x1="69" x2="69" y1="69" y2="55"/>
<line class="connection same" stroke=" black" x1="69" x2="69" y1="55" y2="41"/>
<line class="connection same" stroke=" black" x1="69" x2="69" y1="41" y2="28"/>
@ -767,6 +780,7 @@ symbol[id*="io_"] * { fill:#f8b155;}
<line class="connection same" stroke=" black" x1="55" x2="55" y1="69" y2="83"/>
<line class="connection same" stroke=" black" x1="55" x2="55" y1="83" y2="97"/>
<line class="connection same" stroke=" black" x1="55" x2="55" y1="97" y2="110"/>
<line class="connection same" stroke=" black" x1="55" x2="55" y1="110" y2="124"/>
<line class="connection same" stroke=" black" x1="55" x2="55" y1="69" y2="55"/>
<line class="connection same" stroke=" black" x1="55" x2="55" y1="55" y2="41"/>
<line class="connection same" stroke=" black" x1="55" x2="55" y1="41" y2="28"/>
@ -775,6 +789,7 @@ symbol[id*="io_"] * { fill:#f8b155;}
<line class="connection same" stroke=" black" x1="41" x2="41" y1="69" y2="83"/>
<line class="connection same" stroke=" black" x1="41" x2="41" y1="83" y2="97"/>
<line class="connection same" stroke=" black" x1="41" x2="41" y1="97" y2="110"/>
<line class="connection same" stroke=" black" x1="41" x2="41" y1="110" y2="124"/>
<line class="connection same" stroke=" black" x1="41" x2="41" y1="69" y2="55"/>
<line class="connection same" stroke=" black" x1="41" x2="41" y1="55" y2="41"/>
<line class="connection same" stroke=" black" x1="41" x2="41" y1="41" y2="28"/>
@ -783,6 +798,7 @@ symbol[id*="io_"] * { fill:#f8b155;}
<line class="connection same" stroke=" black" x1="28" x2="28" y1="69" y2="83"/>
<line class="connection same" stroke=" black" x1="28" x2="28" y1="83" y2="97"/>
<line class="connection same" stroke=" black" x1="28" x2="28" y1="97" y2="110"/>
<line class="connection same" stroke=" black" x1="28" x2="28" y1="110" y2="124"/>
<line class="connection same" stroke=" black" x1="28" x2="28" y1="69" y2="55"/>
<line class="connection same" stroke=" black" x1="28" x2="28" y1="55" y2="41"/>
<line class="connection same" stroke=" black" x1="28" x2="28" y1="41" y2="28"/>
@ -791,33 +807,36 @@ symbol[id*="io_"] * { fill:#f8b155;}
<line class="connection same" stroke=" black" x1="14" x2="14" y1="69" y2="83"/>
<line class="connection same" stroke=" black" x1="14" x2="14" y1="83" y2="97"/>
<line class="connection same" stroke=" black" x1="14" x2="14" y1="97" y2="110"/>
<line class="connection same" stroke=" black" x1="14" x2="14" y1="110" y2="124"/>
<line class="connection same" stroke=" black" x1="14" x2="14" y1="69" y2="55"/>
<line class="connection same" stroke=" black" x1="14" x2="14" y1="55" y2="41"/>
<line class="connection same" stroke=" black" x1="14" x2="14" y1="41" y2="28"/>
<line class="connection same" stroke=" black" x1="14" x2="14" y1="28" y2="14"/>
<g id="text">
<text alignment-baseline="middle" class="moduleLabel" fill="black" font-size="11.040000000000001" text-anchor="middle" transform="scale(1,-1)" x="62.1" y="6.9">8 x 8 FPGA </text>
<text alignment-baseline="middle" class="moduleLabel" fill="black" font-size="12.420000000000002" text-anchor="middle" transform="scale(1,-1)" x="69.0" y="6.9">9 x 9 FPGA </text>
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Side by Side Swipe Overlay

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After

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63
SOFA_A/FPGA88_SOFA_A/release/svg/test_enable_pattern.svg
View File

@ -730,11 +730,21 @@ symbol[id*="io_"] * { fill:#f8b155;}
<text alignment-baseline="middle" text-anchor="middle" transform="scale(1,-1)" x="131.0" y="-117.0">io_right_9__8_</text>
</g>
</g>
<g id="main" transform="scale(1.02,-1.02) translate(5.2, 5.2)">
<line class="connection top" stroke=" black" x1="124" x2="110" y1="69" y2="69"/>
<g id="main" transform="scale(1.02,-1.02) translate(-5.2, -5.2)">
<line class="connection top" stroke=" black" x1="138" x2="124" y1="69" y2="69"/>
<line class="connection same" stroke=" black" x1="124" x2="124" y1="69" y2="83"/>
<line class="connection same" stroke=" black" x1="124" x2="124" y1="83" y2="97"/>
<line class="connection same" stroke=" black" x1="124" x2="124" y1="97" y2="110"/>
<line class="connection same" stroke=" black" x1="124" x2="124" y1="110" y2="124"/>
<line class="connection same" stroke=" black" x1="124" x2="124" y1="69" y2="55"/>
<line class="connection same" stroke=" black" x1="124" x2="124" y1="55" y2="41"/>
<line class="connection same" stroke=" black" x1="124" x2="124" y1="41" y2="28"/>
<line class="connection same" stroke=" black" x1="124" x2="124" y1="28" y2="14"/>
<line class="connection same" stroke=" black" x1="124" x2="110" y1="69" y2="69"/>
<line class="connection same" stroke=" black" x1="110" x2="110" y1="69" y2="83"/>
<line class="connection same" stroke=" black" x1="110" x2="110" y1="83" y2="97"/>
<line class="connection same" stroke=" black" x1="110" x2="110" y1="97" y2="110"/>
<line class="connection same" stroke=" black" x1="110" x2="110" y1="110" y2="124"/>
<line class="connection same" stroke=" black" x1="110" x2="110" y1="69" y2="55"/>
<line class="connection same" stroke=" black" x1="110" x2="110" y1="55" y2="41"/>
<line class="connection same" stroke=" black" x1="110" x2="110" y1="41" y2="28"/>
@ -743,6 +753,7 @@ symbol[id*="io_"] * { fill:#f8b155;}
<line class="connection same" stroke=" black" x1="97" x2="97" y1="69" y2="83"/>
<line class="connection same" stroke=" black" x1="97" x2="97" y1="83" y2="97"/>
<line class="connection same" stroke=" black" x1="97" x2="97" y1="97" y2="110"/>
<line class="connection same" stroke=" black" x1="97" x2="97" y1="110" y2="124"/>
<line class="connection same" stroke=" black" x1="97" x2="97" y1="69" y2="55"/>
<line class="connection same" stroke=" black" x1="97" x2="97" y1="55" y2="41"/>
<line class="connection same" stroke=" black" x1="97" x2="97" y1="41" y2="28"/>
@ -751,6 +762,7 @@ symbol[id*="io_"] * { fill:#f8b155;}
<line class="connection same" stroke=" black" x1="83" x2="83" y1="69" y2="83"/>
<line class="connection same" stroke=" black" x1="83" x2="83" y1="83" y2="97"/>
<line class="connection same" stroke=" black" x1="83" x2="83" y1="97" y2="110"/>
<line class="connection same" stroke=" black" x1="83" x2="83" y1="110" y2="124"/>
<line class="connection same" stroke=" black" x1="83" x2="83" y1="69" y2="55"/>
<line class="connection same" stroke=" black" x1="83" x2="83" y1="55" y2="41"/>
<line class="connection same" stroke=" black" x1="83" x2="83" y1="41" y2="28"/>
@ -759,6 +771,7 @@ symbol[id*="io_"] * { fill:#f8b155;}
<line class="connection same" stroke=" black" x1="69" x2="69" y1="69" y2="83"/>
<line class="connection same" stroke=" black" x1="69" x2="69" y1="83" y2="97"/>
<line class="connection same" stroke=" black" x1="69" x2="69" y1="97" y2="110"/>
<line class="connection same" stroke=" black" x1="69" x2="69" y1="110" y2="124"/>
<line class="connection same" stroke=" black" x1="69" x2="69" y1="69" y2="55"/>
<line class="connection same" stroke=" black" x1="69" x2="69" y1="55" y2="41"/>
<line class="connection same" stroke=" black" x1="69" x2="69" y1="41" y2="28"/>
@ -767,6 +780,7 @@ symbol[id*="io_"] * { fill:#f8b155;}
<line class="connection same" stroke=" black" x1="55" x2="55" y1="69" y2="83"/>
<line class="connection same" stroke=" black" x1="55" x2="55" y1="83" y2="97"/>
<line class="connection same" stroke=" black" x1="55" x2="55" y1="97" y2="110"/>
<line class="connection same" stroke=" black" x1="55" x2="55" y1="110" y2="124"/>
<line class="connection same" stroke=" black" x1="55" x2="55" y1="69" y2="55"/>
<line class="connection same" stroke=" black" x1="55" x2="55" y1="55" y2="41"/>
<line class="connection same" stroke=" black" x1="55" x2="55" y1="41" y2="28"/>
@ -775,6 +789,7 @@ symbol[id*="io_"] * { fill:#f8b155;}
<line class="connection same" stroke=" black" x1="41" x2="41" y1="69" y2="83"/>
<line class="connection same" stroke=" black" x1="41" x2="41" y1="83" y2="97"/>
<line class="connection same" stroke=" black" x1="41" x2="41" y1="97" y2="110"/>
<line class="connection same" stroke=" black" x1="41" x2="41" y1="110" y2="124"/>
<line class="connection same" stroke=" black" x1="41" x2="41" y1="69" y2="55"/>
<line class="connection same" stroke=" black" x1="41" x2="41" y1="55" y2="41"/>
<line class="connection same" stroke=" black" x1="41" x2="41" y1="41" y2="28"/>
@ -783,6 +798,7 @@ symbol[id*="io_"] * { fill:#f8b155;}
<line class="connection same" stroke=" black" x1="28" x2="28" y1="69" y2="83"/>
<line class="connection same" stroke=" black" x1="28" x2="28" y1="83" y2="97"/>
<line class="connection same" stroke=" black" x1="28" x2="28" y1="97" y2="110"/>
<line class="connection same" stroke=" black" x1="28" x2="28" y1="110" y2="124"/>
<line class="connection same" stroke=" black" x1="28" x2="28" y1="69" y2="55"/>
<line class="connection same" stroke=" black" x1="28" x2="28" y1="55" y2="41"/>
<line class="connection same" stroke=" black" x1="28" x2="28" y1="41" y2="28"/>
@ -791,33 +807,36 @@ symbol[id*="io_"] * { fill:#f8b155;}
<line class="connection same" stroke=" black" x1="14" x2="14" y1="69" y2="83"/>
<line class="connection same" stroke=" black" x1="14" x2="14" y1="83" y2="97"/>
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<line class="connection same" stroke=" black" x1="14" x2="14" y1="28" y2="14"/>
<g id="text">
<text alignment-baseline="middle" class="moduleLabel" fill="black" font-size="11.040000000000001" text-anchor="middle" transform="scale(1,-1)" x="62.1" y="6.9">8 x 8 FPGA </text>
<text alignment-baseline="middle" class="moduleLabel" fill="black" font-size="12.420000000000002" text-anchor="middle" transform="scale(1,-1)" x="69.0" y="6.9">9 x 9 FPGA </text>
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