diff --git a/.github/workflows/quick_test.sh b/.github/workflows/quick_test.sh
index d6d92dc..b3f3a05 100755
--- a/.github/workflows/quick_test.sh
+++ b/.github/workflows/quick_test.sh
@@ -12,6 +12,9 @@ set -e
 # - Run FPGA tasks to validate netlist generations 
 python3 SCRIPT/repo_setup.py --openfpga_root_path ./OpenFPGA
 
+# Post processing netlist to use custom cells  
+python3 HDL/common/custom_cell_mux_primitive_generator.py --template_netlist HDL/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/SRC/sub_module/mux_primitives.v --output_verilog HDL/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/SRC/sub_module/mux_primitives_hd.v
+
 ##############################################
 # Generate wrapper HDL codes to bridge Caravel I/Os and FPGA I/Os
 python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/caravel_fpga_wrapper_hd_template.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --output_verilog HDL/common/caravel_fpga_wrapper_hd_v1.0.v
@@ -30,3 +33,4 @@ python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_test
 # Generate wrapper testbenches from template tesbenches for scan chain tests
 python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/scff_test_post_pnr_v1.0.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --wrapper_testbench TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v
 python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/scff_test_post_pnr_v1.1.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.1.json --wrapper_testbench TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v
+