mirror of https://github.com/lnis-uofu/SOFA.git
[Testbench] Add configuration chain test benches for pre- and post- pnr simulation
This commit is contained in:
tangxifan
parent
ce91890a0e
commit
439c73d211
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//-------------------------------------------
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// Verilog Testbench for Verifying
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// Configuration Chain of a FPGA
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// Description: This test is applicable to FPGAs which have 1 configuration
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// chain. It will feed a pulse to the head of the configuration chain and
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// check if the pulse is outputted by the tail of the configuration chain
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// in a given time period
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//
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// Note: This test bench is tuned for the post PnR netlists
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// Author: Xifan TANG
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// Organization: University of Utah
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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// Design parameter for FPGA I/O sizes
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//`define FPGA_IO_SIZE 144
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//
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// Design parameter for FPGA bitstream sizes
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//`define FPGA_BITSTREAM_SIZE 65656
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module post_pnr_ccff_test;
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// ----- Local wires for global ports of FPGA fabric -----
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wire [0:0] prog_clk;
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wire [0:0] Test_en;
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wire [0:0] clk;
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// ----- Local wires for I/Os of FPGA fabric -----
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wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_SOC_IN;
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wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_SOC_OUT;
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wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_SOC_DIR;
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wire [0:0] prog_clock;
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reg [0:0] prog_clock_reg;
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wire [0:0] op_clock;
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reg [0:0] op_clock_reg;
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reg [0:0] prog_reset;
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reg [0:0] prog_set;
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reg [0:0] greset;
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reg [0:0] gset;
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// ---- Configuration-chain head -----
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reg [0:0] ccff_head;
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// ---- Configuration-chain tail -----
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wire [0:0] ccff_tail;
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// ---- Scan-chain head -----
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wire [0:0] sc_head;
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// ---- Scan-chain tail -----
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wire [0:0] sc_tail;
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wire [0:0] IO_ISOL_N;
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// ----- Counters for error checking -----
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integer num_prog_cycles = 0;
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integer num_errors = 0;
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// Indicate when configuration should be finished
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reg config_done = 0;
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initial
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begin
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config_done = 1'b0;
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end
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// ----- Begin raw programming clock signal generation -----
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initial
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begin
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prog_clock_reg[0] = 1'b0;
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end
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always
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begin
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#5 prog_clock_reg[0] = ~prog_clock_reg[0];
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end
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// ----- End raw programming clock signal generation -----
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// ----- Actual programming clock is triggered only when config_done and prog_reset are disabled -----
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assign prog_clock[0] = prog_clock_reg[0] & (~prog_reset[0]);
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// ----- Begin raw operating clock signal generation -----
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initial
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begin
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op_clock_reg[0] = 1'b0;
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end
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// ----- End raw operating clock signal generation -----
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// ----- Actual operating clock is triggered only when config_done is enabled -----
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assign op_clock[0] = op_clock_reg[0];
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// ----- Begin programming reset signal generation -----
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initial
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begin
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prog_reset[0] = 1'b1;
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#10 prog_reset[0] = 1'b0;
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end
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// ----- End programming reset signal generation -----
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// ----- Begin programming set signal generation -----
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initial
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begin
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prog_set[0] = 1'b1;
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#10 prog_set[0] = 1'b0;
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end
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// ----- End programming set signal generation -----
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// ----- Begin operating reset signal generation -----
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// ----- Reset signal is disabled always -----
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initial
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begin
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greset[0] = 1'b1;
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end
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// ----- End operating reset signal generation -----
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// ----- Begin operating set signal generation: always disabled -----
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initial
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begin
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gset[0] = 1'b0;
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end
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// ----- End operating set signal generation: always disabled -----
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// ----- Begin connecting global ports of FPGA fabric to stimuli -----
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assign clk[0] = op_clock[0];
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assign prog_clk[0] = prog_clock[0];
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assign Test_en[0] = 1'b0;
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assign sc_head[0] = 1'b0;
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assign IO_ISOL_N[0] = 1'b0;
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// ----- End connecting global ports of FPGA fabric to stimuli -----
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// ----- FPGA top-level module to be capsulated -----
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fpga_core FPGA_DUT (
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.prog_clk(prog_clk[0]),
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.Test_en(Test_en[0]),
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.clk(clk[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:`FPGA_IO_SIZE - 1]),
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.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:`FPGA_IO_SIZE - 1]),
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.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:`FPGA_IO_SIZE - 1]),
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.ccff_head(ccff_head[0]),
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.ccff_tail(ccff_tail[0]),
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.sc_head(sc_head[0]),
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.sc_tail(sc_tail[0]),
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.IO_ISOL_N(IO_ISOL_N)
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);
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// ----- Force constant '0' to FPGA I/O as this testbench only check
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// programming phase -----
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}};
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assign gfpga_pad_EMBEDDED_IO_SOC_OUT[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}};
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// Generate a pulse after programming reset is disabled (in the 2nd clock
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// cycle). Then the head of configuration chain should be always zero
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always @(negedge prog_clock[0]) begin
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ccff_head = 1'b1;
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if (0 != num_prog_cycles) begin
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ccff_head = 1'b0;
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end
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end
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// ----- Count the number of programming cycles -------
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always @(posedge prog_clock[0]) begin
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num_prog_cycles = num_prog_cycles + 1;
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// Indicate when configuration is suppose to end
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if (`FPGA_BITSTREAM_SIZE + 1 == num_prog_cycles) begin
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config_done = 1'b1;
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end
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// Check the ccff_tail when configuration is done
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if (1'b1 == config_done) begin
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if (sc_tail != 1'b1) begin
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$display("Error: sc_tail = %b", sc_tail);
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num_errors = num_errors + 1;
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end
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$display("Simulation finish with %d errors", num_errors);
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// End simulation
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$finish;
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end
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end
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endmodule
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@ -0,0 +1,181 @@
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//-------------------------------------------
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// Verilog Testbench for Verifying
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// Configuration Chain of a FPGA
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// Description: This test is applicable to FPGAs which have 1 configuration
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// chain. It will feed a pulse to the head of the configuration chain and
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// check if the pulse is outputted by the tail of the configuration chain
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// in a given time period
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//
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// Note: This test bench is tuned for the pre PnR netlists
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// Author: Xifan TANG
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// Organization: University of Utah
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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// Design parameter for FPGA I/O sizes
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//`define FPGA_IO_SIZE 144
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//
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// Design parameter for FPGA bitstream sizes
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//`define FPGA_BITSTREAM_SIZE 65656
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module pre_pnr_ccff_test;
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// ----- Local wires for global ports of FPGA fabric -----
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wire [0:0] prog_clk;
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wire [0:0] Test_en;
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wire [0:0] clk;
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// ----- Local wires for I/Os of FPGA fabric -----
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wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
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wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
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wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
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wire [0:0] prog_clock;
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reg [0:0] prog_clock_reg;
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wire [0:0] op_clock;
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reg [0:0] op_clock_reg;
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reg [0:0] prog_reset;
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reg [0:0] prog_set;
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reg [0:0] greset;
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reg [0:0] gset;
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// ---- Configuration-chain head -----
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reg [0:0] ccff_head;
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// ---- Configuration-chain tail -----
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wire [0:0] ccff_tail;
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// ---- Scan-chain head -----
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wire [0:0] sc_head;
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// ---- Scan-chain tail -----
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wire [0:0] sc_tail;
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wire [0:0] IO_ISOL_N;
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// ----- Counters for error checking -----
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integer num_prog_cycles = 0;
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integer num_errors = 0;
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// Indicate when configuration should be finished
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reg config_done = 0;
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initial
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begin
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config_done = 1'b0;
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end
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// ----- Begin raw programming clock signal generation -----
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initial
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begin
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prog_clock_reg[0] = 1'b0;
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end
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always
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begin
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#5 prog_clock_reg[0] = ~prog_clock_reg[0];
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end
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// ----- End raw programming clock signal generation -----
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// ----- Actual programming clock is triggered only when config_done and prog_reset are disabled -----
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assign prog_clock[0] = prog_clock_reg[0] & (~prog_reset[0]);
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// ----- Begin raw operating clock signal generation -----
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initial
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begin
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op_clock_reg[0] = 1'b0;
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end
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// ----- End raw operating clock signal generation -----
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// ----- Actual operating clock is triggered only when config_done is enabled -----
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assign op_clock[0] = op_clock_reg[0];
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// ----- Begin programming reset signal generation -----
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initial
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begin
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prog_reset[0] = 1'b1;
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#10 prog_reset[0] = 1'b0;
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end
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// ----- End programming reset signal generation -----
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// ----- Begin programming set signal generation -----
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initial
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begin
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prog_set[0] = 1'b1;
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#10 prog_set[0] = 1'b0;
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end
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// ----- End programming set signal generation -----
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// ----- Begin operating reset signal generation -----
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// ----- Reset signal is disabled always -----
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initial
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begin
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greset[0] = 1'b1;
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end
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// ----- End operating reset signal generation -----
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// ----- Begin operating set signal generation: always disabled -----
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initial
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begin
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gset[0] = 1'b0;
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end
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// ----- End operating set signal generation: always disabled -----
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// ----- Begin connecting global ports of FPGA fabric to stimuli -----
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assign clk[0] = op_clock[0];
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assign prog_clk[0] = prog_clock[0];
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assign Test_en[0] = 1'b0;
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assign sc_head[0] = 1'b0;
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assign IO_ISOL_N[0] = 1'b0;
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// ----- End connecting global ports of FPGA fabric to stimuli -----
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// ----- FPGA top-level module to be capsulated -----
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fpga_top FPGA_DUT (
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.prog_clk(prog_clk[0]),
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.Test_en(Test_en[0]),
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.clk(clk[0]),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1]),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1]),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:`FPGA_IO_SIZE - 1]),
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.ccff_head(ccff_head[0]),
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.ccff_tail(ccff_tail[0]),
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.IO_ISOL_N(IO_ISOL_N)
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);
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// ----- Force constant '0' to FPGA I/O as this testbench only check
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// programming phase -----
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assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}};
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assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}};
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// Generate a pulse after programming reset is disabled (in the 2nd clock
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// cycle). Then the head of configuration chain should be always zero
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always @(negedge prog_clock[0]) begin
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ccff_head = 1'b1;
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if (0 != num_prog_cycles) begin
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ccff_head = 1'b0;
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end
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end
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// ----- Count the number of programming cycles -------
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always @(posedge prog_clock[0]) begin
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num_prog_cycles = num_prog_cycles + 1;
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// Indicate when configuration is suppose to end
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if (`FPGA_BITSTREAM_SIZE + 1 == num_prog_cycles) begin
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config_done = 1'b1;
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end
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// Check the ccff_tail when configuration is done
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if (1'b1 == config_done) begin
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if (sc_tail != 1'b1) begin
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$display("Error: sc_tail = %b", sc_tail);
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num_errors = num_errors + 1;
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end
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$display("Simulation finish with %d errors", num_errors);
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// End simulation
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$finish;
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end
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end
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endmodule
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@ -0,0 +1,69 @@
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//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Netlist Summary
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// Author: Xifan TANG
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// Organization: University of Utah
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// Date: Wed Nov 11 16:01:30 2020
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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// Design parameter for FPGA I/O sizes
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`define FPGA_IO_SIZE 108
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// Design parameter for FPGA bitstream sizes
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`define FPGA_BITSTREAM_SIZE 65656
|
||||||
|
|
||||||
|
// ------ Include simulation defines -----
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
|
||||||
|
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
|
||||||
|
|
||||||
|
// ------ Include Skywater cell netlists -----
|
||||||
|
// Cells already used pre-PnR
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
|
||||||
|
|
||||||
|
// Cells added due to their use in PnR
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v"
|
||||||
|
|
||||||
|
// ------ Include fabric top-level netlists -----
|
||||||
|
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
|
||||||
|
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
|
||||||
|
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_ccff_test.v"
|
||||||
|
|
@ -0,0 +1,30 @@
|
||||||
|
//-------------------------------------------
|
||||||
|
// FPGA Synthesizable Verilog Netlist
|
||||||
|
// Description: Netlist Summary
|
||||||
|
// Author: Xifan TANG
|
||||||
|
// Organization: University of Utah
|
||||||
|
// Date: Tue Nov 17 19:54:57 2020
|
||||||
|
//-------------------------------------------
|
||||||
|
//----- Time scale -----
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
// ------ Include simulation defines -----
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
|
||||||
|
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
|
||||||
|
|
||||||
|
// Design parameter for FPGA I/O sizes
|
||||||
|
`define FPGA_IO_SIZE 144
|
||||||
|
|
||||||
|
// Design parameter for FPGA bitstream sizes
|
||||||
|
`define FPGA_BITSTREAM_SIZE 65656
|
||||||
|
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_4.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2b/sky130_fd_sc_hd__and2b_4.v"
|
||||||
|
|
||||||
|
// ------ Include fabric top-level netlists -----
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v"
|
||||||
|
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/pre_pnr_ccff_test.v"
|
||||||
|
|
||||||
Loading…
Reference in New Issue