From 40eccfa0ba81e5448bc75dc8b13bb78aad6b3d1b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Nov 2020 11:45:51 -0700 Subject: [PATCH] [Testbench] Update post-PnR testbenches for configuration chain and scan-chain and enhance checking codes --- TESTBENCH/common/post_pnr_ccff_test.v | 26 ++++++++++++---- TESTBENCH/common/post_pnr_scff_test.v | 30 ++++++++++++++----- .../ccff_test_post_pnr_include_netlists.v | 7 +++-- .../scff_test_post_pnr_include_netlists.v | 7 +++-- 4 files changed, 52 insertions(+), 18 deletions(-) diff --git a/TESTBENCH/common/post_pnr_ccff_test.v b/TESTBENCH/common/post_pnr_ccff_test.v index 53f9a1d..4ed9cb3 100644 --- a/TESTBENCH/common/post_pnr_ccff_test.v +++ b/TESTBENCH/common/post_pnr_ccff_test.v @@ -54,6 +54,7 @@ wire [0:0] IO_ISOL_N; // ----- Counters for error checking ----- integer num_prog_cycles = 0; integer num_errors = 0; +integer num_checked_points = 0; // Indicate when configuration should be finished reg config_done = 0; @@ -134,9 +135,9 @@ initial .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:`FPGA_IO_SIZE - 1]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:`FPGA_IO_SIZE - 1]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:`FPGA_IO_SIZE - 1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:`FPGA_IO_SIZE - 1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:`FPGA_IO_SIZE - 1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:`FPGA_IO_SIZE - 1]), .ccff_head(ccff_head[0]), .ccff_tail(ccff_tail[0]), .sc_head(sc_head[0]), @@ -168,11 +169,24 @@ initial // Check the ccff_tail when configuration is done if (1'b1 == config_done) begin - if (sc_tail != 1'b1) begin - $display("Error: sc_tail = %b", sc_tail); - num_errors = num_errors + 1; + // The tail should spit a pulse after configuration is done + // So it should be at logic '1' and then pulled down to logic '0' + if (0 == num_checked_points) begin + if (sc_tail != 1'b1) begin + $display("Error: sc_tail = %b", sc_tail); + num_errors = num_errors + 1; + end end + if (1 <= num_checked_points) begin + if (sc_tail != 1'b0) begin + $display("Error: sc_tail = %b", sc_tail); + num_errors = num_errors + 1; + end + end + num_checked_points = num_checked_points + 1; + end + if (2 < num_checked_points) begin $display("Simulation finish with %d errors", num_errors); // End simulation diff --git a/TESTBENCH/common/post_pnr_scff_test.v b/TESTBENCH/common/post_pnr_scff_test.v index 4b6c15b..85a3eb9 100644 --- a/TESTBENCH/common/post_pnr_scff_test.v +++ b/TESTBENCH/common/post_pnr_scff_test.v @@ -54,6 +54,7 @@ wire [0:0] IO_ISOL_N; // ----- Counters for error checking ----- integer num_clock_cycles = 0; integer num_errors = 0; +integer num_checked_points = 0; // Indicate when configuration should be finished reg scan_done = 0; @@ -130,14 +131,14 @@ initial .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:`FPGA_IO_SIZE - 1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:`FPGA_IO_SIZE - 1]), .ccff_head(ccff_head[0]), .ccff_tail(ccff_tail[0]), .sc_head(sc_head[0]), - .sc_tail(sc_tail[0]) - //.IO_ISOL_N(IO_ISOL_N) + .sc_tail(sc_tail[0]), + .IO_ISOL_N(IO_ISOL_N) ); // ----- Force constant '0' to FPGA I/O as this testbench only check @@ -164,11 +165,24 @@ initial // Check the tail of scan-chain when configuration is done if (1'b1 == scan_done) begin - if (sc_tail != 1'b1) begin - $display("Error: sc_tail = %b", sc_tail); - num_errors = num_errors + 1; + // The tail should spit a pulse after configuration is done + // So it should be at logic '1' and then pulled down to logic '0' + if (0 == num_checked_points) begin + if (sc_tail != 1'b1) begin + $display("Error: sc_tail = %b", sc_tail); + num_errors = num_errors + 1; + end end + if (1 <= num_checked_points) begin + if (sc_tail != 1'b0) begin + $display("Error: sc_tail = %b", sc_tail); + num_errors = num_errors + 1; + end + end + num_checked_points = num_checked_points + 1; + end + if (2 < num_checked_points) begin $display("Simulation finish with %d errors", num_errors); // End simulation diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v index ec47dbe..d736108 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v @@ -9,7 +9,7 @@ `timescale 1ns / 1ps // Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 108 +`define FPGA_IO_SIZE 144 // Design parameter for FPGA bitstream sizes `define FPGA_BITSTREAM_SIZE 65656 @@ -61,9 +61,12 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v" // ------ Include fabric top-level netlists ----- //`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_ccff_test.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v index 6734773..28c7f6d 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -9,7 +9,7 @@ `timescale 1ns / 1ps // Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 108 +`define FPGA_IO_SIZE 144 // Design parameter for FPGA bitstream sizes `define FPGA_SCANCHAIN_SIZE 2304 @@ -61,9 +61,12 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v" // ------ Include fabric top-level netlists ----- //`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_scff_test.v"