From 40ca8dfbe32effe75cc63f5f774edbbe32d419d2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 3 Nov 2020 09:14:47 -0700
Subject: [PATCH] [Arch] Update architecture files to use the wrapper files

---
 ..._scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml | 4 ++--
 ..._N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
index 0a43ff1..5810d79 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -183,14 +183,14 @@
       <port type="output" prefix="Q_N" size="1"/>
       <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
-    <circuit_model type="iopad" name="GPIN" prefix="GPIN" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
+    <circuit_model type="iopad" name="GPIN" prefix="GPIN" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <port type="inout" prefix="PAD" lib_name="A" size="1" is_global="true" is_io="true" />
       <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
-    <circuit_model type="iopad" name="GPOUT" prefix="GPOUT" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
+    <circuit_model type="iopad" name="GPOUT" prefix="GPOUT" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
index e4b1313..16707e5 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
@@ -184,7 +184,7 @@
       <port type="output" prefix="Q_N" size="1"/>
       <port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
-    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/sc_verilog/std_cell_extract.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>