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[PDK] Add standard cell wrapper

This commit is contained in:
tangxifan 2020-11-02 11:28:29 -07:00
parent bff4fdfdc1
commit 3f10b49eeb
1 changed files with 29 additions and 0 deletions
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29
PDK/sc_verilog/std_cell_extract.v Normal file
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`timescale 1ns/1ps
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module GPIO (A, IE, OE, Y, in, out, mem_out);
output A;
output IE;
output OE;
output Y;
input in;
output out;
input mem_out;
assign A = in;
assign out = Y;
assign IE = mem_out;
sky130_fd_sc_hd__inv_1 ie_oe_inv (
.A (mem_out),
.Y (OE) );
endmodule