Merge pull request #59 from lnis-uofu/xt_dev

Now modelsim verification is multithreaded

MSIM/common/run_post_pnr_msim_task.py

@@ -16,6 +16,8 @@ import argparse
 import logging
 import subprocess
 import glob
+import threading
+import run_post_pnr_msim_test
 
 #####################################################################
 # Initialize logger 
@@ -64,15 +66,16 @@ num_sim_finished = 0
 msim_testrun_script_abspath = os.path.abspath(__file__) 
 msim_testrun_script_abspath = re.sub(os.path.basename(msim_testrun_script_abspath), "run_post_pnr_msim_test.py", msim_testrun_script_abspath)
 
+threads = []
 for testbench_file in testbench_files:
   # Find testbench name
   testbench_name = re.findall("(\w+)_include_netlists.v", os.path.basename(testbench_file))[0]
-  cmd = "python3 " + msim_testrun_script_abspath \
+  process = multiprocessing.Process(target=run_post_pnr_msim_test.run_msim, args=(testbench_file, msim_task_dir_abspath + "/" + testbench_name, testbench_name + "_autocheck_top_tb",))
-      + " --verilog_testbench " +  testbench_file \
+  process.start()
-      + " --project_path " + msim_task_dir_abspath + "/" + testbench_name \
+  threads.append(process)
-      + " --testbench_name " + testbench_name + "_autocheck_top_tb"
+
-  subprocess.run(cmd, shell=True, check=True) 
+for process in threads:
-  num_sim_finished += 1
+  process.join()
 
 logging.info("Done")
-logging.info("Finish " + str(num_sim_finished) + " ModelSim simulations")
+logging.info("Finish " + str(len(threads)) + " ModelSim simulations")

MSIM/common/run_post_pnr_msim_test.py

@@ -6,6 +6,7 @@
 # - Analyze output log files and return succeed or failure
 #####################################################################
 
+import sys
 import os
 from os.path import dirname, abspath, isfile
 import shutil
@@ -18,7 +19,10 @@ import subprocess
 # Initialize logger
 #####################################################################
 logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.INFO)
-
+#####################################################################
+# Main function of this script, so that it can be called by other scripts
+#####################################################################
+def main(args):
   #####################################################################
   # Parse the options
   #####################################################################
@@ -29,19 +33,25 @@ parser.add_argument('--project_path', required=True,
                       help='Specify the file path to create the ModelSim project')
   parser.add_argument('--testbench_name', required=True,
                       help='Specify the top-level module of the testbench')
-args = parser.parse_args()
+  args = parser.parse_args(args)
 
+  run_msim(args.verilog_testbench, args.project_path, args.testbench_name)
+
+#####################################################################
+# Main function of this script, so that it can be called by other scripts
+#####################################################################
+def run_msim(verilog_testbench, project_path, testbench_name):
   #####################################################################
   # Check options:
   # - Input testbench file must be valid
   #   Otherwise, error out
   # - If the modelsim project path does not exist, create it
   #####################################################################
-if not isfile(args.verilog_testbench):
+  if not isfile(verilog_testbench):
-  logging.error("Invalid Verilog testbench: " + args.verilog_testbench + "\nFile does not exist!\n")
+    logging.error("Invalid Verilog testbench: " + verilog_testbench + "\nFile does not exist!\n")
     exit(1)
   
-project_abs_path = os.path.abspath(args.project_path)
+  project_abs_path = os.path.abspath(project_path)
   if not os.path.isdir(project_abs_path):
     logging.debug("Creating ModelSim project directory : " + project_abs_path + " ...\n")
     os.makedirs(project_abs_path, exist_ok=True)
@@ -58,7 +68,7 @@ if not isfile(msim_proc_tcl_path):
     exit(1)
   
   # Create output file handler
-tcl_file_path = project_abs_path + "/" + os.path.basename(args.testbench_name) + ".tcl"
+  tcl_file_path = project_abs_path + "/" + os.path.basename(testbench_name) + ".tcl"
   logging.debug("Generating Tcl script for ModelSim: " + tcl_file_path)
   tcl_file = open(tcl_file_path, "w")
   
@@ -69,11 +79,11 @@ tcl_lines.append("echo \"==============================\"")
   tcl_lines.append("pwd")
   tcl_lines.append("echo \"==============================\"")
   tcl_lines.append("\n")
-tcl_lines.append("set project_name " + args.testbench_name)
+  tcl_lines.append("set project_name " + testbench_name)
-tcl_lines.append("set top_tb " + args.testbench_name)
+  tcl_lines.append("set top_tb " + testbench_name)
   tcl_lines.append("\n")
   tcl_lines.append("set project_path \"" + project_abs_path  + "\"")
-tcl_lines.append("set verilog_files \"" + os.path.abspath(args.verilog_testbench)  + "\"")
+  tcl_lines.append("set verilog_files \"" + os.path.abspath(verilog_testbench)  + "\"")
   tcl_lines.append("\n")
   tcl_lines.append("source " + msim_proc_tcl_path)
   tcl_lines.append("\n")
@@ -150,6 +160,9 @@ else :
     verification_passed = True
   
   if (verification_passed) :
-  logging.info(args.testbench_name + "...[Passed]\n")
+    logging.info(testbench_name + "...[Passed]\n")
   else :
-  logging.error(args.testbench_name + "...[Failed]\n")
+    logging.error(testbench_name + "...[Failed]\n")
+
+if __name__ == "__main__":
+  main(sys.argv[1:])