From 3a472b0db03fb36467a6fd003f47845a2d3ace76 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 3 Apr 2021 17:54:59 -0600 Subject: [PATCH] [Flow] Adding Makefile for running task --- .gitignore | 1 + .../config/task_simulation.conf | 22 ++++++--- FPGA1212_QLSOFA_HD_PNR/Makefile | 40 +++++++++++++++ FPGA1212_QLSOFA_HD_PNR/config.sh | 4 +- .../config/task_simulation.conf | 22 ++++++--- FPGA1212_SOFA_CHD_PNR/Makefile | 40 +++++++++++++++ .../config/task_simulation.conf | 22 ++++++--- FPGA1212_SOFA_HD_PNR/Makefile | 40 +++++++++++++++ README.md | 49 ++++++++++++++----- 9 files changed, 201 insertions(+), 39 deletions(-) create mode 100644 FPGA1212_QLSOFA_HD_PNR/Makefile create mode 100644 FPGA1212_SOFA_CHD_PNR/Makefile create mode 100644 FPGA1212_SOFA_HD_PNR/Makefile diff --git a/.gitignore b/.gitignore index fc48497..171fc07 100644 --- a/.gitignore +++ b/.gitignore @@ -11,3 +11,4 @@ **/SRC**/*_tb.v **/SDC/**/*.sdc !**/SDC/**/disable_configure_ports.sdc +*/runOpenFPGA diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task_simulation.conf b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task_simulation.conf index 0f65eca..66d79ea 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task_simulation.conf +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task_simulation.conf @@ -1,4 +1,4 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Configuration file for running experiments # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # timeout_each_job : FPGA Task script splits fpga flow into multiple jobs @@ -13,21 +13,27 @@ spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif -openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml +arch_variable_file=${PATH:TASK_DIR}/design_variables.yml + + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga +openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml +external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml +openfpga_vpr_device_layout=12x12 +openfpga_vpr_route_chan_width=60 [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml +arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif +bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif [SYNTHESIS_PARAM] bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v +bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act +bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/FPGA1212_QLSOFA_HD_PNR/Makefile b/FPGA1212_QLSOFA_HD_PNR/Makefile new file mode 100644 index 0000000..d0ddbe8 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/Makefile @@ -0,0 +1,40 @@ +########################################################################################## +########################################################################################## + +SHELL=bash +PYTHON_EXEC=python3.8 +RERUN = 0 +TB = top +OPTIONS = + +.SILENT: +.ONESHELL: + +runOpenFPGA: + SECONDS=0 + source config.sh + # ===================== Check Tools ===================== + which python3.8 > /dev/null + if [ $$? -eq 1 ]; then + echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit; + fi + + # =================== Clean Previous Run ================================= + rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME} + (cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf) + + # ===================== Generate Netlist ================================= + (currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir && + run-task $${TASK_DIR_NAME} --remove_run_dir all + run-task $${TASK_DIR_NAME} ${OPTIONS}) + + if [ $$? -eq 1 ]; then + echo "X X X X X X Failed to generate netlist X X X X X X"; exit; + fi + + duration=$$SECONDS + date > runOpenFPGA + echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA + +clean: + rm -rf runOpenFPGA \ No newline at end of file diff --git a/FPGA1212_QLSOFA_HD_PNR/config.sh b/FPGA1212_QLSOFA_HD_PNR/config.sh index 3253ebc..521023a 100644 --- a/FPGA1212_QLSOFA_HD_PNR/config.sh +++ b/FPGA1212_QLSOFA_HD_PNR/config.sh @@ -3,8 +3,8 @@ # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = export PROJ_NAME=FPGA1212_QLSOFA_HD # Project Name -export FPGA_SIZE_X=12 # Grid X Size -export FPGA_SIZE_Y=12 # Grid Y Size +export FPGA_SIZE_X=12 # Grid X Size +export FPGA_SIZE_Y=12 # Grid Y Size # Design Style [hier/flat], mostly hier export DESIGN_STYLE=hier export TECHNOLOGY="skywater" diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/config/task_simulation.conf b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/config/task_simulation.conf index 0f65eca..66d79ea 100644 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/config/task_simulation.conf +++ b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/config/task_simulation.conf @@ -1,4 +1,4 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Configuration file for running experiments # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # timeout_each_job : FPGA Task script splits fpga flow into multiple jobs @@ -13,21 +13,27 @@ spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif -openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml +arch_variable_file=${PATH:TASK_DIR}/design_variables.yml + + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga +openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml +external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml +openfpga_vpr_device_layout=12x12 +openfpga_vpr_route_chan_width=60 [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml +arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif +bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif [SYNTHESIS_PARAM] bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v +bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act +bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/FPGA1212_SOFA_CHD_PNR/Makefile b/FPGA1212_SOFA_CHD_PNR/Makefile new file mode 100644 index 0000000..d0ddbe8 --- /dev/null +++ b/FPGA1212_SOFA_CHD_PNR/Makefile @@ -0,0 +1,40 @@ +########################################################################################## +########################################################################################## + +SHELL=bash +PYTHON_EXEC=python3.8 +RERUN = 0 +TB = top +OPTIONS = + +.SILENT: +.ONESHELL: + +runOpenFPGA: + SECONDS=0 + source config.sh + # ===================== Check Tools ===================== + which python3.8 > /dev/null + if [ $$? -eq 1 ]; then + echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit; + fi + + # =================== Clean Previous Run ================================= + rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME} + (cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf) + + # ===================== Generate Netlist ================================= + (currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir && + run-task $${TASK_DIR_NAME} --remove_run_dir all + run-task $${TASK_DIR_NAME} ${OPTIONS}) + + if [ $$? -eq 1 ]; then + echo "X X X X X X Failed to generate netlist X X X X X X"; exit; + fi + + duration=$$SECONDS + date > runOpenFPGA + echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA + +clean: + rm -rf runOpenFPGA \ No newline at end of file diff --git a/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/config/task_simulation.conf b/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/config/task_simulation.conf index 0f65eca..7f44b87 100644 --- a/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/config/task_simulation.conf +++ b/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/config/task_simulation.conf @@ -1,4 +1,4 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Configuration file for running experiments # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # timeout_each_job : FPGA Task script splits fpga flow into multiple jobs @@ -13,21 +13,27 @@ spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif -openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml +arch_variable_file=${PATH:TASK_DIR}/design_variables.yml + + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga +openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml +external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml +openfpga_vpr_device_layout=12x12 +openfpga_vpr_route_chan_width=40 [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml +arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif +bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif [SYNTHESIS_PARAM] bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v +bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act +bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/FPGA1212_SOFA_HD_PNR/Makefile b/FPGA1212_SOFA_HD_PNR/Makefile new file mode 100644 index 0000000..d0ddbe8 --- /dev/null +++ b/FPGA1212_SOFA_HD_PNR/Makefile @@ -0,0 +1,40 @@ +########################################################################################## +########################################################################################## + +SHELL=bash +PYTHON_EXEC=python3.8 +RERUN = 0 +TB = top +OPTIONS = + +.SILENT: +.ONESHELL: + +runOpenFPGA: + SECONDS=0 + source config.sh + # ===================== Check Tools ===================== + which python3.8 > /dev/null + if [ $$? -eq 1 ]; then + echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit; + fi + + # =================== Clean Previous Run ================================= + rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME} + (cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf) + + # ===================== Generate Netlist ================================= + (currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir && + run-task $${TASK_DIR_NAME} --remove_run_dir all + run-task $${TASK_DIR_NAME} ${OPTIONS}) + + if [ $$? -eq 1 ]; then + echo "X X X X X X Failed to generate netlist X X X X X X"; exit; + fi + + duration=$$SECONDS + date > runOpenFPGA + echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA + +clean: + rm -rf runOpenFPGA \ No newline at end of file diff --git a/README.md b/README.md index 5640f1c..0586ab2 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ # SOFA [![linux_build](https://github.com/LNIS-Projects/skywater-openfpga/workflows/linux_build/badge.svg)](https://github.com/LNIS-Projects/skywater-openfpga/actions) [![Documentation Status](https://readthedocs.org/projects/skywater-openfpga/badge/?version=latest)](https://skywater-openfpga.readthedocs.io/en/latest/?badge=latest) - + ## Introduction SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework. @@ -21,24 +21,47 @@ This repository provide the following support for the eFPGA IPs ## Quick Start +To run the user flow using SOFA repository you need to have OpenFPGA installed. +Please visit https://github.com/lnis-uofu/OpenFPGA#compilation for OpenFPGA installaton. + ```bash -#Clone the repository and go inside it -git clone https://github.com/LNIS-Projects/skywater-openfpga.git -python3 SCRIPT/repo_setup.py --openfpga_root_path ${OPENFPGA_PROJECT_DIRECTORY} +export OPENFPGA_PATH= + +# Clone the SOFA repository +git clone https://github.com/lnis-uofu/SOFA.git + +# ======== Goto specific design ======== +# FPGA1212_SOFA_CHD_PNR +# FPGA1212_QLSOFA_HD_PNR +# FPGA1212_SOFA_HD_PNR +cd FPGA1212_QLSOFA_HD_PNR + +# ======== Run example OpenFPGA Task ======== +make runOpenFPGA + +# ======== To view the results ======== +cat FPGA1212_QLSOFA_HD_task/latest/task_result.csv + +# ======== To view detailed log ======== +cat codeopen FPGA1212_QLSOFA_HD_task/latest/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/**/openfpgashell.log + ``` ---- +### To bechmark your own design +Copy your verilog file `FPGA1212_QLSOFA_HD_task/micro_benchmark` directory +and modify `FPGA1212_QLSOFA_HD_task/config/task_simulation.conf` file. + +Details of different paramters can be found [Configure run_fpga_task](https://openfpga.readthedocs.io/en/latest/manual/openfpga_flow/run_fpga_task/) -* If you have openfpga repository cloned at the same level of this project, you can simple call ```bash - python3 SCRIPT/repo_setup.py -``` - -Otherwise, you should provide full path using the option _--openfpga\_root\_path_ +cd FPGA1212_QLSOFA_HD_PNR +vi FPGA1212_QLSOFA_HD_task/config/task_simulation.conf +``` +--- ## Chip Gallery -You can find a chip gallery in the online documentation. +You can find a chip gallery in the online documentation ## Directory Organization @@ -49,7 +72,7 @@ You can find a chip gallery in the online documentation. - **HDL**: Hardware description netlists for the FPGA fabrics - **SDC**: design constraints - **SCRIPT**: Scripts to setup, run OpenFPGA etc. - - **TESTBENCH**: Verilog testbenches generated by OpenFPGA + - **TESTBENCH**: Verilog testbenches generated by OpenFPGA - **PDK**: Technology files linked from skywater opensource pdk - **SNPS\_ICC2**: workspace of Synopsys IC Compiler 2 Keep a README inside the folder about the ICC2 version and how-to-use. @@ -57,7 +80,7 @@ You can find a chip gallery in the online documentation. --- -* Note: +* Note: - Please **ONLY** place folders under this directory. README should be the **ONLY** file under this directory - Each EDA tool should have **independent** workspace in separated directories