From 39aa11c42ce54b2592b91617ce32ca7038950ea1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 17 Nov 2020 13:46:25 -0700 Subject: [PATCH] [Script] Update OpenFPGA task run configuration for pre-pnr files --- .../generate_testbench/config/task_template.conf | 2 +- .../generate_testbench/config/task_template.conf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf index 80e3454..51b0690 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_regis openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=12x12 openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc +openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf index 8f40d1f..5ea9949 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_regis openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc +openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/prepnr openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/SRC/fabric_netlists.v external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x2.xml