diff --git a/DOC/source/device/hd_fpga/figures/qlsofa_hd_layout.png b/DOC/source/device/hd_fpga/figures/qlsofa_hd_layout.png
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diff --git a/DOC/source/device/hd_fpga/figures/sofa_chd_layout.png b/DOC/source/device/hd_fpga/figures/sofa_chd_layout.png
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diff --git a/DOC/source/device/hd_fpga/figures/sofa_hd_layout.png b/DOC/source/device/hd_fpga/figures/sofa_hd_layout.png
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diff --git a/DOC/source/device/hd_fpga/hd_device_gallery.rst b/DOC/source/device/hd_fpga/hd_device_gallery.rst
new file mode 100644
index 0000000..fc5e43d
--- /dev/null
+++ b/DOC/source/device/hd_fpga/hd_device_gallery.rst
@@ -0,0 +1,39 @@
+.. _hd_fpga_device_gallery:
+
+Chip Gallery
+------------
+
+Here lists the images of each HD FPGA chips
+
+SOFA HD
+^^^^^^^
+
+SOFA HD is the base design of the SOFA high-density eFPGA IPs
+
+.. figure:: ./figures/sofa_hd_layout.png
+   :scale: 100%
+   :alt: Layout view of SOFA HD device in Caravel SoC
+
+   Layout view of SOFA HD device in Caravel SoC
+
+QLSOFA HD
+^^^^^^^^^
+
+QLSOFA HD is the arithmetic-enhanced design of the SOFA high-density eFPGA IPs
+
+.. figure:: ./figures/qlsofa_hd_layout.png
+   :scale: 100%
+   :alt: Layout view of QLSOFA HD device in Caravel SoC
+
+   Layout view of QLSOFA HD device in Caravel SoC
+
+SOFA CHD
+^^^^^^^^
+
+SOFA CHD is the performance-optimized design of the SOFA high-density eFPGA IPs
+
+.. figure:: ./figures/sofa_chd_layout.png
+   :scale: 100%
+   :alt: Layout view of SOFA CHD device in Caravel SoC
+
+   Layout view of SOFA CHD device in Caravel SoC
diff --git a/DOC/source/device/hd_fpga/index.rst b/DOC/source/device/hd_fpga/index.rst
index a6802e3..dc6f0d1 100644
--- a/DOC/source/device/hd_fpga/index.rst
+++ b/DOC/source/device/hd_fpga/index.rst
@@ -10,3 +10,5 @@ HD FPGAs
    hd_device_comp
 
    hd_device_dcac
+
+   hd_device_gallery
diff --git a/DOC/source/device/introduction.rst b/DOC/source/device/introduction.rst
index 8c43329..6bda114 100644
--- a/DOC/source/device/introduction.rst
+++ b/DOC/source/device/introduction.rst
@@ -17,4 +17,3 @@ We aims to empower embedded applications with its low-cost design approach but h
   :alt: 24-hour FPGA IP development: from PDK to production-ready layout
 
   24-hour FPGA IP development: from PDK to production-ready layout
-