mirror of https://github.com/lnis-uofu/SOFA.git
Merge pull request #19 from LNIS-Projects/xt_dev
Add Online Documentation about Chip Designs
This commit is contained in:
Laboratory for Nano Integrated Systems (LNIS)
GitHub
commit
368af5a182
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@ -6,3 +6,4 @@
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**/*_task/skywater
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**/*_task/skywater
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**/*_Verilog/SRC_Skeleton
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**/*_Verilog/SRC_Skeleton
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**/*_Verilog/SRCBackup
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**/*_Verilog/SRCBackup
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**/DOC/build
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# .readthedocs.yml
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# Read the Docs configuration file
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# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details
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# Required configuration file version
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version: 2
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# Build documentation in the docs/ directory with Sphinx
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sphinx:
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builder: dirhtml
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configuration: DOC/source/conf.py
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# Optionally build your docs in additional formats such as PDF and ePub
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formats: all
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# Optionally set the version of Python and requirements required to build your docs
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python:
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version: 3.7
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install:
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- requirements: DOC/requirements.txt
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<?xml version="1.0" ?>
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<fabric_key>
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<region id="0">
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<key id="45" alias="grid_clb_4__12_"/>
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<key id="46" alias="cby_4__12_"/>
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<key id="47" alias="grid_clb_5__12_"/>
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<key id="48" alias="cby_5__12_"/>
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<key id="49" alias="grid_clb_6__12_"/>
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<key id="50" alias="cby_6__12_"/>
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<key id="51" alias="grid_clb_7__12_"/>
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<key id="52" alias="cby_7__12_"/>
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<key id="53" alias="grid_clb_8__12_"/>
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<key id="54" alias="cby_8__12_"/>
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<key id="55" alias="grid_clb_9__12_"/>
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<key id="56" alias="cby_9__12_"/>
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<key id="57" alias="grid_clb_10__12_"/>
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<key id="58" alias="cby_10__12_"/>
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<key id="59" alias="grid_clb_11__12_"/>
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<key id="60" alias="cby_11__12_"/>
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<key id="61" alias="grid_clb_12__12_"/>
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<key id="62" alias="cby_12__12_"/>
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<key id="63" alias="grid_io_right_right_13__12_"/>
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<key id="64" alias="sb_12__11_"/>
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<key id="65" alias="cbx_12__11_"/>
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<key id="66" alias="sb_11__11_"/>
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<key id="67" alias="cbx_11__11_"/>
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<key id="68" alias="sb_10__11_"/>
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<key id="69" alias="cbx_10__11_"/>
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<key id="70" alias="sb_9__11_"/>
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<key id="71" alias="cbx_9__11_"/>
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<key id="72" alias="sb_8__11_"/>
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<key id="73" alias="cbx_8__11_"/>
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<key id="74" alias="sb_7__11_"/>
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<key id="75" alias="cbx_7__11_"/>
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<key id="76" alias="sb_6__11_"/>
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<key id="77" alias="cbx_6__11_"/>
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<key id="78" alias="sb_5__11_"/>
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<key id="79" alias="cbx_5__11_"/>
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<key id="80" alias="sb_4__11_"/>
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<key id="81" alias="cbx_4__11_"/>
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<key id="82" alias="sb_3__11_"/>
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<key id="83" alias="cbx_3__11_"/>
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<key id="84" alias="sb_2__11_"/>
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<key id="85" alias="cbx_2__11_"/>
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<key id="86" alias="sb_1__11_"/>
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<key id="87" alias="cbx_1__11_"/>
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<key id="88" alias="sb_0__11_"/>
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<key id="89" alias="cby_0__11_"/>
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<key id="90" alias="grid_io_left_left_0__11_"/>
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<key id="91" alias="grid_clb_1__11_"/>
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<key id="92" alias="cby_1__11_"/>
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<key id="95" alias="grid_clb_3__11_"/>
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<key id="96" alias="cby_3__11_"/>
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<key id="98" alias="cby_4__11_"/>
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<key id="104" alias="cby_7__11_"/>
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<key id="188" alias="sb_2__9_"/>
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<key id="189" alias="cbx_2__9_"/>
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<key id="190" alias="sb_1__9_"/>
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<key id="192" alias="sb_0__9_"/>
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<key id="197" alias="grid_clb_2__9_"/>
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<key id="201" alias="grid_clb_4__9_"/>
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<key id="247" alias="grid_clb_1__8_"/>
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<key id="248" alias="cby_1__8_"/>
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<key id="249" alias="grid_clb_2__8_"/>
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<key id="251" alias="grid_clb_3__8_"/>
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||||||
|
<key id="252" alias="cby_3__8_"/>
|
||||||
|
<key id="253" alias="grid_clb_4__8_"/>
|
||||||
|
<key id="254" alias="cby_4__8_"/>
|
||||||
|
<key id="255" alias="grid_clb_5__8_"/>
|
||||||
|
<key id="256" alias="cby_5__8_"/>
|
||||||
|
<key id="257" alias="grid_clb_6__8_"/>
|
||||||
|
<key id="258" alias="cby_6__8_"/>
|
||||||
|
<key id="259" alias="grid_clb_7__8_"/>
|
||||||
|
<key id="260" alias="cby_7__8_"/>
|
||||||
|
<key id="261" alias="grid_clb_8__8_"/>
|
||||||
|
<key id="262" alias="cby_8__8_"/>
|
||||||
|
<key id="263" alias="grid_clb_9__8_"/>
|
||||||
|
<key id="264" alias="cby_9__8_"/>
|
||||||
|
<key id="265" alias="grid_clb_10__8_"/>
|
||||||
|
<key id="266" alias="cby_10__8_"/>
|
||||||
|
<key id="267" alias="grid_clb_11__8_"/>
|
||||||
|
<key id="268" alias="cby_11__8_"/>
|
||||||
|
<key id="269" alias="grid_clb_12__8_"/>
|
||||||
|
<key id="270" alias="cby_12__8_"/>
|
||||||
|
<key id="271" alias="grid_io_right_right_13__8_"/>
|
||||||
|
<key id="272" alias="sb_12__7_"/>
|
||||||
|
<key id="273" alias="cbx_12__7_"/>
|
||||||
|
<key id="274" alias="sb_11__7_"/>
|
||||||
|
<key id="275" alias="cbx_11__7_"/>
|
||||||
|
<key id="276" alias="sb_10__7_"/>
|
||||||
|
<key id="277" alias="cbx_10__7_"/>
|
||||||
|
<key id="278" alias="sb_9__7_"/>
|
||||||
|
<key id="279" alias="cbx_9__7_"/>
|
||||||
|
<key id="280" alias="sb_8__7_"/>
|
||||||
|
<key id="281" alias="cbx_8__7_"/>
|
||||||
|
<key id="282" alias="sb_7__7_"/>
|
||||||
|
<key id="283" alias="cbx_7__7_"/>
|
||||||
|
<key id="284" alias="sb_6__7_"/>
|
||||||
|
<key id="285" alias="cbx_6__7_"/>
|
||||||
|
<key id="286" alias="sb_5__7_"/>
|
||||||
|
<key id="287" alias="cbx_5__7_"/>
|
||||||
|
<key id="288" alias="sb_4__7_"/>
|
||||||
|
<key id="289" alias="cbx_4__7_"/>
|
||||||
|
<key id="290" alias="sb_3__7_"/>
|
||||||
|
<key id="291" alias="cbx_3__7_"/>
|
||||||
|
<key id="292" alias="sb_2__7_"/>
|
||||||
|
<key id="293" alias="cbx_2__7_"/>
|
||||||
|
<key id="294" alias="sb_1__7_"/>
|
||||||
|
<key id="295" alias="cbx_1__7_"/>
|
||||||
|
<key id="296" alias="sb_0__7_"/>
|
||||||
|
<key id="297" alias="cby_0__7_"/>
|
||||||
|
<key id="298" alias="grid_io_left_left_0__7_"/>
|
||||||
|
<key id="299" alias="grid_clb_1__7_"/>
|
||||||
|
<key id="300" alias="cby_1__7_"/>
|
||||||
|
<key id="301" alias="grid_clb_2__7_"/>
|
||||||
|
<key id="302" alias="cby_2__7_"/>
|
||||||
|
<key id="303" alias="grid_clb_3__7_"/>
|
||||||
|
<key id="304" alias="cby_3__7_"/>
|
||||||
|
<key id="305" alias="grid_clb_4__7_"/>
|
||||||
|
<key id="306" alias="cby_4__7_"/>
|
||||||
|
<key id="307" alias="grid_clb_5__7_"/>
|
||||||
|
<key id="308" alias="cby_5__7_"/>
|
||||||
|
<key id="309" alias="grid_clb_6__7_"/>
|
||||||
|
<key id="310" alias="cby_6__7_"/>
|
||||||
|
<key id="311" alias="grid_clb_7__7_"/>
|
||||||
|
<key id="312" alias="cby_7__7_"/>
|
||||||
|
<key id="313" alias="grid_clb_8__7_"/>
|
||||||
|
<key id="314" alias="cby_8__7_"/>
|
||||||
|
<key id="315" alias="grid_clb_9__7_"/>
|
||||||
|
<key id="316" alias="cby_9__7_"/>
|
||||||
|
<key id="317" alias="grid_clb_10__7_"/>
|
||||||
|
<key id="318" alias="cby_10__7_"/>
|
||||||
|
<key id="319" alias="grid_clb_11__7_"/>
|
||||||
|
<key id="320" alias="cby_11__7_"/>
|
||||||
|
<key id="321" alias="grid_clb_12__7_"/>
|
||||||
|
<key id="322" alias="cby_12__7_"/>
|
||||||
|
<key id="323" alias="grid_io_right_right_13__7_"/>
|
||||||
|
<key id="324" alias="sb_12__6_"/>
|
||||||
|
<key id="325" alias="cbx_12__6_"/>
|
||||||
|
<key id="326" alias="sb_11__6_"/>
|
||||||
|
<key id="327" alias="cbx_11__6_"/>
|
||||||
|
<key id="328" alias="sb_10__6_"/>
|
||||||
|
<key id="329" alias="cbx_10__6_"/>
|
||||||
|
<key id="330" alias="sb_9__6_"/>
|
||||||
|
<key id="331" alias="cbx_9__6_"/>
|
||||||
|
<key id="332" alias="sb_8__6_"/>
|
||||||
|
<key id="333" alias="cbx_8__6_"/>
|
||||||
|
<key id="334" alias="sb_7__6_"/>
|
||||||
|
<key id="335" alias="cbx_7__6_"/>
|
||||||
|
<key id="336" alias="sb_6__6_"/>
|
||||||
|
<key id="337" alias="cbx_6__6_"/>
|
||||||
|
<key id="338" alias="sb_5__6_"/>
|
||||||
|
<key id="339" alias="cbx_5__6_"/>
|
||||||
|
<key id="340" alias="sb_4__6_"/>
|
||||||
|
<key id="341" alias="cbx_4__6_"/>
|
||||||
|
<key id="342" alias="sb_3__6_"/>
|
||||||
|
<key id="343" alias="cbx_3__6_"/>
|
||||||
|
<key id="344" alias="sb_2__6_"/>
|
||||||
|
<key id="345" alias="cbx_2__6_"/>
|
||||||
|
<key id="346" alias="sb_1__6_"/>
|
||||||
|
<key id="347" alias="cbx_1__6_"/>
|
||||||
|
<key id="348" alias="sb_0__6_"/>
|
||||||
|
<key id="349" alias="cby_0__6_"/>
|
||||||
|
<key id="350" alias="grid_io_left_left_0__6_"/>
|
||||||
|
<key id="351" alias="grid_clb_1__6_"/>
|
||||||
|
<key id="352" alias="cby_1__6_"/>
|
||||||
|
<key id="353" alias="grid_clb_2__6_"/>
|
||||||
|
<key id="354" alias="cby_2__6_"/>
|
||||||
|
<key id="355" alias="grid_clb_3__6_"/>
|
||||||
|
<key id="356" alias="cby_3__6_"/>
|
||||||
|
<key id="357" alias="grid_clb_4__6_"/>
|
||||||
|
<key id="358" alias="cby_4__6_"/>
|
||||||
|
<key id="359" alias="grid_clb_5__6_"/>
|
||||||
|
<key id="360" alias="cby_5__6_"/>
|
||||||
|
<key id="361" alias="grid_clb_6__6_"/>
|
||||||
|
<key id="362" alias="cby_6__6_"/>
|
||||||
|
<key id="363" alias="grid_clb_7__6_"/>
|
||||||
|
<key id="364" alias="cby_7__6_"/>
|
||||||
|
<key id="365" alias="grid_clb_8__6_"/>
|
||||||
|
<key id="366" alias="cby_8__6_"/>
|
||||||
|
<key id="367" alias="grid_clb_9__6_"/>
|
||||||
|
<key id="368" alias="cby_9__6_"/>
|
||||||
|
<key id="369" alias="grid_clb_10__6_"/>
|
||||||
|
<key id="370" alias="cby_10__6_"/>
|
||||||
|
<key id="371" alias="grid_clb_11__6_"/>
|
||||||
|
<key id="372" alias="cby_11__6_"/>
|
||||||
|
<key id="373" alias="grid_clb_12__6_"/>
|
||||||
|
<key id="374" alias="cby_12__6_"/>
|
||||||
|
<key id="375" alias="grid_io_right_right_13__6_"/>
|
||||||
|
<key id="376" alias="sb_12__5_"/>
|
||||||
|
<key id="377" alias="cbx_12__5_"/>
|
||||||
|
<key id="378" alias="sb_11__5_"/>
|
||||||
|
<key id="379" alias="cbx_11__5_"/>
|
||||||
|
<key id="380" alias="sb_10__5_"/>
|
||||||
|
<key id="381" alias="cbx_10__5_"/>
|
||||||
|
<key id="382" alias="sb_9__5_"/>
|
||||||
|
<key id="383" alias="cbx_9__5_"/>
|
||||||
|
<key id="384" alias="sb_8__5_"/>
|
||||||
|
<key id="385" alias="cbx_8__5_"/>
|
||||||
|
<key id="386" alias="sb_7__5_"/>
|
||||||
|
<key id="387" alias="cbx_7__5_"/>
|
||||||
|
<key id="388" alias="sb_6__5_"/>
|
||||||
|
<key id="389" alias="cbx_6__5_"/>
|
||||||
|
<key id="390" alias="sb_5__5_"/>
|
||||||
|
<key id="391" alias="cbx_5__5_"/>
|
||||||
|
<key id="392" alias="sb_4__5_"/>
|
||||||
|
<key id="393" alias="cbx_4__5_"/>
|
||||||
|
<key id="394" alias="sb_3__5_"/>
|
||||||
|
<key id="395" alias="cbx_3__5_"/>
|
||||||
|
<key id="396" alias="sb_2__5_"/>
|
||||||
|
<key id="397" alias="cbx_2__5_"/>
|
||||||
|
<key id="398" alias="sb_1__5_"/>
|
||||||
|
<key id="399" alias="cbx_1__5_"/>
|
||||||
|
<key id="400" alias="sb_0__5_"/>
|
||||||
|
<key id="401" alias="cby_0__5_"/>
|
||||||
|
<key id="402" alias="grid_io_left_left_0__5_"/>
|
||||||
|
<key id="403" alias="grid_clb_1__5_"/>
|
||||||
|
<key id="404" alias="cby_1__5_"/>
|
||||||
|
<key id="405" alias="grid_clb_2__5_"/>
|
||||||
|
<key id="406" alias="cby_2__5_"/>
|
||||||
|
<key id="407" alias="grid_clb_3__5_"/>
|
||||||
|
<key id="408" alias="cby_3__5_"/>
|
||||||
|
<key id="409" alias="grid_clb_4__5_"/>
|
||||||
|
<key id="410" alias="cby_4__5_"/>
|
||||||
|
<key id="411" alias="grid_clb_5__5_"/>
|
||||||
|
<key id="412" alias="cby_5__5_"/>
|
||||||
|
<key id="413" alias="grid_clb_6__5_"/>
|
||||||
|
<key id="414" alias="cby_6__5_"/>
|
||||||
|
<key id="415" alias="grid_clb_7__5_"/>
|
||||||
|
<key id="416" alias="cby_7__5_"/>
|
||||||
|
<key id="417" alias="grid_clb_8__5_"/>
|
||||||
|
<key id="418" alias="cby_8__5_"/>
|
||||||
|
<key id="419" alias="grid_clb_9__5_"/>
|
||||||
|
<key id="420" alias="cby_9__5_"/>
|
||||||
|
<key id="421" alias="grid_clb_10__5_"/>
|
||||||
|
<key id="422" alias="cby_10__5_"/>
|
||||||
|
<key id="423" alias="grid_clb_11__5_"/>
|
||||||
|
<key id="424" alias="cby_11__5_"/>
|
||||||
|
<key id="425" alias="grid_clb_12__5_"/>
|
||||||
|
<key id="426" alias="cby_12__5_"/>
|
||||||
|
<key id="427" alias="grid_io_right_right_13__5_"/>
|
||||||
|
<key id="428" alias="sb_12__4_"/>
|
||||||
|
<key id="429" alias="cbx_12__4_"/>
|
||||||
|
<key id="430" alias="sb_11__4_"/>
|
||||||
|
<key id="431" alias="cbx_11__4_"/>
|
||||||
|
<key id="432" alias="sb_10__4_"/>
|
||||||
|
<key id="433" alias="cbx_10__4_"/>
|
||||||
|
<key id="434" alias="sb_9__4_"/>
|
||||||
|
<key id="435" alias="cbx_9__4_"/>
|
||||||
|
<key id="436" alias="sb_8__4_"/>
|
||||||
|
<key id="437" alias="cbx_8__4_"/>
|
||||||
|
<key id="438" alias="sb_7__4_"/>
|
||||||
|
<key id="439" alias="cbx_7__4_"/>
|
||||||
|
<key id="440" alias="sb_6__4_"/>
|
||||||
|
<key id="441" alias="cbx_6__4_"/>
|
||||||
|
<key id="442" alias="sb_5__4_"/>
|
||||||
|
<key id="443" alias="cbx_5__4_"/>
|
||||||
|
<key id="444" alias="sb_4__4_"/>
|
||||||
|
<key id="445" alias="cbx_4__4_"/>
|
||||||
|
<key id="446" alias="sb_3__4_"/>
|
||||||
|
<key id="447" alias="cbx_3__4_"/>
|
||||||
|
<key id="448" alias="sb_2__4_"/>
|
||||||
|
<key id="449" alias="cbx_2__4_"/>
|
||||||
|
<key id="450" alias="sb_1__4_"/>
|
||||||
|
<key id="451" alias="cbx_1__4_"/>
|
||||||
|
<key id="452" alias="sb_0__4_"/>
|
||||||
|
<key id="453" alias="cby_0__4_"/>
|
||||||
|
<key id="454" alias="grid_io_left_left_0__4_"/>
|
||||||
|
<key id="455" alias="grid_clb_1__4_"/>
|
||||||
|
<key id="456" alias="cby_1__4_"/>
|
||||||
|
<key id="457" alias="grid_clb_2__4_"/>
|
||||||
|
<key id="458" alias="cby_2__4_"/>
|
||||||
|
<key id="459" alias="grid_clb_3__4_"/>
|
||||||
|
<key id="460" alias="cby_3__4_"/>
|
||||||
|
<key id="461" alias="grid_clb_4__4_"/>
|
||||||
|
<key id="462" alias="cby_4__4_"/>
|
||||||
|
<key id="463" alias="grid_clb_5__4_"/>
|
||||||
|
<key id="464" alias="cby_5__4_"/>
|
||||||
|
<key id="465" alias="grid_clb_6__4_"/>
|
||||||
|
<key id="466" alias="cby_6__4_"/>
|
||||||
|
<key id="467" alias="grid_clb_7__4_"/>
|
||||||
|
<key id="468" alias="cby_7__4_"/>
|
||||||
|
<key id="469" alias="grid_clb_8__4_"/>
|
||||||
|
<key id="470" alias="cby_8__4_"/>
|
||||||
|
<key id="471" alias="grid_clb_9__4_"/>
|
||||||
|
<key id="472" alias="cby_9__4_"/>
|
||||||
|
<key id="473" alias="grid_clb_10__4_"/>
|
||||||
|
<key id="474" alias="cby_10__4_"/>
|
||||||
|
<key id="475" alias="grid_clb_11__4_"/>
|
||||||
|
<key id="476" alias="cby_11__4_"/>
|
||||||
|
<key id="477" alias="grid_clb_12__4_"/>
|
||||||
|
<key id="478" alias="cby_12__4_"/>
|
||||||
|
<key id="479" alias="grid_io_right_right_13__4_"/>
|
||||||
|
<key id="480" alias="sb_12__3_"/>
|
||||||
|
<key id="481" alias="cbx_12__3_"/>
|
||||||
|
<key id="482" alias="sb_11__3_"/>
|
||||||
|
<key id="483" alias="cbx_11__3_"/>
|
||||||
|
<key id="484" alias="sb_10__3_"/>
|
||||||
|
<key id="485" alias="cbx_10__3_"/>
|
||||||
|
<key id="486" alias="sb_9__3_"/>
|
||||||
|
<key id="487" alias="cbx_9__3_"/>
|
||||||
|
<key id="488" alias="sb_8__3_"/>
|
||||||
|
<key id="489" alias="cbx_8__3_"/>
|
||||||
|
<key id="490" alias="sb_7__3_"/>
|
||||||
|
<key id="491" alias="cbx_7__3_"/>
|
||||||
|
<key id="492" alias="sb_6__3_"/>
|
||||||
|
<key id="493" alias="cbx_6__3_"/>
|
||||||
|
<key id="494" alias="sb_5__3_"/>
|
||||||
|
<key id="495" alias="cbx_5__3_"/>
|
||||||
|
<key id="496" alias="sb_4__3_"/>
|
||||||
|
<key id="497" alias="cbx_4__3_"/>
|
||||||
|
<key id="498" alias="sb_3__3_"/>
|
||||||
|
<key id="499" alias="cbx_3__3_"/>
|
||||||
|
<key id="500" alias="sb_2__3_"/>
|
||||||
|
<key id="501" alias="cbx_2__3_"/>
|
||||||
|
<key id="502" alias="sb_1__3_"/>
|
||||||
|
<key id="503" alias="cbx_1__3_"/>
|
||||||
|
<key id="504" alias="sb_0__3_"/>
|
||||||
|
<key id="505" alias="cby_0__3_"/>
|
||||||
|
<key id="506" alias="grid_io_left_left_0__3_"/>
|
||||||
|
<key id="507" alias="grid_clb_1__3_"/>
|
||||||
|
<key id="508" alias="cby_1__3_"/>
|
||||||
|
<key id="509" alias="grid_clb_2__3_"/>
|
||||||
|
<key id="510" alias="cby_2__3_"/>
|
||||||
|
<key id="511" alias="grid_clb_3__3_"/>
|
||||||
|
<key id="512" alias="cby_3__3_"/>
|
||||||
|
<key id="513" alias="grid_clb_4__3_"/>
|
||||||
|
<key id="514" alias="cby_4__3_"/>
|
||||||
|
<key id="515" alias="grid_clb_5__3_"/>
|
||||||
|
<key id="516" alias="cby_5__3_"/>
|
||||||
|
<key id="517" alias="grid_clb_6__3_"/>
|
||||||
|
<key id="518" alias="cby_6__3_"/>
|
||||||
|
<key id="519" alias="grid_clb_7__3_"/>
|
||||||
|
<key id="520" alias="cby_7__3_"/>
|
||||||
|
<key id="521" alias="grid_clb_8__3_"/>
|
||||||
|
<key id="522" alias="cby_8__3_"/>
|
||||||
|
<key id="523" alias="grid_clb_9__3_"/>
|
||||||
|
<key id="524" alias="cby_9__3_"/>
|
||||||
|
<key id="525" alias="grid_clb_10__3_"/>
|
||||||
|
<key id="526" alias="cby_10__3_"/>
|
||||||
|
<key id="527" alias="grid_clb_11__3_"/>
|
||||||
|
<key id="528" alias="cby_11__3_"/>
|
||||||
|
<key id="529" alias="grid_clb_12__3_"/>
|
||||||
|
<key id="530" alias="cby_12__3_"/>
|
||||||
|
<key id="531" alias="grid_io_right_right_13__3_"/>
|
||||||
|
<key id="532" alias="sb_12__2_"/>
|
||||||
|
<key id="533" alias="cbx_12__2_"/>
|
||||||
|
<key id="534" alias="sb_11__2_"/>
|
||||||
|
<key id="535" alias="cbx_11__2_"/>
|
||||||
|
<key id="536" alias="sb_10__2_"/>
|
||||||
|
<key id="537" alias="cbx_10__2_"/>
|
||||||
|
<key id="538" alias="sb_9__2_"/>
|
||||||
|
<key id="539" alias="cbx_9__2_"/>
|
||||||
|
<key id="540" alias="sb_8__2_"/>
|
||||||
|
<key id="541" alias="cbx_8__2_"/>
|
||||||
|
<key id="542" alias="sb_7__2_"/>
|
||||||
|
<key id="543" alias="cbx_7__2_"/>
|
||||||
|
<key id="544" alias="sb_6__2_"/>
|
||||||
|
<key id="545" alias="cbx_6__2_"/>
|
||||||
|
<key id="546" alias="sb_5__2_"/>
|
||||||
|
<key id="547" alias="cbx_5__2_"/>
|
||||||
|
<key id="548" alias="sb_4__2_"/>
|
||||||
|
<key id="549" alias="cbx_4__2_"/>
|
||||||
|
<key id="550" alias="sb_3__2_"/>
|
||||||
|
<key id="551" alias="cbx_3__2_"/>
|
||||||
|
<key id="552" alias="sb_2__2_"/>
|
||||||
|
<key id="553" alias="cbx_2__2_"/>
|
||||||
|
<key id="554" alias="sb_1__2_"/>
|
||||||
|
<key id="555" alias="cbx_1__2_"/>
|
||||||
|
<key id="556" alias="sb_0__2_"/>
|
||||||
|
<key id="557" alias="cby_0__2_"/>
|
||||||
|
<key id="558" alias="grid_io_left_left_0__2_"/>
|
||||||
|
<key id="559" alias="grid_clb_1__2_"/>
|
||||||
|
<key id="560" alias="cby_1__2_"/>
|
||||||
|
<key id="561" alias="grid_clb_2__2_"/>
|
||||||
|
<key id="562" alias="cby_2__2_"/>
|
||||||
|
<key id="563" alias="grid_clb_3__2_"/>
|
||||||
|
<key id="564" alias="cby_3__2_"/>
|
||||||
|
<key id="565" alias="grid_clb_4__2_"/>
|
||||||
|
<key id="566" alias="cby_4__2_"/>
|
||||||
|
<key id="567" alias="grid_clb_5__2_"/>
|
||||||
|
<key id="568" alias="cby_5__2_"/>
|
||||||
|
<key id="569" alias="grid_clb_6__2_"/>
|
||||||
|
<key id="570" alias="cby_6__2_"/>
|
||||||
|
<key id="571" alias="grid_clb_7__2_"/>
|
||||||
|
<key id="572" alias="cby_7__2_"/>
|
||||||
|
<key id="573" alias="grid_clb_8__2_"/>
|
||||||
|
<key id="574" alias="cby_8__2_"/>
|
||||||
|
<key id="575" alias="grid_clb_9__2_"/>
|
||||||
|
<key id="576" alias="cby_9__2_"/>
|
||||||
|
<key id="577" alias="grid_clb_10__2_"/>
|
||||||
|
<key id="578" alias="cby_10__2_"/>
|
||||||
|
<key id="579" alias="grid_clb_11__2_"/>
|
||||||
|
<key id="580" alias="cby_11__2_"/>
|
||||||
|
<key id="581" alias="grid_clb_12__2_"/>
|
||||||
|
<key id="582" alias="cby_12__2_"/>
|
||||||
|
<key id="583" alias="grid_io_right_right_13__2_"/>
|
||||||
|
<key id="584" alias="sb_12__1_"/>
|
||||||
|
<key id="585" alias="cbx_12__1_"/>
|
||||||
|
<key id="586" alias="sb_11__1_"/>
|
||||||
|
<key id="587" alias="cbx_11__1_"/>
|
||||||
|
<key id="588" alias="sb_10__1_"/>
|
||||||
|
<key id="589" alias="cbx_10__1_"/>
|
||||||
|
<key id="590" alias="sb_9__1_"/>
|
||||||
|
<key id="591" alias="cbx_9__1_"/>
|
||||||
|
<key id="592" alias="sb_8__1_"/>
|
||||||
|
<key id="593" alias="cbx_8__1_"/>
|
||||||
|
<key id="594" alias="sb_7__1_"/>
|
||||||
|
<key id="595" alias="cbx_7__1_"/>
|
||||||
|
<key id="596" alias="sb_6__1_"/>
|
||||||
|
<key id="597" alias="cbx_6__1_"/>
|
||||||
|
<key id="598" alias="sb_5__1_"/>
|
||||||
|
<key id="599" alias="cbx_5__1_"/>
|
||||||
|
<key id="600" alias="sb_4__1_"/>
|
||||||
|
<key id="601" alias="cbx_4__1_"/>
|
||||||
|
<key id="602" alias="sb_3__1_"/>
|
||||||
|
<key id="603" alias="cbx_3__1_"/>
|
||||||
|
<key id="604" alias="sb_2__1_"/>
|
||||||
|
<key id="605" alias="cbx_2__1_"/>
|
||||||
|
<key id="606" alias="sb_1__1_"/>
|
||||||
|
<key id="607" alias="cbx_1__1_"/>
|
||||||
|
<key id="608" alias="sb_0__1_"/>
|
||||||
|
<key id="609" alias="cby_0__1_"/>
|
||||||
|
<key id="610" alias="grid_io_left_left_0__1_"/>
|
||||||
|
<key id="611" alias="grid_clb_1__1_"/>
|
||||||
|
<key id="612" alias="cby_1__1_"/>
|
||||||
|
<key id="613" alias="grid_clb_2__1_"/>
|
||||||
|
<key id="614" alias="cby_2__1_"/>
|
||||||
|
<key id="615" alias="grid_clb_3__1_"/>
|
||||||
|
<key id="616" alias="cby_3__1_"/>
|
||||||
|
<key id="617" alias="grid_clb_4__1_"/>
|
||||||
|
<key id="618" alias="cby_4__1_"/>
|
||||||
|
<key id="619" alias="grid_clb_5__1_"/>
|
||||||
|
<key id="620" alias="cby_5__1_"/>
|
||||||
|
<key id="621" alias="grid_clb_6__1_"/>
|
||||||
|
<key id="622" alias="cby_6__1_"/>
|
||||||
|
<key id="623" alias="grid_clb_7__1_"/>
|
||||||
|
<key id="624" alias="cby_7__1_"/>
|
||||||
|
<key id="625" alias="grid_clb_8__1_"/>
|
||||||
|
<key id="626" alias="cby_8__1_"/>
|
||||||
|
<key id="627" alias="grid_clb_9__1_"/>
|
||||||
|
<key id="628" alias="cby_9__1_"/>
|
||||||
|
<key id="629" alias="grid_clb_10__1_"/>
|
||||||
|
<key id="630" alias="cby_10__1_"/>
|
||||||
|
<key id="631" alias="grid_clb_11__1_"/>
|
||||||
|
<key id="632" alias="cby_11__1_"/>
|
||||||
|
<key id="633" alias="grid_clb_12__1_"/>
|
||||||
|
<key id="634" alias="cby_12__1_"/>
|
||||||
|
<key id="635" alias="grid_io_right_right_13__1_"/>
|
||||||
|
<key id="636" alias="sb_12__0_"/>
|
||||||
|
<key id="637" alias="cbx_12__0_"/>
|
||||||
|
<key id="638" alias="grid_io_bottom_bottom_12__0_"/>
|
||||||
|
<key id="639" alias="sb_11__0_"/>
|
||||||
|
<key id="640" alias="cbx_11__0_"/>
|
||||||
|
<key id="641" alias="grid_io_bottom_bottom_11__0_"/>
|
||||||
|
<key id="642" alias="sb_10__0_"/>
|
||||||
|
<key id="643" alias="cbx_10__0_"/>
|
||||||
|
<key id="644" alias="grid_io_bottom_bottom_10__0_"/>
|
||||||
|
<key id="645" alias="sb_9__0_"/>
|
||||||
|
<key id="646" alias="cbx_9__0_"/>
|
||||||
|
<key id="647" alias="grid_io_bottom_bottom_9__0_"/>
|
||||||
|
<key id="648" alias="sb_8__0_"/>
|
||||||
|
<key id="649" alias="cbx_8__0_"/>
|
||||||
|
<key id="650" alias="grid_io_bottom_bottom_8__0_"/>
|
||||||
|
<key id="651" alias="sb_7__0_"/>
|
||||||
|
<key id="652" alias="cbx_7__0_"/>
|
||||||
|
<key id="653" alias="grid_io_bottom_bottom_7__0_"/>
|
||||||
|
<key id="654" alias="sb_6__0_"/>
|
||||||
|
<key id="655" alias="cbx_6__0_"/>
|
||||||
|
<key id="656" alias="grid_io_bottom_bottom_6__0_"/>
|
||||||
|
<key id="657" alias="sb_5__0_"/>
|
||||||
|
<key id="658" alias="cbx_5__0_"/>
|
||||||
|
<key id="659" alias="grid_io_bottom_bottom_5__0_"/>
|
||||||
|
<key id="660" alias="sb_4__0_"/>
|
||||||
|
<key id="661" alias="cbx_4__0_"/>
|
||||||
|
<key id="662" alias="grid_io_bottom_bottom_4__0_"/>
|
||||||
|
<key id="663" alias="sb_3__0_"/>
|
||||||
|
<key id="664" alias="cbx_3__0_"/>
|
||||||
|
<key id="665" alias="grid_io_bottom_bottom_3__0_"/>
|
||||||
|
<key id="666" alias="sb_2__0_"/>
|
||||||
|
<key id="667" alias="cbx_2__0_"/>
|
||||||
|
<key id="668" alias="grid_io_bottom_bottom_2__0_"/>
|
||||||
|
<key id="669" alias="sb_1__0_"/>
|
||||||
|
<key id="670" alias="cbx_1__0_"/>
|
||||||
|
<key id="671" alias="grid_io_bottom_bottom_1__0_"/>
|
||||||
|
<key id="672" alias="sb_0__0_"/>
|
||||||
|
</region>
|
||||||
|
</fabric_key>
|
||||||
|
|
@ -157,7 +157,7 @@
|
||||||
<port type="input" prefix="Test_en" lib_name="SCE" size="1" is_global="true" default_val="0"/>
|
<port type="input" prefix="Test_en" lib_name="SCE" size="1" is_global="true" default_val="0"/>
|
||||||
<!-- <port type="input" prefix="reset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_reset="true"/> -->
|
<!-- <port type="input" prefix="reset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_reset="true"/> -->
|
||||||
<port type="output" prefix="Q" size="1"/>
|
<port type="output" prefix="Q" size="1"/>
|
||||||
<port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="true" default_val="0" />
|
<port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="false" default_val="0" />
|
||||||
</circuit_model>
|
</circuit_model>
|
||||||
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
|
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
|
||||||
<design_technology type="cmos" fracturable_lut="true"/>
|
<design_technology type="cmos" fracturable_lut="true"/>
|
||||||
|
|
@ -214,6 +214,9 @@
|
||||||
<direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
|
<direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
|
||||||
<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
|
<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
|
||||||
</direct_connection>
|
</direct_connection>
|
||||||
|
<tile_annotations>
|
||||||
|
<global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
|
||||||
|
</tile_annotations>
|
||||||
<pb_type_annotations>
|
<pb_type_annotations>
|
||||||
<!-- physical pb_type binding in complex block IO -->
|
<!-- physical pb_type binding in complex block IO -->
|
||||||
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,33 @@
|
||||||
|
# Minimal makefile for Sphinx documentation
|
||||||
|
#
|
||||||
|
|
||||||
|
# You can set these variables from the command line.
|
||||||
|
SPHINXOPTS =
|
||||||
|
SPHINXBUILD = sphinx-build
|
||||||
|
SOURCEDIR = source
|
||||||
|
BUILDDIR = build
|
||||||
|
|
||||||
|
PAPER =
|
||||||
|
PAPEROPT_a4 = -D latex_paper_size=a4
|
||||||
|
PAPEROPT_letter = -D latex_paper_size=letter
|
||||||
|
ALL_SPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) $(SOURCEDIR)
|
||||||
|
|
||||||
|
# Put it first so that "make" without argument is like "make help".
|
||||||
|
help:
|
||||||
|
@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
|
||||||
|
|
||||||
|
livehtml:
|
||||||
|
sphinx-autobuild -b html $(ALL_SPHINXOPTS) $(BUILDDIR)/html
|
||||||
|
|
||||||
|
clean:
|
||||||
|
rm -rf $(BUILDDIR)/*
|
||||||
|
|
||||||
|
.PHONY: help clean Makefile
|
||||||
|
|
||||||
|
# Catch-all target: route all unknown targets to Sphinx using the new
|
||||||
|
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
|
||||||
|
%: Makefile
|
||||||
|
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
|
||||||
|
#html:
|
||||||
|
# $(SPHINXBUILD) -b html $@ "$(SOURCEDIR)" "$(BUILDDIR)/html" $(SPHINXOPTS)
|
||||||
|
|
||||||
|
|
@ -0,0 +1,35 @@
|
||||||
|
@ECHO OFF
|
||||||
|
|
||||||
|
pushd %~dp0
|
||||||
|
|
||||||
|
REM Command file for Sphinx documentation
|
||||||
|
|
||||||
|
if "%SPHINXBUILD%" == "" (
|
||||||
|
set SPHINXBUILD=sphinx-build
|
||||||
|
)
|
||||||
|
set SOURCEDIR=source
|
||||||
|
set BUILDDIR=build
|
||||||
|
|
||||||
|
if "%1" == "" goto help
|
||||||
|
|
||||||
|
%SPHINXBUILD% >NUL 2>NUL
|
||||||
|
if errorlevel 9009 (
|
||||||
|
echo.
|
||||||
|
echo.The 'sphinx-build' command was not found. Make sure you have Sphinx
|
||||||
|
echo.installed, then set the SPHINXBUILD environment variable to point
|
||||||
|
echo.to the full path of the 'sphinx-build' executable. Alternatively you
|
||||||
|
echo.may add the Sphinx directory to PATH.
|
||||||
|
echo.
|
||||||
|
echo.If you don't have Sphinx installed, grab it from
|
||||||
|
echo.http://sphinx-doc.org/
|
||||||
|
exit /b 1
|
||||||
|
)
|
||||||
|
|
||||||
|
%SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS%
|
||||||
|
goto end
|
||||||
|
|
||||||
|
:help
|
||||||
|
%SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS%
|
||||||
|
|
||||||
|
:end
|
||||||
|
popd
|
||||||
|
|
@ -0,0 +1,16 @@
|
||||||
|
#Python requirements file for building documentation
|
||||||
|
# used by Read The Docs to install python required
|
||||||
|
# modules with pip.
|
||||||
|
|
||||||
|
# Support Markdown
|
||||||
|
#recommonmark
|
||||||
|
|
||||||
|
#Handle references in bibtex format
|
||||||
|
sphinxcontrib-bibtex
|
||||||
|
sphinxcontrib-tikz
|
||||||
|
|
||||||
|
#Work-around bug "AttributeError: 'Values' object has no attribute 'character_level_inline_markup'" with docutils 0.13.1
|
||||||
|
#See:
|
||||||
|
# * https://github.com/sphinx-doc/sphinx/issues/3951
|
||||||
|
# * https://sourceforge.net/p/docutils/bugs/304/
|
||||||
|
#docutils>=0.14
|
||||||
|
|
@ -0,0 +1,13 @@
|
||||||
|
Acknowledgment
|
||||||
|
--------------
|
||||||
|
|
||||||
|
.. figure:: ./figures/uofu_logo.png
|
||||||
|
:scale: 50%
|
||||||
|
|
||||||
|
.. figure:: ./figures/lnis_logo.png
|
||||||
|
:scale: 50%
|
||||||
|
|
||||||
|
Supported by DARPA PoSH program
|
||||||
|
|
||||||
|
.. figure:: ./figures/darpa_logo.png
|
||||||
|
:scale: 50%
|
||||||
|
|
@ -0,0 +1,22 @@
|
||||||
|
Configurable Logic Block User Guide
|
||||||
|
-----------------------------------
|
||||||
|
|
||||||
|
Each Configurable Logic Block (CLB) consists of 8 logic elements as shown in :numref:`fig_fle_arch`.
|
||||||
|
|
||||||
|
.. _fig_fle_arch:
|
||||||
|
|
||||||
|
.. figure:: ./figures/fle_arch.png
|
||||||
|
:scale: 100%
|
||||||
|
:alt: Logic element schematic
|
||||||
|
|
||||||
|
Schematic of a logic element
|
||||||
|
|
||||||
|
.. _fig_clb_arch:
|
||||||
|
|
||||||
|
.. figure:: ./figures/clb_arch.png
|
||||||
|
:scale: 60%
|
||||||
|
:alt: Configurable Logic Block schematic
|
||||||
|
|
||||||
|
Configurable logic block and its chain connections across FPGA
|
||||||
|
|
||||||
|
|
||||||
Binary file not shown.
|
After Width: | Height: | Size: 76 KiB |
|
|
@ -0,0 +1,7 @@
|
||||||
|
.. _arch:
|
||||||
|
Architecture
|
||||||
|
|
||||||
|
.. toctree::
|
||||||
|
:maxdepth: 2
|
||||||
|
|
||||||
|
clb
|
||||||
|
|
@ -0,0 +1,201 @@
|
||||||
|
# -*- coding: utf-8 -*-
|
||||||
|
#
|
||||||
|
# Configuration file for the Sphinx documentation builder.
|
||||||
|
#
|
||||||
|
# This file does only contain a selection of the most common options. For a
|
||||||
|
# full list see the documentation:
|
||||||
|
# http://www.sphinx-doc.org/en/master/config
|
||||||
|
|
||||||
|
# -- Path setup --------------------------------------------------------------
|
||||||
|
|
||||||
|
# If extensions (or modules to document with autodoc) are in another directory,
|
||||||
|
# add these directories to sys.path here. If the directory is relative to the
|
||||||
|
# documentation root, use os.path.abspath to make it absolute, like shown here.
|
||||||
|
#
|
||||||
|
import sys
|
||||||
|
import os
|
||||||
|
import shlex
|
||||||
|
# sys.path.insert(0, os.path.abspath('.'))
|
||||||
|
|
||||||
|
import sphinx_rtd_theme
|
||||||
|
|
||||||
|
# Uncomment for local build
|
||||||
|
#html_theme = "sphinx_rtd_theme"
|
||||||
|
#html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
|
||||||
|
|
||||||
|
# Import sphinxcontrib.bibtex
|
||||||
|
have_sphinxcontrib_bibtex = True
|
||||||
|
try:
|
||||||
|
import sphinxcontrib.bibtex
|
||||||
|
except ImportError:
|
||||||
|
have_sphinxcontrib_bibtex = False
|
||||||
|
|
||||||
|
# -- Project information -----------------------------------------------------
|
||||||
|
|
||||||
|
project = u'Skywater-OpenFPGA Chips'
|
||||||
|
copyright = u'2020, Xifan Tang'
|
||||||
|
author = u'Xifan Tang'
|
||||||
|
|
||||||
|
# The short X.Y version
|
||||||
|
version = u''
|
||||||
|
# The full version, including alpha/beta/rc tags
|
||||||
|
release = u'1.0'
|
||||||
|
|
||||||
|
|
||||||
|
# -- General configuration ---------------------------------------------------
|
||||||
|
|
||||||
|
# If your documentation needs a minimal Sphinx version, state it here.
|
||||||
|
#
|
||||||
|
# needs_sphinx = '1.0'
|
||||||
|
|
||||||
|
# Add any Sphinx extension module names here, as strings. They can be
|
||||||
|
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
|
||||||
|
# ones.
|
||||||
|
extensions = [
|
||||||
|
'sphinx.ext.todo',
|
||||||
|
'sphinx.ext.mathjax',
|
||||||
|
'sphinx.ext.graphviz',
|
||||||
|
'sphinxcontrib.bibtex',
|
||||||
|
'sphinx.ext.autosectionlabel',
|
||||||
|
]
|
||||||
|
|
||||||
|
# Add any paths that contain templates here, relative to this directory.
|
||||||
|
#templates_path = ['ytemplates']
|
||||||
|
templates_path = [sphinx_rtd_theme.get_html_theme_path()]
|
||||||
|
|
||||||
|
# The suffix(es) of source filenames.
|
||||||
|
# You can specify multiple suffix as a list of string:
|
||||||
|
#
|
||||||
|
# source_suffix = ['.rst', '.md']
|
||||||
|
source_suffix = '.rst'
|
||||||
|
|
||||||
|
# The master toctree document.
|
||||||
|
master_doc = 'index'
|
||||||
|
|
||||||
|
# The language for content autogenerated by Sphinx. Refer to documentation
|
||||||
|
# for a list of supported languages.
|
||||||
|
#
|
||||||
|
# This is also used if you do content translation via gettext catalogs.
|
||||||
|
# Usually you set "language" from the command line for these cases.
|
||||||
|
language = None
|
||||||
|
|
||||||
|
# List of patterns, relative to source directory, that match files and
|
||||||
|
# directories to ignore when looking for source files.
|
||||||
|
# This pattern also affects html_static_path and html_extra_path.
|
||||||
|
exclude_patterns = []
|
||||||
|
|
||||||
|
# The name of the Pygments (syntax highlighting) style to use.
|
||||||
|
pygments_style = 'sphinx'
|
||||||
|
|
||||||
|
# If true, `todo` and `todoList` produce output, else they produce nothing.
|
||||||
|
todo_include_todos = True
|
||||||
|
|
||||||
|
# Number figures for referencing
|
||||||
|
numfig = True
|
||||||
|
|
||||||
|
|
||||||
|
# -- Options for HTML output -------------------------------------------------
|
||||||
|
|
||||||
|
# The theme to use for HTML and HTML Help pages. See the documentation for
|
||||||
|
# a list of builtin themes.
|
||||||
|
#
|
||||||
|
#html_theme = 'alabaster'
|
||||||
|
html_theme = 'sphinx_rtd_theme'
|
||||||
|
|
||||||
|
# Theme options are theme-specific and customize the look and feel of a theme
|
||||||
|
# further. For a list of options available for each theme, see the
|
||||||
|
# documentation.
|
||||||
|
#
|
||||||
|
# Comment when using local build
|
||||||
|
# Uncomment when using readthedocs build
|
||||||
|
#html_theme_options = {sphinx_rtd_theme}
|
||||||
|
|
||||||
|
# Add any paths that contain custom static files (such as style sheets) here,
|
||||||
|
# relative to this directory. They are copied after the builtin static files,
|
||||||
|
# so a file named "default.css" will overwrite the builtin "default.css".
|
||||||
|
#html_static_path = ['ystatic']
|
||||||
|
|
||||||
|
# Custom sidebar templates, must be a dictionary that maps document names
|
||||||
|
# to template names.
|
||||||
|
#
|
||||||
|
# The default sidebars (for documents that don't match any pattern) are
|
||||||
|
# defined by theme itself. Builtin themes are using these templates by
|
||||||
|
# default: ``['localtoc.html', 'relations.html', 'sourcelink.html',
|
||||||
|
# 'searchbox.html']``.
|
||||||
|
#
|
||||||
|
# html_sidebars = {}
|
||||||
|
|
||||||
|
|
||||||
|
# -- Options for HTMLHelp output ---------------------------------------------
|
||||||
|
|
||||||
|
# Output file base name for HTML help builder.
|
||||||
|
htmlhelp_basename = 'OpenFPGAdoc'
|
||||||
|
|
||||||
|
|
||||||
|
# -- Options for LaTeX output ------------------------------------------------
|
||||||
|
|
||||||
|
latex_elements = {
|
||||||
|
# The paper size ('letterpaper' or 'a4paper').
|
||||||
|
#
|
||||||
|
# 'papersize': 'letterpaper',
|
||||||
|
|
||||||
|
# The font size ('10pt', '11pt' or '12pt').
|
||||||
|
#
|
||||||
|
# 'pointsize': '10pt',
|
||||||
|
|
||||||
|
# Additional stuff for the LaTeX preamble.
|
||||||
|
#
|
||||||
|
# 'preamble': '',
|
||||||
|
|
||||||
|
# Latex figure (float) alignment
|
||||||
|
#
|
||||||
|
# 'figure_align': 'htbp',
|
||||||
|
}
|
||||||
|
|
||||||
|
# Grouping the document tree into LaTeX files. List of tuples
|
||||||
|
# (source start file, target name, title,
|
||||||
|
# author, documentclass [howto, manual, or own class]).
|
||||||
|
latex_documents = [
|
||||||
|
(master_doc, 'OpenFPGA.tex', u'OpenFPGA Documentation',
|
||||||
|
u'Xifan Tang', 'manual'),
|
||||||
|
]
|
||||||
|
|
||||||
|
|
||||||
|
# -- Options for manual page output ------------------------------------------
|
||||||
|
|
||||||
|
# One entry per manual page. List of tuples
|
||||||
|
# (source start file, name, description, authors, manual section).
|
||||||
|
man_pages = [
|
||||||
|
(master_doc, 'openfpga', u'OpenFPGA Documentation',
|
||||||
|
[author], 1)
|
||||||
|
]
|
||||||
|
|
||||||
|
|
||||||
|
# -- Options for Texinfo output ----------------------------------------------
|
||||||
|
|
||||||
|
# Grouping the document tree into Texinfo files. List of tuples
|
||||||
|
# (source start file, target name, title, author,
|
||||||
|
# dir menu entry, description, category)
|
||||||
|
texinfo_documents = [
|
||||||
|
(master_doc, 'Skywater-OpenFPGA', u'Skywater-OpenFPGA Documentation',
|
||||||
|
author, 'Skywater-OpenFPGA', 'Open-source FPGA chips built with Skywater PDK and OpenFPGA.',
|
||||||
|
'Miscellaneous'),
|
||||||
|
]
|
||||||
|
|
||||||
|
|
||||||
|
# -- Options for Epub output -------------------------------------------------
|
||||||
|
|
||||||
|
# Bibliographic Dublin Core info.
|
||||||
|
epub_title = project
|
||||||
|
|
||||||
|
# The unique identifier of the text. This can be a ISBN number
|
||||||
|
# or the project homepage.
|
||||||
|
#
|
||||||
|
# epub_identifier = ''
|
||||||
|
|
||||||
|
# A unique identification for the text.
|
||||||
|
#
|
||||||
|
# epub_uid = ''
|
||||||
|
|
||||||
|
# A list of files that should not be packed into the epub file.
|
||||||
|
epub_exclude_files = ['search.html']
|
||||||
|
|
@ -0,0 +1,22 @@
|
||||||
|
.. _contact:
|
||||||
|
|
||||||
|
Contacts
|
||||||
|
~~~~~~~~
|
||||||
|
|
||||||
|
.. option:: General Questions
|
||||||
|
|
||||||
|
Prof. Pierre-Emmanuel Gaillardon
|
||||||
|
|
||||||
|
pierre-emmanuel.gaillardon@utah.edu
|
||||||
|
|
||||||
|
.. option:: Technical Questions about OpenFPGA
|
||||||
|
|
||||||
|
Prof. Xifan Tang
|
||||||
|
|
||||||
|
xifan.tang@utah.edu
|
||||||
|
|
||||||
|
.. option:: Technical Questions about Physical Design
|
||||||
|
|
||||||
|
Ganesh Gore
|
||||||
|
|
||||||
|
ganesh.gore@utah.edu
|
||||||
|
|
@ -0,0 +1,68 @@
|
||||||
|
DC and AC Characteristics
|
||||||
|
-------------------------
|
||||||
|
|
||||||
|
Each FPGA device contains 37 I/O pins, whose details are summarized in the following tables.
|
||||||
|
|
||||||
|
I/O usage and port information
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
.. table:: I/O usage and sizes
|
||||||
|
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| I/O Type | Description | No. of Pins |
|
||||||
|
+===========+========================================================================+=============+
|
||||||
|
| Data I/O | Datapath I/Os of FPGA fabric | 30 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| Clk | Operating clock of FPGA core | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| ProgClk | Clock used by configuration protocol to program FPGA fabric | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| CCin | Input of configuation protocol to load bitstream | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| CCout | Output of configuration protocol to read back bitstream | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| TestEn | Activate the test mode of FPGA fabric | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| SCin | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| SCout | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| Total | | 37 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
|
||||||
|
Recommended Operating Conditions
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
.. table:: Recommended Operating Conditions
|
||||||
|
|
||||||
|
+----------+------------------------------+------+------+-------+
|
||||||
|
| Symbol | Description | Min | Max | Units |
|
||||||
|
+==========+==============================+======+======+=======+
|
||||||
|
| VDD_io | Supply voltage for I/Os | TBD | TBD | V |
|
||||||
|
+----------+------------------------------+------+------+-------+
|
||||||
|
| VDD_core | Supply voltage for FPGA core | TBD | TBD | V |
|
||||||
|
+----------+------------------------------+------+------+-------+
|
||||||
|
| V_in | Input voltage for other I/Os | TBD | TBD | V |
|
||||||
|
+----------+------------------------------+------+------+-------+
|
||||||
|
| I_in | Maximum current through pins | N/A | TBD | mA |
|
||||||
|
+----------+------------------------------+------+------+-------+
|
||||||
|
| f_max | Maximum frequency of I/Os | N/A | TBD | MHz |
|
||||||
|
+----------+------------------------------+------+------+-------+
|
||||||
|
|
||||||
|
Typical AC Characteristics
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
.. table:: Typical AC characteristics for FPGA I/Os
|
||||||
|
|
||||||
|
+-----------------+-------------------------------------------+------+------+-------+
|
||||||
|
| Symbol | Description | Min | Max | Units |
|
||||||
|
+=================+===========================================+======+======+=======+
|
||||||
|
| V_in Overshoot | Maximum allowed overshoot voltage for Vin | TBD | TBD | V |
|
||||||
|
+-----------------+-------------------------------------------+------+------+-------+
|
||||||
|
| V_in Undershoot | Minimum allowed overshoot voltage for Vin | TBD | TBD | V |
|
||||||
|
+-----------------+-------------------------------------------+------+------+-------+
|
||||||
|
| I_VDD_core | Quiescent VDD_core supply current | TBD | TBD | mA |
|
||||||
|
+-----------------+-------------------------------------------+------+------+-------+
|
||||||
|
| I_VDD_io | Quiescent VDD_io supply current | TBD | TBD | mA |
|
||||||
|
+-----------------+-------------------------------------------+------+------+-------+
|
||||||
|
|
||||||
Binary file not shown.
|
After Width: | Height: | Size: 326 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 153 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 95 KiB |
|
|
@ -0,0 +1,43 @@
|
||||||
|
.. OpenFPGA documentation master file, created by
|
||||||
|
sphinx-quickstart on Thu Sep 13 12:15:14 2018.
|
||||||
|
You can adapt this file completely to your liking, but it should at least
|
||||||
|
contain the root `toctree` directive.
|
||||||
|
|
||||||
|
Welcome to FROG's documentation!
|
||||||
|
====================================
|
||||||
|
|
||||||
|
.. toctree::
|
||||||
|
:caption: Device
|
||||||
|
|
||||||
|
technical_highlights
|
||||||
|
|
||||||
|
dc_ac_character
|
||||||
|
|
||||||
|
.. toctree::
|
||||||
|
:maxdepth: 2
|
||||||
|
:caption: Architecture
|
||||||
|
|
||||||
|
arch/index
|
||||||
|
|
||||||
|
.. toctree::
|
||||||
|
:maxdepth: 2
|
||||||
|
:caption: Appendix
|
||||||
|
|
||||||
|
contact
|
||||||
|
|
||||||
|
acknowledgment
|
||||||
|
|
||||||
|
For more information on the OpenFPGA see openfpga_doc_ or openfpga_github_
|
||||||
|
|
||||||
|
For more information on the original FPGA architecture description language see xml_vtr_
|
||||||
|
|
||||||
|
Indices and tables
|
||||||
|
==================
|
||||||
|
|
||||||
|
* :ref:`genindex`
|
||||||
|
* :ref:`modindex`
|
||||||
|
* :ref:`search`
|
||||||
|
|
||||||
|
.. _openfpga_doc: https://docs.verilogtorouting.org/en/latest/
|
||||||
|
.. _openfpga_github: https://github.com/verilog-to-routing/vtr-verilog-to-routing
|
||||||
|
.. _xml_vtr: https://docs.verilogtorouting.org/en/latest/arch/reference/
|
||||||
|
|
@ -0,0 +1,36 @@
|
||||||
|
Device Overview
|
||||||
|
---------------
|
||||||
|
|
||||||
|
All the FPGA devices in this project are fully open-source, from the architecture description to the physical design outputs, e.g., GDSII.
|
||||||
|
All the devices are designed through the OpenFPGA framework and the Skywater 130nm PDK.
|
||||||
|
The devices are embedded FPGA IPs, which are designed to interface the caravel SoC interface.
|
||||||
|
We aims to empower embedded applications with its low-cost design approach but high-density architecture.
|
||||||
|
|
||||||
|
|
||||||
|
- Native support on shift registers
|
||||||
|
|
||||||
|
- Operating temperature ranging from 0 :math:`^\circ C` to 85 :math:`^\circ C`
|
||||||
|
|
||||||
|
|
||||||
|
.. table:: Logic capacity of High Density (HD) FPGA IP
|
||||||
|
|
||||||
|
+--------------------------+------------+
|
||||||
|
| Resource Type | Capacity |
|
||||||
|
+==========================+============+
|
||||||
|
| Look-Up Tables [1]_ | 1152 |
|
||||||
|
+--------------------------+------------+
|
||||||
|
| Flip-flops | 2204 |
|
||||||
|
+--------------------------+------------+
|
||||||
|
| Max. Configuration Speed | TBD |
|
||||||
|
+--------------------------+------------+
|
||||||
|
| Max. Operating Speed | TBD |
|
||||||
|
+--------------------------+------------+
|
||||||
|
| User I/O Pins | 30 |
|
||||||
|
+--------------------------+------------+
|
||||||
|
| Max. I/O Speed | TBD |
|
||||||
|
+--------------------------+------------+
|
||||||
|
| Core Voltage | 1.8V |
|
||||||
|
+--------------------------+------------+
|
||||||
|
|
||||||
|
.. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT.
|
||||||
|
|
||||||
|
|
@ -57,6 +57,9 @@ module caravel_fpga_wrapper (
|
||||||
wire sc_head;
|
wire sc_head;
|
||||||
wire sc_tail;
|
wire sc_tail;
|
||||||
|
|
||||||
|
// Switch between wishbone and logic analyzer
|
||||||
|
wire wb_la_switch;
|
||||||
|
|
||||||
// Wire-bond TOP side I/O of FPGA to LEFT-side of Caravel interface
|
// Wire-bond TOP side I/O of FPGA to LEFT-side of Caravel interface
|
||||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[0] = io_in[24];
|
assign gfpga_pad_EMBEDDED_IO_SOC_IN[0] = io_in[24];
|
||||||
assign io_out[24] = gfpga_pad_EMBEDDED_IO_SOC_OUT[0];
|
assign io_out[24] = gfpga_pad_EMBEDDED_IO_SOC_OUT[0];
|
||||||
|
|
@ -88,7 +91,7 @@ module caravel_fpga_wrapper (
|
||||||
assign io_out[0] = 1'b0;
|
assign io_out[0] = 1'b0;
|
||||||
assign io_oeb[0] = 1'b1;
|
assign io_oeb[0] = 1'b1;
|
||||||
|
|
||||||
// Wire-bond RIGHT side I/O of FPGA to BOTTOm-side of Caravel interface
|
// Wire-bond RIGHT side I/O of FPGA to BOTTOM-side of Caravel interface
|
||||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[22:23] = la_data_in[0:1];
|
assign gfpga_pad_EMBEDDED_IO_SOC_IN[22:23] = la_data_in[0:1];
|
||||||
assign la_data_in[0:1] = gfpga_pad_EMBEDDED_IO_SOC_OUT[22:23];
|
assign la_data_in[0:1] = gfpga_pad_EMBEDDED_IO_SOC_OUT[22:23];
|
||||||
assign la_data_in[0:1] = gfpga_pad_EMBEDDED_IO_SOC_DIR[22:23];
|
assign la_data_in[0:1] = gfpga_pad_EMBEDDED_IO_SOC_DIR[22:23];
|
||||||
|
|
@ -99,9 +102,9 @@ module caravel_fpga_wrapper (
|
||||||
assign la_data_in[2:73] = gfpga_pad_EMBEDDED_IO_SOC_DIR[24:95];
|
assign la_data_in[2:73] = gfpga_pad_EMBEDDED_IO_SOC_DIR[24:95];
|
||||||
|
|
||||||
// Wire-bond LEFT side I/O of FPGA to BOTTOM-side of Caravel interface
|
// Wire-bond LEFT side I/O of FPGA to BOTTOM-side of Caravel interface
|
||||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[96:98] = la_data_in[74:76];
|
assign gfpga_pad_EMBEDDED_IO_SOC_IN[96:99] = la_data_in[74:77];
|
||||||
assign la_data_in[74:76] = gfpga_pad_EMBEDDED_IO_SOC_OUT[96:98];
|
assign la_data_in[74:77] = gfpga_pad_EMBEDDED_IO_SOC_OUT[96:99];
|
||||||
assign la_data_in[74:76] = gfpga_pad_EMBEDDED_IO_SOC_DIR[96:98];
|
assign la_data_in[74:77] = gfpga_pad_EMBEDDED_IO_SOC_DIR[96:99];
|
||||||
|
|
||||||
// Wire-bond LEFT side I/O of FPGA to LEFT-side of Caravel interface
|
// Wire-bond LEFT side I/O of FPGA to LEFT-side of Caravel interface
|
||||||
assign prog_clk = io_in[37];
|
assign prog_clk = io_in[37];
|
||||||
|
|
@ -115,11 +118,17 @@ module caravel_fpga_wrapper (
|
||||||
assign io_out[35] = ccff_tail;
|
assign io_out[35] = ccff_tail;
|
||||||
assign io_oeb[35] = 1'b0;
|
assign io_oeb[35] = 1'b0;
|
||||||
|
|
||||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[99:107] = io_in[34:26];
|
assign gfpga_pad_EMBEDDED_IO_SOC_IN[100:107] = io_in[34:27];
|
||||||
assign io_out[34:26] = gfpga_pad_EMBEDDED_IO_SOC_OUT[99:107];
|
assign io_out[34:27] = gfpga_pad_EMBEDDED_IO_SOC_OUT[100:107];
|
||||||
assign io_oeb[34:26] = gfpga_pad_EMBEDDED_IO_SOC_DIR[99:107];
|
assign io_oeb[34:27] = gfpga_pad_EMBEDDED_IO_SOC_DIR[100:107];
|
||||||
|
|
||||||
assign sc_in = io_in[25];
|
assign sc_in = io_in[26];
|
||||||
|
assign io_out[26] = 1'b0;
|
||||||
|
assign io_oeb[26] = 1'b1;
|
||||||
|
|
||||||
|
// I/O[25] is reserved for a switch between wishbone interface
|
||||||
|
// and logic analyzer
|
||||||
|
assign wb_la_switch = io_in[25];
|
||||||
assign io_out[25] = 1'b0;
|
assign io_out[25] = 1'b0;
|
||||||
assign io_oeb[25] = 1'b1;
|
assign io_oeb[25] = 1'b1;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,38 @@
|
||||||
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||||
|
# Configuration file for running experiments
|
||||||
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||||
|
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||||
|
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||||
|
# timeout_each_job is timeout for each job
|
||||||
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||||
|
|
||||||
|
[GENERAL]
|
||||||
|
run_engine=openfpga_shell
|
||||||
|
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||||
|
power_analysis = true
|
||||||
|
spice_output=false
|
||||||
|
verilog_output=true
|
||||||
|
timeout_each_job = 1*60
|
||||||
|
fpga_flow=yosys_vpr
|
||||||
|
|
||||||
|
[OpenFPGA_SHELL]
|
||||||
|
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
|
||||||
|
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
|
||||||
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
|
openfpga_vpr_device_layout=12x12
|
||||||
|
openfpga_vpr_route_chan_width=40
|
||||||
|
openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc
|
||||||
|
openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc
|
||||||
|
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
|
||||||
|
|
||||||
|
[ARCHITECTURES]
|
||||||
|
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
|
||||||
|
|
||||||
|
[BENCHMARKS]
|
||||||
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||||
|
|
||||||
|
[SYNTHESIS_PARAM]
|
||||||
|
bench0_top = and2
|
||||||
|
|
||||||
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
|
#end_flow_with_test=
|
||||||
|
|
@ -0,0 +1,37 @@
|
||||||
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||||
|
# Configuration file for running experiments
|
||||||
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||||
|
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||||
|
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||||
|
# timeout_each_job is timeout for each job
|
||||||
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||||
|
|
||||||
|
[GENERAL]
|
||||||
|
run_engine=openfpga_shell
|
||||||
|
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||||
|
power_analysis = true
|
||||||
|
spice_output=false
|
||||||
|
verilog_output=true
|
||||||
|
timeout_each_job = 1*60
|
||||||
|
fpga_flow=yosys_vpr
|
||||||
|
|
||||||
|
[OpenFPGA_SHELL]
|
||||||
|
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
|
||||||
|
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
|
||||||
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
|
openfpga_vpr_device_layout=12x12
|
||||||
|
openfpga_vpr_route_chan_width=40
|
||||||
|
openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc
|
||||||
|
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
|
||||||
|
|
||||||
|
[ARCHITECTURES]
|
||||||
|
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
|
||||||
|
|
||||||
|
[BENCHMARKS]
|
||||||
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||||
|
|
||||||
|
[SYNTHESIS_PARAM]
|
||||||
|
bench0_top = and2
|
||||||
|
|
||||||
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
|
#end_flow_with_test=
|
||||||
|
|
@ -0,0 +1,38 @@
|
||||||
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||||
|
# Configuration file for running experiments
|
||||||
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||||
|
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||||
|
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||||
|
# timeout_each_job is timeout for each job
|
||||||
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||||
|
|
||||||
|
[GENERAL]
|
||||||
|
run_engine=openfpga_shell
|
||||||
|
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||||
|
power_analysis = true
|
||||||
|
spice_output=false
|
||||||
|
verilog_output=true
|
||||||
|
timeout_each_job = 1*60
|
||||||
|
fpga_flow=yosys_vpr
|
||||||
|
|
||||||
|
[OpenFPGA_SHELL]
|
||||||
|
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
|
||||||
|
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
|
||||||
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
|
openfpga_vpr_device_layout=12x12
|
||||||
|
openfpga_vpr_route_chan_width=40
|
||||||
|
openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc
|
||||||
|
openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v
|
||||||
|
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
|
||||||
|
|
||||||
|
[ARCHITECTURES]
|
||||||
|
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
|
||||||
|
|
||||||
|
[BENCHMARKS]
|
||||||
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||||
|
|
||||||
|
[SYNTHESIS_PARAM]
|
||||||
|
bench0_top = and2
|
||||||
|
|
||||||
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
|
#end_flow_with_test=
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,67 @@
|
||||||
|
//-------------------------------------------
|
||||||
|
// FPGA Synthesizable Verilog Netlist
|
||||||
|
// Description: Netlist Summary
|
||||||
|
// Author: Xifan TANG
|
||||||
|
// Organization: University of Utah
|
||||||
|
// Date: Wed Nov 11 16:01:30 2020
|
||||||
|
//-------------------------------------------
|
||||||
|
//----- Time scale -----
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
// ------ Include simulation defines -----
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/define_simulation.v"
|
||||||
|
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
|
||||||
|
|
||||||
|
// ------ Include Skywater cell netlists -----
|
||||||
|
// Cells already used pre-PnR
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
|
||||||
|
|
||||||
|
// Cells added due to their use in PnR
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v"
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v"
|
||||||
|
|
||||||
|
// ------ Include fabric top-level netlists -----
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
|
||||||
|
|
||||||
|
|
||||||
|
`ifdef AUTOCHECKED_SIMULATION
|
||||||
|
`include "and2_output_verilog.v"
|
||||||
|
`endif
|
||||||
|
|
||||||
|
`ifdef AUTOCHECKED_SIMULATION
|
||||||
|
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v"
|
||||||
|
`endif
|
||||||
|
|
||||||
Loading…
Reference in New Issue