mirror of https://github.com/lnis-uofu/SOFA.git
Merge branch 'master' into arch_exploration
This commit is contained in:
Andrew Pond
commit
317e149d95
|
|
@ -36,7 +36,7 @@ jobs:
|
|||
${{ matrix.config.name }}_PNR/*_task/**
|
||||
- name: Running benchmark
|
||||
shell: bash
|
||||
if: ${{ env.GIT_DIFF || (github.event_name == 'pull_request' && github.ref == 'refs/heads/master') }}
|
||||
if: ${{ env.GIT_DIFF || (github.event_name == 'pull_request' && github.ref == 'refs/heads/master') || (github.ref == 'refs/heads/master') }}
|
||||
run: |
|
||||
${PYTHON_EXEC} -m pip install -r requirements.txt
|
||||
cat ${{ matrix.config.name }}_PNR/${{ matrix.config.name }}_task/config/task_simulation.conf
|
||||
|
|
|
|||
|
|
@ -14,4 +14,5 @@
|
|||
*/runOpenFPGA
|
||||
**/*_task/latest
|
||||
**/*_task/run**
|
||||
**/*_task/config/task.conf
|
||||
**/*_task/config/task.conf
|
||||
.vscode/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,322 @@
|
|||
<!-- Architecture annotation for OpenFPGA framework
|
||||
This annotation supports the k4_frac_cc_sky130nm.xml
|
||||
- General purpose logic block
|
||||
- K = 4, N = 8, I = 24
|
||||
- Routing architecture
|
||||
- 10% L = 1, fc_in = 0.15, Fc_out = 0.10
|
||||
- 10% L = 2, fc_in = 0.15, Fc_out = 0.10
|
||||
- 80% L = 4, fc_in = 0.15, Fc_out = 0.10
|
||||
- DSP block:
|
||||
- Multi-mode multiplier which can operate in two modes
|
||||
- Mode A: 18-bit multiplier
|
||||
- Mode B: two independent 9-bit multipliers
|
||||
- Skywater 130nm PDK
|
||||
- circuit models are binded to the opensource skywater
|
||||
foundry high-density standard cell library
|
||||
-->
|
||||
<openfpga_architecture>
|
||||
<technology_library>
|
||||
<device_library>
|
||||
<device_model name="logic" type="transistor">
|
||||
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||
<design vdd="0.9" pn_ratio="2"/>
|
||||
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||
</device_model>
|
||||
<device_model name="io" type="transistor">
|
||||
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||
<design vdd="2.5" pn_ratio="3"/>
|
||||
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||
</device_model>
|
||||
</device_library>
|
||||
<variation_library>
|
||||
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||
</variation_library>
|
||||
</technology_library>
|
||||
<circuit_library>
|
||||
<circuit_model type="inv_buf" name="inv_01" prefix="inv_01" verilog_netlist="./inv/sky130_fd_sc_hd__inv_1.v">
|
||||
<design_technology type="cmos" topology="inverter" size="1"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="Y" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_1" prefix="sky130_fd_sc_hd__inv_1" is_default="true">
|
||||
<design_technology type="cmos" topology="inverter" size="1"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="Y" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="X" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_4" prefix="sky130_fd_sc_hd__buf_4" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="X" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="Y" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true">
|
||||
<design_technology type="cmos" topology="OR"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="a" lib_name="A" size="1"/>
|
||||
<port type="input" prefix="b" lib_name="B" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="X" size="1"/>
|
||||
<delay_matrix type="rise" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<!-- Define a circuit model for the standard cell MUX2
|
||||
OpenFPGA requires the following truth table for the MUX2
|
||||
When the select signal sel is enabled, the first input, i.e., in0
|
||||
will be propagated to the output, i.e., out
|
||||
If your standard cell provider does not offer the exact truth table,
|
||||
you can simply swap the inputs as shown in the example below
|
||||
-->
|
||||
<circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1">
|
||||
<design_technology type="cmos" topology="MUX2"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in0" lib_name="A1" size="1"/>
|
||||
<port type="input" prefix="in1" lib_name="A0" size="1"/>
|
||||
<port type="input" prefix="sel" lib_name="S" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="X" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
|
||||
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
|
||||
</circuit_model>
|
||||
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="0" C="0" num_level="1"/>
|
||||
<!-- model_type could be T, res_val cap_val should be defined -->
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
|
||||
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ff" name="CUSTOM_DATAFF" prefix="CUSTOM_DATAFF" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
|
||||
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="input" prefix="DI" lib_name="SI" size="1"/>
|
||||
<port type="input" prefix="Test_en" lib_name="SE" size="1" is_global="true" default_val="0"/>
|
||||
<port type="input" prefix="R" size="1" default_val="0"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="clock" prefix="C" lib_name="CK" size="1" default_val="0" />
|
||||
<port type="sram" prefix="mode" lib_name="MODE" size="1" mode_select="true" circuit_model_name="CUSTOM_CCFF" default_val="0"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="lut" name="frac_lut4_arith" prefix="frac_lut4_arith" dump_structural_verilog="true" verilog_netlist="frac_lut4_arith.v">
|
||||
<design_technology type="cmos" fracturable_lut="true"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
|
||||
<lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
|
||||
<lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
|
||||
<lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
|
||||
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
|
||||
<port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hd__or2_1"/>
|
||||
<port type="input" prefix="cin" size="1" is_harden_lut_port="true"/>
|
||||
<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
|
||||
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
|
||||
<port type="output" prefix="cout" size="1" is_harden_lut_port="true"/>
|
||||
<port type="sram" prefix="sram" size="16"/>
|
||||
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="CUSTOM_CCFF" default_val="1"/>
|
||||
</circuit_model>
|
||||
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ccff" name="CUSTOM_CCFF" prefix="CUSTOM_CCFF" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
|
||||
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="input" prefix="scan_data_in" lib_name="SCD" size="1"/>
|
||||
<!-- This port allows readback configurable memories without modifying the storage -->
|
||||
<port type="input" prefix="config_readback" lib_name="SCE" size="1" is_global="true" default_val="0"/>
|
||||
<!-- This port allows programming circuitry is be isolated from datapath logic during programming -->
|
||||
<port type="input" prefix="config_enable" lib_name="CFGE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||
<port type="input" prefix="pReset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_prog="true" is_reset="true"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="iopad" name="EMBEDDED_IO_ISOLN" prefix="EMBEDDED_IO_ISOLN" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
|
||||
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
|
||||
<port type="input" prefix="SOC_IN" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
|
||||
<port type="output" prefix="SOC_OUT" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
|
||||
<port type="output" prefix="SOC_DIR" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
|
||||
<port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
|
||||
<port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
|
||||
<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
|
||||
<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="CUSTOM_CCFF" default_val="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="hard_logic" name="CARRY_MUX2" prefix="CARRY_MUX2" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/mux2.v">
|
||||
<design_technology type="cmos"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="a" lib_name="A0" size="1"/>
|
||||
<port type="input" prefix="b" lib_name="A1" size="1"/>
|
||||
<port type="input" prefix="cin" lib_name="S" size="1"/>
|
||||
<port type="output" prefix="cout" lib_name="Y" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="hard_logic" name="frac_mult_18x18" prefix="frac_mult_18x18" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/frac_mult_18x18.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/frac_mult_18x18.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="A" lib_name="A" size="18"/>
|
||||
<port type="input" prefix="B" lib_name="B" size="18"/>
|
||||
<port type="output" prefix="Y" lib_name="Y" size="36"/>
|
||||
<port type="sram" prefix="mode" lib_name="MODE" size="1" mode_select="true" circuit_model_name="CUSTOM_CCFF" default_val="1"/>
|
||||
</circuit_model>
|
||||
</circuit_library>
|
||||
<configuration_protocol>
|
||||
<organization type="scan_chain" circuit_model_name="CUSTOM_CCFF" num_regions="1"/>
|
||||
</configuration_protocol>
|
||||
<connection_block>
|
||||
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
|
||||
</connection_block>
|
||||
<switch_block>
|
||||
<switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
|
||||
<switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
|
||||
<switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
|
||||
</switch_block>
|
||||
<routing_segment>
|
||||
<segment name="L1" circuit_model_name="chan_segment"/>
|
||||
<segment name="L2" circuit_model_name="chan_segment"/>
|
||||
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||
</routing_segment>
|
||||
<direct_connection>
|
||||
<direct name="carry_chain" circuit_model_name="direct_interc"/>
|
||||
<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
|
||||
</direct_connection>
|
||||
<tile_annotations>
|
||||
<global_port name="clk" is_clock="true" default_val="0">
|
||||
<tile name="clb" port="clk" x="-1" y="-1"/>
|
||||
</global_port>
|
||||
<global_port name="Reset" is_reset="true" default_val="1">
|
||||
<tile name="clb" port="reset" x="-1" y="-1"/>
|
||||
</global_port>
|
||||
</tile_annotations>
|
||||
<pb_type_annotations>
|
||||
<!-- physical pb_type binding in complex block IO -->
|
||||
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||
<!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
|
||||
<pb_type name="io[physical].iopad" circuit_model_name="EMBEDDED_IO_ISOLN" mode_bits="1"/>
|
||||
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
|
||||
<!-- physical pb_type binding in complex block CLB -->
|
||||
<!-- physical mode will be the default mode if not specified -->
|
||||
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
||||
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" circuit_model_name="frac_lut4_arith" mode_bits="00"/>
|
||||
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="CUSTOM_DATAFF" mode_bits="0"/>
|
||||
<!-- Binding operating pb_type to physical pb_type -->
|
||||
<!-- Binding operating pb_types in mode 'arithmetic' -->
|
||||
<pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" mode_bits="11"/>
|
||||
<!-- Binding operating pb_types in mode 'n2_lut3' -->
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" mode_bits="01" physical_pb_type_index_factor="0.5">
|
||||
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
|
||||
<port name="in" physical_mode_port="in[0:2]"/>
|
||||
<port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0">
|
||||
<port name="clk" physical_mode_port="C"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1">
|
||||
<port name="RN" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<!-- Binding operating pb_types in mode 'ble4' -->
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" mode_bits="00">
|
||||
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
|
||||
<port name="in" physical_mode_port="in[0:3]"/>
|
||||
<port name="out" physical_mode_port="lut4_out"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
|
||||
<port name="clk" physical_mode_port="C"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
|
||||
<port name="RN" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<!-- End physical pb_type binding in complex block CLB -->
|
||||
|
||||
<!-- physical pb_type binding in complex block dsp -->
|
||||
<pb_type name="mult_18" physical_mode_name="mult_18x18"/>
|
||||
<!-- Bind the primitive pb_type in the physical mode to a circuit model -->
|
||||
<pb_type name="mult_18[mult_18x18].mult_18x18_slice.mult_18x18" circuit_model_name="frac_mult_18x18" mode_bits="0"/>
|
||||
<pb_type name="mult_18[mult_9x9].mult_9x9_slice.mult_9x9" physical_pb_type_name="mult_18[mult_18x18].mult_18x18_slice.mult_18x18" mode_bits="1" physical_pb_type_index_factor="0">
|
||||
<port name="A" physical_mode_port="A[0:8]" physical_mode_port_rotate_offset="9"/>
|
||||
<port name="B" physical_mode_port="B[0:8]" physical_mode_port_rotate_offset="9"/>
|
||||
<port name="Y" physical_mode_port="Y[0:17]" physical_mode_port_rotate_offset="18"/>
|
||||
</pb_type>
|
||||
</pb_type_annotations>
|
||||
</openfpga_architecture>
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
L1_SB_MUX_DELAY: 1.44e-9
|
||||
L2_SB_MUX_DELAY: 1.44e-9
|
||||
L4_SB_MUX_DELAY: 1.44e-9
|
||||
CB_MUX_DELAY: 1.38e-9
|
||||
L1_WIRE_R: 100
|
||||
L1_WIRE_C: 1e-12
|
||||
L2_WIRE_R: 100
|
||||
L2_WIRE_C: 1e-12
|
||||
L4_WIRE_R: 100
|
||||
L4_WIRE_C: 1e-12
|
||||
INPAD_DELAY: 0.11e-9
|
||||
OUTPAD_DELAY: 0.11e-9
|
||||
FF_T_SETUP: 0.39e-9
|
||||
FF_T_CLK2Q: 0.43e-9
|
||||
LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
|
||||
LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
|
||||
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
|
||||
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
|
||||
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
|
||||
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
|
||||
LUT_CIN2LUT3_OUT_DELAY: 1.21e-9
|
||||
LUT_CIN2LUT4_OUT_DELAY: 1.21e-9
|
||||
LUT_CIN2COUT_DELAY: 1.21e-9
|
||||
LUT_IN2COUT_DELAY: 1.21e-9
|
||||
LUT3_DELAY: 0.92e-9
|
||||
LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
|
||||
LUT4_DELAY: 1.21e-9
|
||||
LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
|
||||
ADDER_LUT4_CIN2OUT_DELAY: 1.21e-9
|
||||
ADDER_LUT4_CIN2COUT_DELAY: 1.21e-9
|
||||
ADDER_LUT4_IN2OUT_DELAY: 1.21e-9
|
||||
ADDER_LUT4_IN2COUT_DELAY: 1.21e-9
|
||||
MULT9_A2Y_DELAY_MAX: 1.523e-9
|
||||
MULT9_A2Y_DELAY_MIN: 0.776e-9
|
||||
MULT9_B2Y_DELAY_MAX: 1.523e-9
|
||||
MULT9_B2Y_DELAY_MIN: 0.776e-9
|
||||
MULT18_A2Y_DELAY_MAX: 1.523e-9
|
||||
MULT18_A2Y_DELAY_MIN: 0.776e-9
|
||||
MULT18_B2Y_DELAY_MAX: 1.523e-9
|
||||
MULT18_B2Y_DELAY_MIN: 0.776e-9
|
||||
|
|
@ -12,6 +12,7 @@ Please reveal the following architecture features in the names to help quickly s
|
|||
- aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os.
|
||||
- multi\_io\_capacity: If I/O capacity is different on each side of FPGAs.
|
||||
- reduced\_io: If I/Os only appear a certain or multiple sides of FPGAs
|
||||
- <frac>\_dsp<M>: If the FPGA includes M-bit DSP blocks. The keyword 'frac' is to specify if the DSP block is fracturable to operate in different modes.
|
||||
- <feature\_size>: The technology node which the delay numbers are extracted from.
|
||||
|
||||
Other features are used in naming should be listed here.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,25 @@
|
|||
//-----------------------------
|
||||
// 9-bit multiplier
|
||||
//-----------------------------
|
||||
module mult_9(
|
||||
input [0:8] A,
|
||||
input [0:8] B,
|
||||
output [0:17] Y
|
||||
);
|
||||
|
||||
assign Y = A * B;
|
||||
|
||||
endmodule
|
||||
|
||||
//-----------------------------
|
||||
// 18-bit multiplier
|
||||
//-----------------------------
|
||||
module mult_18(
|
||||
input [0:17] A,
|
||||
input [0:17] B,
|
||||
output [0:35] Y
|
||||
);
|
||||
|
||||
assign Y = A * B;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
//-----------------------------
|
||||
// 9-bit multiplier
|
||||
//-----------------------------
|
||||
module mult_9x9 (
|
||||
input [0:8] A,
|
||||
input [0:8] B,
|
||||
output [0:17] Y
|
||||
);
|
||||
parameter A_SIGNED = 0;
|
||||
parameter B_SIGNED = 0;
|
||||
parameter A_WIDTH = 0;
|
||||
parameter B_WIDTH = 0;
|
||||
parameter Y_WIDTH = 0;
|
||||
|
||||
mult_9 #() _TECHMAP_REPLACE_ (
|
||||
.A (A),
|
||||
.B (B),
|
||||
.Y (Y) );
|
||||
|
||||
endmodule
|
||||
|
||||
//-----------------------------
|
||||
// 18-bit multiplier
|
||||
//-----------------------------
|
||||
module mult_18x18 (
|
||||
input [0:17] A,
|
||||
input [0:17] B,
|
||||
output [0:35] Y
|
||||
);
|
||||
parameter A_SIGNED = 0;
|
||||
parameter B_SIGNED = 0;
|
||||
parameter A_WIDTH = 0;
|
||||
parameter B_WIDTH = 0;
|
||||
parameter Y_WIDTH = 0;
|
||||
|
||||
mult_18 #() _TECHMAP_REPLACE_ (
|
||||
.A (A),
|
||||
.B (B),
|
||||
.Y (Y) );
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
|
|
@ -8,16 +8,17 @@
|
|||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_analysis = false
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = true
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 20*60
|
||||
fpga_flow=vpr_blif
|
||||
timeout_each_job = 1*60
|
||||
fpga_flow=yosys_vpr
|
||||
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
|
||||
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
|
||||
openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga
|
||||
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
|
||||
|
|
@ -28,12 +29,10 @@ openfpga_vpr_route_chan_width=60
|
|||
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif
|
||||
bench0=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench0_top = top
|
||||
bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
|
||||
bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v
|
||||
bench0_top = counter
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
vpr_fpga_verilog_formal_verification_top_netlist=
|
||||
#end_flow_with_test=
|
||||
|
|
|
|||
|
|
@ -0,0 +1,54 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = true
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 1*60
|
||||
fpga_flow=yosys_vpr
|
||||
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
|
||||
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga
|
||||
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
|
||||
openfpga_vpr_device_layout=12x12
|
||||
openfpga_vpr_route_chan_width=60
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:TASK_DIR}/BENCHMARK/and2/and2.v
|
||||
bench1=${PATH:TASK_DIR}/BENCHMARK/and2_latch/and2_latch.v
|
||||
bench2=${PATH:TASK_DIR}/BENCHMARK/bin2bcd/bin2bcd.v
|
||||
bench3=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
|
||||
bench4=${PATH:TASK_DIR}/BENCHMARK/routing_test/routing_test.v
|
||||
# RS decoder needs 1.5k LUT4, exceeding device capacity
|
||||
#bench5=${PATH:TASK_DIR}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
|
||||
bench6=${PATH:TASK_DIR}/BENCHMARK/simon_bit_serial/rtl/*.v
|
||||
bench7=${PATH:TASK_DIR}/BENCHMARK/and2_or2/and2_or2.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench0_top = and2
|
||||
bench1_top = and2_latch
|
||||
bench2_top = bin2bcd
|
||||
bench3_top = counter
|
||||
bench4_top = routing_test
|
||||
# RS decoder needs 1.5k LUT4, exceeding device capacity
|
||||
#bench5_top = rs_decoder_top
|
||||
bench6_top = top_module
|
||||
bench7_top = and2_or2
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
#end_flow_with_test=
|
||||
|
|
@ -29,26 +29,10 @@ openfpga_vpr_route_chan_width=60
|
|||
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:TASK_DIR}/BENCHMARK/and2/and2.v
|
||||
bench1=${PATH:TASK_DIR}/BENCHMARK/and2_latch/and2_latch.v
|
||||
bench2=${PATH:TASK_DIR}/BENCHMARK/bin2bcd/bin2bcd.v
|
||||
bench3=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
|
||||
bench4=${PATH:TASK_DIR}/BENCHMARK/routing_test/routing_test.v
|
||||
# RS decoder needs 1.5k LUT4, exceeding device capacity
|
||||
#bench5=${PATH:TASK_DIR}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
|
||||
bench6=${PATH:TASK_DIR}/BENCHMARK/simon_bit_serial/rtl/*.v
|
||||
bench7=${PATH:TASK_DIR}/BENCHMARK/and2_or2/and2_or2.v
|
||||
bench0=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench0_top = and2
|
||||
bench1_top = and2_latch
|
||||
bench2_top = bin2bcd
|
||||
bench3_top = counter
|
||||
bench4_top = routing_test
|
||||
# RS decoder needs 1.5k LUT4, exceeding device capacity
|
||||
#bench5_top = rs_decoder_top
|
||||
bench6_top = top_module
|
||||
bench7_top = and2_or2
|
||||
bench0_top = counter
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
#end_flow_with_test=
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@ build_fabric_bitstream --verbose
|
|||
|
||||
# Write fabric-dependent bitstream
|
||||
write_fabric_bitstream --file fabric_bitstream.xml --format xml
|
||||
write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
|
||||
|
||||
# Write the Verilog testbench for FPGA fabric
|
||||
# - We suggest the use of same output directory as fabric Verilog netlists
|
||||
|
|
@ -53,11 +54,9 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml
|
|||
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
|
||||
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
|
||||
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
|
||||
write_verilog_testbench --file ./SRC \
|
||||
write_full_testbench --file ./SRC \
|
||||
--bitstream fabric_bitstream.bit \
|
||||
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
|
||||
--print_top_testbench \
|
||||
--print_preconfig_top_testbench \
|
||||
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
|
||||
--explicit_port_mapping
|
||||
# Exclude signal initialization since it does not help simulator converge
|
||||
# due to the lack of reset pins for flip-flops
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ OPTIONS =
|
|||
.SILENT:
|
||||
.ONESHELL:
|
||||
|
||||
.PHONY: runOpenFPGA
|
||||
runOpenFPGA:
|
||||
SECONDS=0
|
||||
source config.sh
|
||||
|
|
|
|||
|
|
@ -53,11 +53,9 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml
|
|||
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
|
||||
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
|
||||
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
|
||||
write_verilog_testbench --file ./SRC \
|
||||
write_full_testbench --file ./SRC \
|
||||
--bitstream fabric_bitstream.bit
|
||||
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
|
||||
--print_top_testbench \
|
||||
--print_preconfig_top_testbench \
|
||||
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
|
||||
--explicit_port_mapping
|
||||
# Exclude signal initialization since it does not help simulator converge
|
||||
# due to the lack of reset pins for flip-flops
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@ build_fabric_bitstream --verbose
|
|||
|
||||
# Write fabric-dependent bitstream
|
||||
write_fabric_bitstream --file fabric_bitstream.xml --format xml
|
||||
write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
|
||||
|
||||
# Write the Verilog testbench for FPGA fabric
|
||||
# - We suggest the use of same output directory as fabric Verilog netlists
|
||||
|
|
@ -53,11 +54,9 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml
|
|||
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
|
||||
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
|
||||
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
|
||||
write_verilog_testbench --file ./SRC \
|
||||
write_full_testbench --file ./SRC \
|
||||
--bitstream fabric_bitstream.bit
|
||||
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
|
||||
--print_top_testbench \
|
||||
--print_preconfig_top_testbench \
|
||||
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
|
||||
--explicit_port_mapping
|
||||
# Exclude signal initialization since it does not help simulator converge
|
||||
# due to the lack of reset pins for flip-flops
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
../../BENCHMARK
|
||||
|
|
@ -0,0 +1,678 @@
|
|||
<?xml version="1.0" ?>
|
||||
<fabric_key>
|
||||
<region id="0">
|
||||
<key id="0" alias="sb_12__12_"/>
|
||||
<key id="1" alias="cbx_12__12_"/>
|
||||
<key id="2" alias="grid_io_top_top_12__13_"/>
|
||||
<key id="3" alias="sb_11__12_"/>
|
||||
<key id="4" alias="cbx_11__12_"/>
|
||||
<key id="5" alias="grid_io_top_top_11__13_"/>
|
||||
<key id="6" alias="sb_10__12_"/>
|
||||
<key id="7" alias="cbx_10__12_"/>
|
||||
<key id="8" alias="grid_io_top_top_10__13_"/>
|
||||
<key id="9" alias="sb_9__12_"/>
|
||||
<key id="10" alias="cbx_9__12_"/>
|
||||
<key id="11" alias="grid_io_top_top_9__13_"/>
|
||||
<key id="12" alias="sb_8__12_"/>
|
||||
<key id="13" alias="cbx_8__12_"/>
|
||||
<key id="14" alias="grid_io_top_top_8__13_"/>
|
||||
<key id="15" alias="sb_7__12_"/>
|
||||
<key id="16" alias="cbx_7__12_"/>
|
||||
<key id="17" alias="grid_io_top_top_7__13_"/>
|
||||
<key id="18" alias="sb_6__12_"/>
|
||||
<key id="19" alias="cbx_6__12_"/>
|
||||
<key id="20" alias="grid_io_top_top_6__13_"/>
|
||||
<key id="21" alias="sb_5__12_"/>
|
||||
<key id="22" alias="cbx_5__12_"/>
|
||||
<key id="23" alias="grid_io_top_top_5__13_"/>
|
||||
<key id="24" alias="sb_4__12_"/>
|
||||
<key id="25" alias="cbx_4__12_"/>
|
||||
<key id="26" alias="grid_io_top_top_4__13_"/>
|
||||
<key id="27" alias="sb_3__12_"/>
|
||||
<key id="28" alias="cbx_3__12_"/>
|
||||
<key id="29" alias="grid_io_top_top_3__13_"/>
|
||||
<key id="30" alias="sb_2__12_"/>
|
||||
<key id="31" alias="cbx_2__12_"/>
|
||||
<key id="32" alias="grid_io_top_top_2__13_"/>
|
||||
<key id="33" alias="sb_1__12_"/>
|
||||
<key id="34" alias="cbx_1__12_"/>
|
||||
<key id="35" alias="grid_io_top_top_1__13_"/>
|
||||
<key id="36" alias="sb_0__12_"/>
|
||||
<key id="37" alias="cby_0__12_"/>
|
||||
<key id="38" alias="grid_io_left_left_0__12_"/>
|
||||
<key id="39" alias="grid_clb_1__12_"/>
|
||||
<key id="40" alias="cby_1__12_"/>
|
||||
<key id="41" alias="grid_clb_2__12_"/>
|
||||
<key id="42" alias="cby_2__12_"/>
|
||||
<key id="43" alias="grid_clb_3__12_"/>
|
||||
<key id="44" alias="cby_3__12_"/>
|
||||
<key id="45" alias="grid_clb_4__12_"/>
|
||||
<key id="46" alias="cby_4__12_"/>
|
||||
<key id="47" alias="grid_clb_5__12_"/>
|
||||
<key id="48" alias="cby_5__12_"/>
|
||||
<key id="49" alias="grid_clb_6__12_"/>
|
||||
<key id="50" alias="cby_6__12_"/>
|
||||
<key id="51" alias="grid_clb_7__12_"/>
|
||||
<key id="52" alias="cby_7__12_"/>
|
||||
<key id="53" alias="grid_clb_8__12_"/>
|
||||
<key id="54" alias="cby_8__12_"/>
|
||||
<key id="55" alias="grid_clb_9__12_"/>
|
||||
<key id="56" alias="cby_9__12_"/>
|
||||
<key id="57" alias="grid_clb_10__12_"/>
|
||||
<key id="58" alias="cby_10__12_"/>
|
||||
<key id="59" alias="grid_clb_11__12_"/>
|
||||
<key id="60" alias="cby_11__12_"/>
|
||||
<key id="61" alias="grid_clb_12__12_"/>
|
||||
<key id="62" alias="cby_12__12_"/>
|
||||
<key id="63" alias="grid_io_right_right_13__12_"/>
|
||||
<key id="64" alias="sb_12__11_"/>
|
||||
<key id="65" alias="cbx_12__11_"/>
|
||||
<key id="66" alias="sb_11__11_"/>
|
||||
<key id="67" alias="cbx_11__11_"/>
|
||||
<key id="68" alias="sb_10__11_"/>
|
||||
<key id="69" alias="cbx_10__11_"/>
|
||||
<key id="70" alias="sb_9__11_"/>
|
||||
<key id="71" alias="cbx_9__11_"/>
|
||||
<key id="72" alias="sb_8__11_"/>
|
||||
<key id="73" alias="cbx_8__11_"/>
|
||||
<key id="74" alias="sb_7__11_"/>
|
||||
<key id="75" alias="cbx_7__11_"/>
|
||||
<key id="76" alias="sb_6__11_"/>
|
||||
<key id="77" alias="cbx_6__11_"/>
|
||||
<key id="78" alias="sb_5__11_"/>
|
||||
<key id="79" alias="cbx_5__11_"/>
|
||||
<key id="80" alias="sb_4__11_"/>
|
||||
<key id="81" alias="cbx_4__11_"/>
|
||||
<key id="82" alias="sb_3__11_"/>
|
||||
<key id="83" alias="cbx_3__11_"/>
|
||||
<key id="84" alias="sb_2__11_"/>
|
||||
<key id="85" alias="cbx_2__11_"/>
|
||||
<key id="86" alias="sb_1__11_"/>
|
||||
<key id="87" alias="cbx_1__11_"/>
|
||||
<key id="88" alias="sb_0__11_"/>
|
||||
<key id="89" alias="cby_0__11_"/>
|
||||
<key id="90" alias="grid_io_left_left_0__11_"/>
|
||||
<key id="91" alias="grid_clb_1__11_"/>
|
||||
<key id="92" alias="cby_1__11_"/>
|
||||
<key id="93" alias="grid_clb_2__11_"/>
|
||||
<key id="94" alias="cby_2__11_"/>
|
||||
<key id="95" alias="grid_clb_3__11_"/>
|
||||
<key id="96" alias="cby_3__11_"/>
|
||||
<key id="97" alias="grid_clb_4__11_"/>
|
||||
<key id="98" alias="cby_4__11_"/>
|
||||
<key id="99" alias="grid_clb_5__11_"/>
|
||||
<key id="100" alias="cby_5__11_"/>
|
||||
<key id="101" alias="grid_clb_6__11_"/>
|
||||
<key id="102" alias="cby_6__11_"/>
|
||||
<key id="103" alias="grid_clb_7__11_"/>
|
||||
<key id="104" alias="cby_7__11_"/>
|
||||
<key id="105" alias="grid_clb_8__11_"/>
|
||||
<key id="106" alias="cby_8__11_"/>
|
||||
<key id="107" alias="grid_clb_9__11_"/>
|
||||
<key id="108" alias="cby_9__11_"/>
|
||||
<key id="109" alias="grid_clb_10__11_"/>
|
||||
<key id="110" alias="cby_10__11_"/>
|
||||
<key id="111" alias="grid_clb_11__11_"/>
|
||||
<key id="112" alias="cby_11__11_"/>
|
||||
<key id="113" alias="grid_clb_12__11_"/>
|
||||
<key id="114" alias="cby_12__11_"/>
|
||||
<key id="115" alias="grid_io_right_right_13__11_"/>
|
||||
<key id="116" alias="sb_12__10_"/>
|
||||
<key id="117" alias="cbx_12__10_"/>
|
||||
<key id="118" alias="sb_11__10_"/>
|
||||
<key id="119" alias="cbx_11__10_"/>
|
||||
<key id="120" alias="sb_10__10_"/>
|
||||
<key id="121" alias="cbx_10__10_"/>
|
||||
<key id="122" alias="sb_9__10_"/>
|
||||
<key id="123" alias="cbx_9__10_"/>
|
||||
<key id="124" alias="sb_8__10_"/>
|
||||
<key id="125" alias="cbx_8__10_"/>
|
||||
<key id="126" alias="sb_7__10_"/>
|
||||
<key id="127" alias="cbx_7__10_"/>
|
||||
<key id="128" alias="sb_6__10_"/>
|
||||
<key id="129" alias="cbx_6__10_"/>
|
||||
<key id="130" alias="sb_5__10_"/>
|
||||
<key id="131" alias="cbx_5__10_"/>
|
||||
<key id="132" alias="sb_4__10_"/>
|
||||
<key id="133" alias="cbx_4__10_"/>
|
||||
<key id="134" alias="sb_3__10_"/>
|
||||
<key id="135" alias="cbx_3__10_"/>
|
||||
<key id="136" alias="sb_2__10_"/>
|
||||
<key id="137" alias="cbx_2__10_"/>
|
||||
<key id="138" alias="sb_1__10_"/>
|
||||
<key id="139" alias="cbx_1__10_"/>
|
||||
<key id="140" alias="sb_0__10_"/>
|
||||
<key id="141" alias="cby_0__10_"/>
|
||||
<key id="142" alias="grid_io_left_left_0__10_"/>
|
||||
<key id="143" alias="grid_clb_1__10_"/>
|
||||
<key id="144" alias="cby_1__10_"/>
|
||||
<key id="145" alias="grid_clb_2__10_"/>
|
||||
<key id="146" alias="cby_2__10_"/>
|
||||
<key id="147" alias="grid_clb_3__10_"/>
|
||||
<key id="148" alias="cby_3__10_"/>
|
||||
<key id="149" alias="grid_clb_4__10_"/>
|
||||
<key id="150" alias="cby_4__10_"/>
|
||||
<key id="151" alias="grid_clb_5__10_"/>
|
||||
<key id="152" alias="cby_5__10_"/>
|
||||
<key id="153" alias="grid_clb_6__10_"/>
|
||||
<key id="154" alias="cby_6__10_"/>
|
||||
<key id="155" alias="grid_clb_7__10_"/>
|
||||
<key id="156" alias="cby_7__10_"/>
|
||||
<key id="157" alias="grid_clb_8__10_"/>
|
||||
<key id="158" alias="cby_8__10_"/>
|
||||
<key id="159" alias="grid_clb_9__10_"/>
|
||||
<key id="160" alias="cby_9__10_"/>
|
||||
<key id="161" alias="grid_clb_10__10_"/>
|
||||
<key id="162" alias="cby_10__10_"/>
|
||||
<key id="163" alias="grid_clb_11__10_"/>
|
||||
<key id="164" alias="cby_11__10_"/>
|
||||
<key id="165" alias="grid_clb_12__10_"/>
|
||||
<key id="166" alias="cby_12__10_"/>
|
||||
<key id="167" alias="grid_io_right_right_13__10_"/>
|
||||
<key id="168" alias="sb_12__9_"/>
|
||||
<key id="169" alias="cbx_12__9_"/>
|
||||
<key id="170" alias="sb_11__9_"/>
|
||||
<key id="171" alias="cbx_11__9_"/>
|
||||
<key id="172" alias="sb_10__9_"/>
|
||||
<key id="173" alias="cbx_10__9_"/>
|
||||
<key id="174" alias="sb_9__9_"/>
|
||||
<key id="175" alias="cbx_9__9_"/>
|
||||
<key id="176" alias="sb_8__9_"/>
|
||||
<key id="177" alias="cbx_8__9_"/>
|
||||
<key id="178" alias="sb_7__9_"/>
|
||||
<key id="179" alias="cbx_7__9_"/>
|
||||
<key id="180" alias="sb_6__9_"/>
|
||||
<key id="181" alias="cbx_6__9_"/>
|
||||
<key id="182" alias="sb_5__9_"/>
|
||||
<key id="183" alias="cbx_5__9_"/>
|
||||
<key id="184" alias="sb_4__9_"/>
|
||||
<key id="185" alias="cbx_4__9_"/>
|
||||
<key id="186" alias="sb_3__9_"/>
|
||||
<key id="187" alias="cbx_3__9_"/>
|
||||
<key id="188" alias="sb_2__9_"/>
|
||||
<key id="189" alias="cbx_2__9_"/>
|
||||
<key id="190" alias="sb_1__9_"/>
|
||||
<key id="191" alias="cbx_1__9_"/>
|
||||
<key id="192" alias="sb_0__9_"/>
|
||||
<key id="193" alias="cby_0__9_"/>
|
||||
<key id="194" alias="grid_io_left_left_0__9_"/>
|
||||
<key id="195" alias="grid_clb_1__9_"/>
|
||||
<key id="196" alias="cby_1__9_"/>
|
||||
<key id="197" alias="grid_clb_2__9_"/>
|
||||
<key id="198" alias="cby_2__9_"/>
|
||||
<key id="199" alias="grid_clb_3__9_"/>
|
||||
<key id="200" alias="cby_3__9_"/>
|
||||
<key id="201" alias="grid_clb_4__9_"/>
|
||||
<key id="202" alias="cby_4__9_"/>
|
||||
<key id="203" alias="grid_clb_5__9_"/>
|
||||
<key id="204" alias="cby_5__9_"/>
|
||||
<key id="205" alias="grid_clb_6__9_"/>
|
||||
<key id="206" alias="cby_6__9_"/>
|
||||
<key id="207" alias="grid_clb_7__9_"/>
|
||||
<key id="208" alias="cby_7__9_"/>
|
||||
<key id="209" alias="grid_clb_8__9_"/>
|
||||
<key id="210" alias="cby_8__9_"/>
|
||||
<key id="211" alias="grid_clb_9__9_"/>
|
||||
<key id="212" alias="cby_9__9_"/>
|
||||
<key id="213" alias="grid_clb_10__9_"/>
|
||||
<key id="214" alias="cby_10__9_"/>
|
||||
<key id="215" alias="grid_clb_11__9_"/>
|
||||
<key id="216" alias="cby_11__9_"/>
|
||||
<key id="217" alias="grid_clb_12__9_"/>
|
||||
<key id="218" alias="cby_12__9_"/>
|
||||
<key id="219" alias="grid_io_right_right_13__9_"/>
|
||||
<key id="220" alias="sb_12__8_"/>
|
||||
<key id="221" alias="cbx_12__8_"/>
|
||||
<key id="222" alias="sb_11__8_"/>
|
||||
<key id="223" alias="cbx_11__8_"/>
|
||||
<key id="224" alias="sb_10__8_"/>
|
||||
<key id="225" alias="cbx_10__8_"/>
|
||||
<key id="226" alias="sb_9__8_"/>
|
||||
<key id="227" alias="cbx_9__8_"/>
|
||||
<key id="228" alias="sb_8__8_"/>
|
||||
<key id="229" alias="cbx_8__8_"/>
|
||||
<key id="230" alias="sb_7__8_"/>
|
||||
<key id="231" alias="cbx_7__8_"/>
|
||||
<key id="232" alias="sb_6__8_"/>
|
||||
<key id="233" alias="cbx_6__8_"/>
|
||||
<key id="234" alias="sb_5__8_"/>
|
||||
<key id="235" alias="cbx_5__8_"/>
|
||||
<key id="236" alias="sb_4__8_"/>
|
||||
<key id="237" alias="cbx_4__8_"/>
|
||||
<key id="238" alias="sb_3__8_"/>
|
||||
<key id="239" alias="cbx_3__8_"/>
|
||||
<key id="240" alias="sb_2__8_"/>
|
||||
<key id="241" alias="cbx_2__8_"/>
|
||||
<key id="242" alias="sb_1__8_"/>
|
||||
<key id="243" alias="cbx_1__8_"/>
|
||||
<key id="244" alias="sb_0__8_"/>
|
||||
<key id="245" alias="cby_0__8_"/>
|
||||
<key id="246" alias="grid_io_left_left_0__8_"/>
|
||||
<key id="247" alias="grid_clb_1__8_"/>
|
||||
<key id="248" alias="cby_1__8_"/>
|
||||
<key id="249" alias="grid_clb_2__8_"/>
|
||||
<key id="250" alias="cby_2__8_"/>
|
||||
<key id="251" alias="grid_clb_3__8_"/>
|
||||
<key id="252" alias="cby_3__8_"/>
|
||||
<key id="253" alias="grid_clb_4__8_"/>
|
||||
<key id="254" alias="cby_4__8_"/>
|
||||
<key id="255" alias="grid_clb_5__8_"/>
|
||||
<key id="256" alias="cby_5__8_"/>
|
||||
<key id="257" alias="grid_clb_6__8_"/>
|
||||
<key id="258" alias="cby_6__8_"/>
|
||||
<key id="259" alias="grid_clb_7__8_"/>
|
||||
<key id="260" alias="cby_7__8_"/>
|
||||
<key id="261" alias="grid_clb_8__8_"/>
|
||||
<key id="262" alias="cby_8__8_"/>
|
||||
<key id="263" alias="grid_clb_9__8_"/>
|
||||
<key id="264" alias="cby_9__8_"/>
|
||||
<key id="265" alias="grid_clb_10__8_"/>
|
||||
<key id="266" alias="cby_10__8_"/>
|
||||
<key id="267" alias="grid_clb_11__8_"/>
|
||||
<key id="268" alias="cby_11__8_"/>
|
||||
<key id="269" alias="grid_clb_12__8_"/>
|
||||
<key id="270" alias="cby_12__8_"/>
|
||||
<key id="271" alias="grid_io_right_right_13__8_"/>
|
||||
<key id="272" alias="sb_12__7_"/>
|
||||
<key id="273" alias="cbx_12__7_"/>
|
||||
<key id="274" alias="sb_11__7_"/>
|
||||
<key id="275" alias="cbx_11__7_"/>
|
||||
<key id="276" alias="sb_10__7_"/>
|
||||
<key id="277" alias="cbx_10__7_"/>
|
||||
<key id="278" alias="sb_9__7_"/>
|
||||
<key id="279" alias="cbx_9__7_"/>
|
||||
<key id="280" alias="sb_8__7_"/>
|
||||
<key id="281" alias="cbx_8__7_"/>
|
||||
<key id="282" alias="sb_7__7_"/>
|
||||
<key id="283" alias="cbx_7__7_"/>
|
||||
<key id="284" alias="sb_6__7_"/>
|
||||
<key id="285" alias="cbx_6__7_"/>
|
||||
<key id="286" alias="sb_5__7_"/>
|
||||
<key id="287" alias="cbx_5__7_"/>
|
||||
<key id="288" alias="sb_4__7_"/>
|
||||
<key id="289" alias="cbx_4__7_"/>
|
||||
<key id="290" alias="sb_3__7_"/>
|
||||
<key id="291" alias="cbx_3__7_"/>
|
||||
<key id="292" alias="sb_2__7_"/>
|
||||
<key id="293" alias="cbx_2__7_"/>
|
||||
<key id="294" alias="sb_1__7_"/>
|
||||
<key id="295" alias="cbx_1__7_"/>
|
||||
<key id="296" alias="sb_0__7_"/>
|
||||
<key id="297" alias="cby_0__7_"/>
|
||||
<key id="298" alias="grid_io_left_left_0__7_"/>
|
||||
<key id="299" alias="grid_clb_1__7_"/>
|
||||
<key id="300" alias="cby_1__7_"/>
|
||||
<key id="301" alias="grid_clb_2__7_"/>
|
||||
<key id="302" alias="cby_2__7_"/>
|
||||
<key id="303" alias="grid_clb_3__7_"/>
|
||||
<key id="304" alias="cby_3__7_"/>
|
||||
<key id="305" alias="grid_clb_4__7_"/>
|
||||
<key id="306" alias="cby_4__7_"/>
|
||||
<key id="307" alias="grid_clb_5__7_"/>
|
||||
<key id="308" alias="cby_5__7_"/>
|
||||
<key id="309" alias="grid_clb_6__7_"/>
|
||||
<key id="310" alias="cby_6__7_"/>
|
||||
<key id="311" alias="grid_clb_7__7_"/>
|
||||
<key id="312" alias="cby_7__7_"/>
|
||||
<key id="313" alias="grid_clb_8__7_"/>
|
||||
<key id="314" alias="cby_8__7_"/>
|
||||
<key id="315" alias="grid_clb_9__7_"/>
|
||||
<key id="316" alias="cby_9__7_"/>
|
||||
<key id="317" alias="grid_clb_10__7_"/>
|
||||
<key id="318" alias="cby_10__7_"/>
|
||||
<key id="319" alias="grid_clb_11__7_"/>
|
||||
<key id="320" alias="cby_11__7_"/>
|
||||
<key id="321" alias="grid_clb_12__7_"/>
|
||||
<key id="322" alias="cby_12__7_"/>
|
||||
<key id="323" alias="grid_io_right_right_13__7_"/>
|
||||
<key id="324" alias="sb_12__6_"/>
|
||||
<key id="325" alias="cbx_12__6_"/>
|
||||
<key id="326" alias="sb_11__6_"/>
|
||||
<key id="327" alias="cbx_11__6_"/>
|
||||
<key id="328" alias="sb_10__6_"/>
|
||||
<key id="329" alias="cbx_10__6_"/>
|
||||
<key id="330" alias="sb_9__6_"/>
|
||||
<key id="331" alias="cbx_9__6_"/>
|
||||
<key id="332" alias="sb_8__6_"/>
|
||||
<key id="333" alias="cbx_8__6_"/>
|
||||
<key id="334" alias="sb_7__6_"/>
|
||||
<key id="335" alias="cbx_7__6_"/>
|
||||
<key id="336" alias="sb_6__6_"/>
|
||||
<key id="337" alias="cbx_6__6_"/>
|
||||
<key id="338" alias="sb_5__6_"/>
|
||||
<key id="339" alias="cbx_5__6_"/>
|
||||
<key id="340" alias="sb_4__6_"/>
|
||||
<key id="341" alias="cbx_4__6_"/>
|
||||
<key id="342" alias="sb_3__6_"/>
|
||||
<key id="343" alias="cbx_3__6_"/>
|
||||
<key id="344" alias="sb_2__6_"/>
|
||||
<key id="345" alias="cbx_2__6_"/>
|
||||
<key id="346" alias="sb_1__6_"/>
|
||||
<key id="347" alias="cbx_1__6_"/>
|
||||
<key id="348" alias="sb_0__6_"/>
|
||||
<key id="349" alias="cby_0__6_"/>
|
||||
<key id="350" alias="grid_io_left_left_0__6_"/>
|
||||
<key id="351" alias="grid_clb_1__6_"/>
|
||||
<key id="352" alias="cby_1__6_"/>
|
||||
<key id="353" alias="grid_clb_2__6_"/>
|
||||
<key id="354" alias="cby_2__6_"/>
|
||||
<key id="355" alias="grid_clb_3__6_"/>
|
||||
<key id="356" alias="cby_3__6_"/>
|
||||
<key id="357" alias="grid_clb_4__6_"/>
|
||||
<key id="358" alias="cby_4__6_"/>
|
||||
<key id="359" alias="grid_clb_5__6_"/>
|
||||
<key id="360" alias="cby_5__6_"/>
|
||||
<key id="361" alias="grid_clb_6__6_"/>
|
||||
<key id="362" alias="cby_6__6_"/>
|
||||
<key id="363" alias="grid_clb_7__6_"/>
|
||||
<key id="364" alias="cby_7__6_"/>
|
||||
<key id="365" alias="grid_clb_8__6_"/>
|
||||
<key id="366" alias="cby_8__6_"/>
|
||||
<key id="367" alias="grid_clb_9__6_"/>
|
||||
<key id="368" alias="cby_9__6_"/>
|
||||
<key id="369" alias="grid_clb_10__6_"/>
|
||||
<key id="370" alias="cby_10__6_"/>
|
||||
<key id="371" alias="grid_clb_11__6_"/>
|
||||
<key id="372" alias="cby_11__6_"/>
|
||||
<key id="373" alias="grid_clb_12__6_"/>
|
||||
<key id="374" alias="cby_12__6_"/>
|
||||
<key id="375" alias="grid_io_right_right_13__6_"/>
|
||||
<key id="376" alias="sb_12__5_"/>
|
||||
<key id="377" alias="cbx_12__5_"/>
|
||||
<key id="378" alias="sb_11__5_"/>
|
||||
<key id="379" alias="cbx_11__5_"/>
|
||||
<key id="380" alias="sb_10__5_"/>
|
||||
<key id="381" alias="cbx_10__5_"/>
|
||||
<key id="382" alias="sb_9__5_"/>
|
||||
<key id="383" alias="cbx_9__5_"/>
|
||||
<key id="384" alias="sb_8__5_"/>
|
||||
<key id="385" alias="cbx_8__5_"/>
|
||||
<key id="386" alias="sb_7__5_"/>
|
||||
<key id="387" alias="cbx_7__5_"/>
|
||||
<key id="388" alias="sb_6__5_"/>
|
||||
<key id="389" alias="cbx_6__5_"/>
|
||||
<key id="390" alias="sb_5__5_"/>
|
||||
<key id="391" alias="cbx_5__5_"/>
|
||||
<key id="392" alias="sb_4__5_"/>
|
||||
<key id="393" alias="cbx_4__5_"/>
|
||||
<key id="394" alias="sb_3__5_"/>
|
||||
<key id="395" alias="cbx_3__5_"/>
|
||||
<key id="396" alias="sb_2__5_"/>
|
||||
<key id="397" alias="cbx_2__5_"/>
|
||||
<key id="398" alias="sb_1__5_"/>
|
||||
<key id="399" alias="cbx_1__5_"/>
|
||||
<key id="400" alias="sb_0__5_"/>
|
||||
<key id="401" alias="cby_0__5_"/>
|
||||
<key id="402" alias="grid_io_left_left_0__5_"/>
|
||||
<key id="403" alias="grid_clb_1__5_"/>
|
||||
<key id="404" alias="cby_1__5_"/>
|
||||
<key id="405" alias="grid_clb_2__5_"/>
|
||||
<key id="406" alias="cby_2__5_"/>
|
||||
<key id="407" alias="grid_clb_3__5_"/>
|
||||
<key id="408" alias="cby_3__5_"/>
|
||||
<key id="409" alias="grid_clb_4__5_"/>
|
||||
<key id="410" alias="cby_4__5_"/>
|
||||
<key id="411" alias="grid_clb_5__5_"/>
|
||||
<key id="412" alias="cby_5__5_"/>
|
||||
<key id="413" alias="grid_clb_6__5_"/>
|
||||
<key id="414" alias="cby_6__5_"/>
|
||||
<key id="415" alias="grid_clb_7__5_"/>
|
||||
<key id="416" alias="cby_7__5_"/>
|
||||
<key id="417" alias="grid_clb_8__5_"/>
|
||||
<key id="418" alias="cby_8__5_"/>
|
||||
<key id="419" alias="grid_clb_9__5_"/>
|
||||
<key id="420" alias="cby_9__5_"/>
|
||||
<key id="421" alias="grid_clb_10__5_"/>
|
||||
<key id="422" alias="cby_10__5_"/>
|
||||
<key id="423" alias="grid_clb_11__5_"/>
|
||||
<key id="424" alias="cby_11__5_"/>
|
||||
<key id="425" alias="grid_clb_12__5_"/>
|
||||
<key id="426" alias="cby_12__5_"/>
|
||||
<key id="427" alias="grid_io_right_right_13__5_"/>
|
||||
<key id="428" alias="sb_12__4_"/>
|
||||
<key id="429" alias="cbx_12__4_"/>
|
||||
<key id="430" alias="sb_11__4_"/>
|
||||
<key id="431" alias="cbx_11__4_"/>
|
||||
<key id="432" alias="sb_10__4_"/>
|
||||
<key id="433" alias="cbx_10__4_"/>
|
||||
<key id="434" alias="sb_9__4_"/>
|
||||
<key id="435" alias="cbx_9__4_"/>
|
||||
<key id="436" alias="sb_8__4_"/>
|
||||
<key id="437" alias="cbx_8__4_"/>
|
||||
<key id="438" alias="sb_7__4_"/>
|
||||
<key id="439" alias="cbx_7__4_"/>
|
||||
<key id="440" alias="sb_6__4_"/>
|
||||
<key id="441" alias="cbx_6__4_"/>
|
||||
<key id="442" alias="sb_5__4_"/>
|
||||
<key id="443" alias="cbx_5__4_"/>
|
||||
<key id="444" alias="sb_4__4_"/>
|
||||
<key id="445" alias="cbx_4__4_"/>
|
||||
<key id="446" alias="sb_3__4_"/>
|
||||
<key id="447" alias="cbx_3__4_"/>
|
||||
<key id="448" alias="sb_2__4_"/>
|
||||
<key id="449" alias="cbx_2__4_"/>
|
||||
<key id="450" alias="sb_1__4_"/>
|
||||
<key id="451" alias="cbx_1__4_"/>
|
||||
<key id="452" alias="sb_0__4_"/>
|
||||
<key id="453" alias="cby_0__4_"/>
|
||||
<key id="454" alias="grid_io_left_left_0__4_"/>
|
||||
<key id="455" alias="grid_clb_1__4_"/>
|
||||
<key id="456" alias="cby_1__4_"/>
|
||||
<key id="457" alias="grid_clb_2__4_"/>
|
||||
<key id="458" alias="cby_2__4_"/>
|
||||
<key id="459" alias="grid_clb_3__4_"/>
|
||||
<key id="460" alias="cby_3__4_"/>
|
||||
<key id="461" alias="grid_clb_4__4_"/>
|
||||
<key id="462" alias="cby_4__4_"/>
|
||||
<key id="463" alias="grid_clb_5__4_"/>
|
||||
<key id="464" alias="cby_5__4_"/>
|
||||
<key id="465" alias="grid_clb_6__4_"/>
|
||||
<key id="466" alias="cby_6__4_"/>
|
||||
<key id="467" alias="grid_clb_7__4_"/>
|
||||
<key id="468" alias="cby_7__4_"/>
|
||||
<key id="469" alias="grid_clb_8__4_"/>
|
||||
<key id="470" alias="cby_8__4_"/>
|
||||
<key id="471" alias="grid_clb_9__4_"/>
|
||||
<key id="472" alias="cby_9__4_"/>
|
||||
<key id="473" alias="grid_clb_10__4_"/>
|
||||
<key id="474" alias="cby_10__4_"/>
|
||||
<key id="475" alias="grid_clb_11__4_"/>
|
||||
<key id="476" alias="cby_11__4_"/>
|
||||
<key id="477" alias="grid_clb_12__4_"/>
|
||||
<key id="478" alias="cby_12__4_"/>
|
||||
<key id="479" alias="grid_io_right_right_13__4_"/>
|
||||
<key id="480" alias="sb_12__3_"/>
|
||||
<key id="481" alias="cbx_12__3_"/>
|
||||
<key id="482" alias="sb_11__3_"/>
|
||||
<key id="483" alias="cbx_11__3_"/>
|
||||
<key id="484" alias="sb_10__3_"/>
|
||||
<key id="485" alias="cbx_10__3_"/>
|
||||
<key id="486" alias="sb_9__3_"/>
|
||||
<key id="487" alias="cbx_9__3_"/>
|
||||
<key id="488" alias="sb_8__3_"/>
|
||||
<key id="489" alias="cbx_8__3_"/>
|
||||
<key id="490" alias="sb_7__3_"/>
|
||||
<key id="491" alias="cbx_7__3_"/>
|
||||
<key id="492" alias="sb_6__3_"/>
|
||||
<key id="493" alias="cbx_6__3_"/>
|
||||
<key id="494" alias="sb_5__3_"/>
|
||||
<key id="495" alias="cbx_5__3_"/>
|
||||
<key id="496" alias="sb_4__3_"/>
|
||||
<key id="497" alias="cbx_4__3_"/>
|
||||
<key id="498" alias="sb_3__3_"/>
|
||||
<key id="499" alias="cbx_3__3_"/>
|
||||
<key id="500" alias="sb_2__3_"/>
|
||||
<key id="501" alias="cbx_2__3_"/>
|
||||
<key id="502" alias="sb_1__3_"/>
|
||||
<key id="503" alias="cbx_1__3_"/>
|
||||
<key id="504" alias="sb_0__3_"/>
|
||||
<key id="505" alias="cby_0__3_"/>
|
||||
<key id="506" alias="grid_io_left_left_0__3_"/>
|
||||
<key id="507" alias="grid_clb_1__3_"/>
|
||||
<key id="508" alias="cby_1__3_"/>
|
||||
<key id="509" alias="grid_clb_2__3_"/>
|
||||
<key id="510" alias="cby_2__3_"/>
|
||||
<key id="511" alias="grid_clb_3__3_"/>
|
||||
<key id="512" alias="cby_3__3_"/>
|
||||
<key id="513" alias="grid_clb_4__3_"/>
|
||||
<key id="514" alias="cby_4__3_"/>
|
||||
<key id="515" alias="grid_clb_5__3_"/>
|
||||
<key id="516" alias="cby_5__3_"/>
|
||||
<key id="517" alias="grid_clb_6__3_"/>
|
||||
<key id="518" alias="cby_6__3_"/>
|
||||
<key id="519" alias="grid_clb_7__3_"/>
|
||||
<key id="520" alias="cby_7__3_"/>
|
||||
<key id="521" alias="grid_clb_8__3_"/>
|
||||
<key id="522" alias="cby_8__3_"/>
|
||||
<key id="523" alias="grid_clb_9__3_"/>
|
||||
<key id="524" alias="cby_9__3_"/>
|
||||
<key id="525" alias="grid_clb_10__3_"/>
|
||||
<key id="526" alias="cby_10__3_"/>
|
||||
<key id="527" alias="grid_clb_11__3_"/>
|
||||
<key id="528" alias="cby_11__3_"/>
|
||||
<key id="529" alias="grid_clb_12__3_"/>
|
||||
<key id="530" alias="cby_12__3_"/>
|
||||
<key id="531" alias="grid_io_right_right_13__3_"/>
|
||||
<key id="532" alias="sb_12__2_"/>
|
||||
<key id="533" alias="cbx_12__2_"/>
|
||||
<key id="534" alias="sb_11__2_"/>
|
||||
<key id="535" alias="cbx_11__2_"/>
|
||||
<key id="536" alias="sb_10__2_"/>
|
||||
<key id="537" alias="cbx_10__2_"/>
|
||||
<key id="538" alias="sb_9__2_"/>
|
||||
<key id="539" alias="cbx_9__2_"/>
|
||||
<key id="540" alias="sb_8__2_"/>
|
||||
<key id="541" alias="cbx_8__2_"/>
|
||||
<key id="542" alias="sb_7__2_"/>
|
||||
<key id="543" alias="cbx_7__2_"/>
|
||||
<key id="544" alias="sb_6__2_"/>
|
||||
<key id="545" alias="cbx_6__2_"/>
|
||||
<key id="546" alias="sb_5__2_"/>
|
||||
<key id="547" alias="cbx_5__2_"/>
|
||||
<key id="548" alias="sb_4__2_"/>
|
||||
<key id="549" alias="cbx_4__2_"/>
|
||||
<key id="550" alias="sb_3__2_"/>
|
||||
<key id="551" alias="cbx_3__2_"/>
|
||||
<key id="552" alias="sb_2__2_"/>
|
||||
<key id="553" alias="cbx_2__2_"/>
|
||||
<key id="554" alias="sb_1__2_"/>
|
||||
<key id="555" alias="cbx_1__2_"/>
|
||||
<key id="556" alias="sb_0__2_"/>
|
||||
<key id="557" alias="cby_0__2_"/>
|
||||
<key id="558" alias="grid_io_left_left_0__2_"/>
|
||||
<key id="559" alias="grid_clb_1__2_"/>
|
||||
<key id="560" alias="cby_1__2_"/>
|
||||
<key id="561" alias="grid_clb_2__2_"/>
|
||||
<key id="562" alias="cby_2__2_"/>
|
||||
<key id="563" alias="grid_clb_3__2_"/>
|
||||
<key id="564" alias="cby_3__2_"/>
|
||||
<key id="565" alias="grid_clb_4__2_"/>
|
||||
<key id="566" alias="cby_4__2_"/>
|
||||
<key id="567" alias="grid_clb_5__2_"/>
|
||||
<key id="568" alias="cby_5__2_"/>
|
||||
<key id="569" alias="grid_clb_6__2_"/>
|
||||
<key id="570" alias="cby_6__2_"/>
|
||||
<key id="571" alias="grid_clb_7__2_"/>
|
||||
<key id="572" alias="cby_7__2_"/>
|
||||
<key id="573" alias="grid_clb_8__2_"/>
|
||||
<key id="574" alias="cby_8__2_"/>
|
||||
<key id="575" alias="grid_clb_9__2_"/>
|
||||
<key id="576" alias="cby_9__2_"/>
|
||||
<key id="577" alias="grid_clb_10__2_"/>
|
||||
<key id="578" alias="cby_10__2_"/>
|
||||
<key id="579" alias="grid_clb_11__2_"/>
|
||||
<key id="580" alias="cby_11__2_"/>
|
||||
<key id="581" alias="grid_clb_12__2_"/>
|
||||
<key id="582" alias="cby_12__2_"/>
|
||||
<key id="583" alias="grid_io_right_right_13__2_"/>
|
||||
<key id="584" alias="sb_12__1_"/>
|
||||
<key id="585" alias="cbx_12__1_"/>
|
||||
<key id="586" alias="sb_11__1_"/>
|
||||
<key id="587" alias="cbx_11__1_"/>
|
||||
<key id="588" alias="sb_10__1_"/>
|
||||
<key id="589" alias="cbx_10__1_"/>
|
||||
<key id="590" alias="sb_9__1_"/>
|
||||
<key id="591" alias="cbx_9__1_"/>
|
||||
<key id="592" alias="sb_8__1_"/>
|
||||
<key id="593" alias="cbx_8__1_"/>
|
||||
<key id="594" alias="sb_7__1_"/>
|
||||
<key id="595" alias="cbx_7__1_"/>
|
||||
<key id="596" alias="sb_6__1_"/>
|
||||
<key id="597" alias="cbx_6__1_"/>
|
||||
<key id="598" alias="sb_5__1_"/>
|
||||
<key id="599" alias="cbx_5__1_"/>
|
||||
<key id="600" alias="sb_4__1_"/>
|
||||
<key id="601" alias="cbx_4__1_"/>
|
||||
<key id="602" alias="sb_3__1_"/>
|
||||
<key id="603" alias="cbx_3__1_"/>
|
||||
<key id="604" alias="sb_2__1_"/>
|
||||
<key id="605" alias="cbx_2__1_"/>
|
||||
<key id="606" alias="sb_1__1_"/>
|
||||
<key id="607" alias="cbx_1__1_"/>
|
||||
<key id="608" alias="sb_0__1_"/>
|
||||
<key id="609" alias="cby_0__1_"/>
|
||||
<key id="610" alias="grid_io_left_left_0__1_"/>
|
||||
<key id="611" alias="grid_clb_1__1_"/>
|
||||
<key id="612" alias="cby_1__1_"/>
|
||||
<key id="613" alias="grid_clb_2__1_"/>
|
||||
<key id="614" alias="cby_2__1_"/>
|
||||
<key id="615" alias="grid_clb_3__1_"/>
|
||||
<key id="616" alias="cby_3__1_"/>
|
||||
<key id="617" alias="grid_clb_4__1_"/>
|
||||
<key id="618" alias="cby_4__1_"/>
|
||||
<key id="619" alias="grid_clb_5__1_"/>
|
||||
<key id="620" alias="cby_5__1_"/>
|
||||
<key id="621" alias="grid_clb_6__1_"/>
|
||||
<key id="622" alias="cby_6__1_"/>
|
||||
<key id="623" alias="grid_clb_7__1_"/>
|
||||
<key id="624" alias="cby_7__1_"/>
|
||||
<key id="625" alias="grid_clb_8__1_"/>
|
||||
<key id="626" alias="cby_8__1_"/>
|
||||
<key id="627" alias="grid_clb_9__1_"/>
|
||||
<key id="628" alias="cby_9__1_"/>
|
||||
<key id="629" alias="grid_clb_10__1_"/>
|
||||
<key id="630" alias="cby_10__1_"/>
|
||||
<key id="631" alias="grid_clb_11__1_"/>
|
||||
<key id="632" alias="cby_11__1_"/>
|
||||
<key id="633" alias="grid_clb_12__1_"/>
|
||||
<key id="634" alias="cby_12__1_"/>
|
||||
<key id="635" alias="grid_io_right_right_13__1_"/>
|
||||
<key id="636" alias="sb_12__0_"/>
|
||||
<key id="637" alias="cbx_12__0_"/>
|
||||
<key id="638" alias="grid_io_bottom_bottom_12__0_"/>
|
||||
<key id="639" alias="sb_11__0_"/>
|
||||
<key id="640" alias="cbx_11__0_"/>
|
||||
<key id="641" alias="grid_io_bottom_bottom_11__0_"/>
|
||||
<key id="642" alias="sb_10__0_"/>
|
||||
<key id="643" alias="cbx_10__0_"/>
|
||||
<key id="644" alias="grid_io_bottom_bottom_10__0_"/>
|
||||
<key id="645" alias="sb_9__0_"/>
|
||||
<key id="646" alias="cbx_9__0_"/>
|
||||
<key id="647" alias="grid_io_bottom_bottom_9__0_"/>
|
||||
<key id="648" alias="sb_8__0_"/>
|
||||
<key id="649" alias="cbx_8__0_"/>
|
||||
<key id="650" alias="grid_io_bottom_bottom_8__0_"/>
|
||||
<key id="651" alias="sb_7__0_"/>
|
||||
<key id="652" alias="cbx_7__0_"/>
|
||||
<key id="653" alias="grid_io_bottom_bottom_7__0_"/>
|
||||
<key id="654" alias="sb_6__0_"/>
|
||||
<key id="655" alias="cbx_6__0_"/>
|
||||
<key id="656" alias="grid_io_bottom_bottom_6__0_"/>
|
||||
<key id="657" alias="sb_5__0_"/>
|
||||
<key id="658" alias="cbx_5__0_"/>
|
||||
<key id="659" alias="grid_io_bottom_bottom_5__0_"/>
|
||||
<key id="660" alias="sb_4__0_"/>
|
||||
<key id="661" alias="cbx_4__0_"/>
|
||||
<key id="662" alias="grid_io_bottom_bottom_4__0_"/>
|
||||
<key id="663" alias="sb_3__0_"/>
|
||||
<key id="664" alias="cbx_3__0_"/>
|
||||
<key id="665" alias="grid_io_bottom_bottom_3__0_"/>
|
||||
<key id="666" alias="sb_2__0_"/>
|
||||
<key id="667" alias="cbx_2__0_"/>
|
||||
<key id="668" alias="grid_io_bottom_bottom_2__0_"/>
|
||||
<key id="669" alias="sb_1__0_"/>
|
||||
<key id="670" alias="cbx_1__0_"/>
|
||||
<key id="671" alias="grid_io_bottom_bottom_1__0_"/>
|
||||
<key id="672" alias="sb_0__0_"/>
|
||||
</region>
|
||||
</fabric_key>
|
||||
|
|
@ -0,0 +1,322 @@
|
|||
<!-- Architecture annotation for OpenFPGA framework
|
||||
This annotation supports the k4_frac_cc_sky130nm.xml
|
||||
- General purpose logic block
|
||||
- K = 4, N = 8, I = 24
|
||||
- Routing architecture
|
||||
- 10% L = 1, fc_in = 0.15, Fc_out = 0.10
|
||||
- 10% L = 2, fc_in = 0.15, Fc_out = 0.10
|
||||
- 80% L = 4, fc_in = 0.15, Fc_out = 0.10
|
||||
- DSP block:
|
||||
- Multi-mode multiplier which can operate in two modes
|
||||
- Mode A: 18-bit multiplier
|
||||
- Mode B: two independent 9-bit multipliers
|
||||
- Skywater 130nm PDK
|
||||
- circuit models are binded to the opensource skywater
|
||||
foundry high-density standard cell library
|
||||
-->
|
||||
<openfpga_architecture>
|
||||
<technology_library>
|
||||
<device_library>
|
||||
<device_model name="logic" type="transistor">
|
||||
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||
<design vdd="0.9" pn_ratio="2"/>
|
||||
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||
</device_model>
|
||||
<device_model name="io" type="transistor">
|
||||
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||
<design vdd="2.5" pn_ratio="3"/>
|
||||
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||
</device_model>
|
||||
</device_library>
|
||||
<variation_library>
|
||||
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||
</variation_library>
|
||||
</technology_library>
|
||||
<circuit_library>
|
||||
<circuit_model type="inv_buf" name="inv_01" prefix="inv_01" verilog_netlist="./inv/sky130_fd_sc_hd__inv_1.v">
|
||||
<design_technology type="cmos" topology="inverter" size="1"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="Y" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_1" prefix="sky130_fd_sc_hd__inv_1" is_default="true">
|
||||
<design_technology type="cmos" topology="inverter" size="1"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="Y" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="X" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_4" prefix="sky130_fd_sc_hd__buf_4" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="X" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="Y" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true">
|
||||
<design_technology type="cmos" topology="OR"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="a" lib_name="A" size="1"/>
|
||||
<port type="input" prefix="b" lib_name="B" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="X" size="1"/>
|
||||
<delay_matrix type="rise" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<!-- Define a circuit model for the standard cell MUX2
|
||||
OpenFPGA requires the following truth table for the MUX2
|
||||
When the select signal sel is enabled, the first input, i.e., in0
|
||||
will be propagated to the output, i.e., out
|
||||
If your standard cell provider does not offer the exact truth table,
|
||||
you can simply swap the inputs as shown in the example below
|
||||
-->
|
||||
<circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1">
|
||||
<design_technology type="cmos" topology="MUX2"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in0" lib_name="A1" size="1"/>
|
||||
<port type="input" prefix="in1" lib_name="A0" size="1"/>
|
||||
<port type="input" prefix="sel" lib_name="S" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="X" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
|
||||
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
|
||||
</circuit_model>
|
||||
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="0" C="0" num_level="1"/>
|
||||
<!-- model_type could be T, res_val cap_val should be defined -->
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
|
||||
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ff" name="CUSTOM_DATAFF" prefix="CUSTOM_DATAFF" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
|
||||
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="input" prefix="DI" lib_name="SI" size="1"/>
|
||||
<port type="input" prefix="Test_en" lib_name="SE" size="1" is_global="true" default_val="0"/>
|
||||
<port type="input" prefix="R" size="1" default_val="0"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="clock" prefix="C" lib_name="CK" size="1" default_val="0" />
|
||||
<port type="sram" prefix="mode" lib_name="MODE" size="1" mode_select="true" circuit_model_name="CUSTOM_CCFF" default_val="0"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="lut" name="frac_lut4_arith" prefix="frac_lut4_arith" dump_structural_verilog="true" verilog_netlist="frac_lut4_arith.v">
|
||||
<design_technology type="cmos" fracturable_lut="true"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
|
||||
<lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
|
||||
<lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
|
||||
<lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
|
||||
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
|
||||
<port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hd__or2_1"/>
|
||||
<port type="input" prefix="cin" size="1" is_harden_lut_port="true"/>
|
||||
<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
|
||||
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
|
||||
<port type="output" prefix="cout" size="1" is_harden_lut_port="true"/>
|
||||
<port type="sram" prefix="sram" size="16"/>
|
||||
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="CUSTOM_CCFF" default_val="1"/>
|
||||
</circuit_model>
|
||||
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ccff" name="CUSTOM_CCFF" prefix="CUSTOM_CCFF" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
|
||||
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="input" prefix="scan_data_in" lib_name="SCD" size="1"/>
|
||||
<!-- This port allows readback configurable memories without modifying the storage -->
|
||||
<port type="input" prefix="config_readback" lib_name="SCE" size="1" is_global="true" default_val="0"/>
|
||||
<!-- This port allows programming circuitry is be isolated from datapath logic during programming -->
|
||||
<port type="input" prefix="config_enable" lib_name="CFGE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||
<port type="input" prefix="pReset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_prog="true" is_reset="true"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="iopad" name="EMBEDDED_IO_ISOLN" prefix="EMBEDDED_IO_ISOLN" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
|
||||
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
|
||||
<port type="input" prefix="SOC_IN" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
|
||||
<port type="output" prefix="SOC_OUT" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
|
||||
<port type="output" prefix="SOC_DIR" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
|
||||
<port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
|
||||
<port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
|
||||
<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
|
||||
<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="CUSTOM_CCFF" default_val="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="hard_logic" name="CARRY_MUX2" prefix="CARRY_MUX2" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/mux2.v">
|
||||
<design_technology type="cmos"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="a" lib_name="A0" size="1"/>
|
||||
<port type="input" prefix="b" lib_name="A1" size="1"/>
|
||||
<port type="input" prefix="cin" lib_name="S" size="1"/>
|
||||
<port type="output" prefix="cout" lib_name="Y" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="hard_logic" name="frac_mult_18x18" prefix="frac_mult_18x18" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/frac_mult_18x18.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/frac_mult_18x18.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="A" lib_name="A" size="18"/>
|
||||
<port type="input" prefix="B" lib_name="B" size="18"/>
|
||||
<port type="output" prefix="Y" lib_name="Y" size="36"/>
|
||||
<port type="sram" prefix="mode" lib_name="MODE" size="1" mode_select="true" circuit_model_name="CUSTOM_CCFF" default_val="1"/>
|
||||
</circuit_model>
|
||||
</circuit_library>
|
||||
<configuration_protocol>
|
||||
<organization type="scan_chain" circuit_model_name="CUSTOM_CCFF" num_regions="1"/>
|
||||
</configuration_protocol>
|
||||
<connection_block>
|
||||
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
|
||||
</connection_block>
|
||||
<switch_block>
|
||||
<switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
|
||||
<switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
|
||||
<switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
|
||||
</switch_block>
|
||||
<routing_segment>
|
||||
<segment name="L1" circuit_model_name="chan_segment"/>
|
||||
<segment name="L2" circuit_model_name="chan_segment"/>
|
||||
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||
</routing_segment>
|
||||
<direct_connection>
|
||||
<direct name="carry_chain" circuit_model_name="direct_interc"/>
|
||||
<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
|
||||
</direct_connection>
|
||||
<tile_annotations>
|
||||
<global_port name="clk" is_clock="true" default_val="0">
|
||||
<tile name="clb" port="clk" x="-1" y="-1"/>
|
||||
</global_port>
|
||||
<global_port name="Reset" is_reset="true" default_val="1">
|
||||
<tile name="clb" port="reset" x="-1" y="-1"/>
|
||||
</global_port>
|
||||
</tile_annotations>
|
||||
<pb_type_annotations>
|
||||
<!-- physical pb_type binding in complex block IO -->
|
||||
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||
<!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
|
||||
<pb_type name="io[physical].iopad" circuit_model_name="EMBEDDED_IO_ISOLN" mode_bits="1"/>
|
||||
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
|
||||
<!-- physical pb_type binding in complex block CLB -->
|
||||
<!-- physical mode will be the default mode if not specified -->
|
||||
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
||||
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" circuit_model_name="frac_lut4_arith" mode_bits="00"/>
|
||||
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="CUSTOM_DATAFF" mode_bits="0"/>
|
||||
<!-- Binding operating pb_type to physical pb_type -->
|
||||
<!-- Binding operating pb_types in mode 'arithmetic' -->
|
||||
<pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" mode_bits="11"/>
|
||||
<!-- Binding operating pb_types in mode 'n2_lut3' -->
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" mode_bits="01" physical_pb_type_index_factor="0.5">
|
||||
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
|
||||
<port name="in" physical_mode_port="in[0:2]"/>
|
||||
<port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0">
|
||||
<port name="clk" physical_mode_port="C"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1">
|
||||
<port name="RN" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<!-- Binding operating pb_types in mode 'ble4' -->
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" mode_bits="00">
|
||||
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
|
||||
<port name="in" physical_mode_port="in[0:3]"/>
|
||||
<port name="out" physical_mode_port="lut4_out"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
|
||||
<port name="clk" physical_mode_port="C"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
|
||||
<port name="RN" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<!-- End physical pb_type binding in complex block CLB -->
|
||||
|
||||
<!-- physical pb_type binding in complex block dsp -->
|
||||
<pb_type name="mult_18" physical_mode_name="mult_18x18"/>
|
||||
<!-- Bind the primitive pb_type in the physical mode to a circuit model -->
|
||||
<pb_type name="mult_18[mult_18x18].mult_18x18_slice.mult_18x18" circuit_model_name="frac_mult_18x18" mode_bits="0"/>
|
||||
<pb_type name="mult_18[mult_9x9].mult_9x9_slice.mult_9x9" physical_pb_type_name="mult_18[mult_18x18].mult_18x18_slice.mult_18x18" mode_bits="1" physical_pb_type_index_factor="0">
|
||||
<port name="A" physical_mode_port="A[0:8]" physical_mode_port_rotate_offset="9"/>
|
||||
<port name="B" physical_mode_port="B[0:8]" physical_mode_port_rotate_offset="9"/>
|
||||
<port name="Y" physical_mode_port="Y[0:17]" physical_mode_port_rotate_offset="18"/>
|
||||
</pb_type>
|
||||
</pb_type_annotations>
|
||||
</openfpga_architecture>
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,54 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = true
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 1*60
|
||||
fpga_flow=yosys_vpr
|
||||
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
|
||||
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga
|
||||
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
|
||||
openfpga_vpr_device_layout=12x12
|
||||
openfpga_vpr_route_chan_width=60
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:TASK_DIR}/BENCHMARK/and2/and2.v
|
||||
bench1=${PATH:TASK_DIR}/BENCHMARK/and2_latch/and2_latch.v
|
||||
bench2=${PATH:TASK_DIR}/BENCHMARK/bin2bcd/bin2bcd.v
|
||||
bench3=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
|
||||
bench4=${PATH:TASK_DIR}/BENCHMARK/routing_test/routing_test.v
|
||||
# RS decoder needs 1.5k LUT4, exceeding device capacity
|
||||
#bench5=${PATH:TASK_DIR}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
|
||||
bench6=${PATH:TASK_DIR}/BENCHMARK/simon_bit_serial/rtl/*.v
|
||||
bench7=${PATH:TASK_DIR}/BENCHMARK/and2_or2/and2_or2.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench0_top = and2
|
||||
bench1_top = and2_latch
|
||||
bench2_top = bin2bcd
|
||||
bench3_top = counter
|
||||
bench4_top = routing_test
|
||||
# RS decoder needs 1.5k LUT4, exceeding device capacity
|
||||
#bench5_top = rs_decoder_top
|
||||
bench6_top = top_module
|
||||
bench7_top = and2_or2
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
#end_flow_with_test=
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_analysis = false
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 20*60
|
||||
fpga_flow=vpr_blif
|
||||
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
|
||||
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
|
||||
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
|
||||
openfpga_vpr_device_layout=12x12
|
||||
openfpga_vpr_route_chan_width=60
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench0_top = top
|
||||
bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
|
||||
bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
vpr_fpga_verilog_formal_verification_top_netlist=
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = true
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 1*60
|
||||
fpga_flow=yosys_vpr
|
||||
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga
|
||||
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
|
||||
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
|
||||
openfpga_vpr_device_layout=12x12
|
||||
openfpga_vpr_route_chan_width=60
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench0_top = counter
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
#end_flow_with_test=
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
L1_SB_MUX_DELAY: 1.44e-9
|
||||
L2_SB_MUX_DELAY: 1.44e-9
|
||||
L4_SB_MUX_DELAY: 1.44e-9
|
||||
CB_MUX_DELAY: 1.38e-9
|
||||
L1_WIRE_R: 100
|
||||
L1_WIRE_C: 1e-12
|
||||
L2_WIRE_R: 100
|
||||
L2_WIRE_C: 1e-12
|
||||
L4_WIRE_R: 100
|
||||
L4_WIRE_C: 1e-12
|
||||
INPAD_DELAY: 0.11e-9
|
||||
OUTPAD_DELAY: 0.11e-9
|
||||
FF_T_SETUP: 0.39e-9
|
||||
FF_T_CLK2Q: 0.43e-9
|
||||
LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
|
||||
LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
|
||||
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
|
||||
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
|
||||
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
|
||||
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
|
||||
LUT_CIN2LUT3_OUT_DELAY: 1.21e-9
|
||||
LUT_CIN2LUT4_OUT_DELAY: 1.21e-9
|
||||
LUT_CIN2COUT_DELAY: 1.21e-9
|
||||
LUT_IN2COUT_DELAY: 1.21e-9
|
||||
LUT3_DELAY: 0.92e-9
|
||||
LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
|
||||
LUT4_DELAY: 1.21e-9
|
||||
LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
|
||||
ADDER_LUT4_CIN2OUT_DELAY: 1.21e-9
|
||||
ADDER_LUT4_CIN2COUT_DELAY: 1.21e-9
|
||||
ADDER_LUT4_IN2OUT_DELAY: 1.21e-9
|
||||
ADDER_LUT4_IN2COUT_DELAY: 1.21e-9
|
||||
MULT9_A2Y_DELAY_MAX: 1.523e-9
|
||||
MULT9_A2Y_DELAY_MIN: 0.776e-9
|
||||
MULT9_B2Y_DELAY_MAX: 1.523e-9
|
||||
MULT9_B2Y_DELAY_MIN: 0.776e-9
|
||||
MULT18_A2Y_DELAY_MAX: 1.523e-9
|
||||
MULT18_A2Y_DELAY_MIN: 0.776e-9
|
||||
MULT18_B2Y_DELAY_MAX: 1.523e-9
|
||||
MULT18_B2Y_DELAY_MIN: 0.776e-9
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
# This script is designed to generate fabric Verilog netlists
|
||||
# with a fixed device layout
|
||||
# It will only output netlists to be used by backend tools,
|
||||
# i.e., Synopsys ICC2, including
|
||||
# - Verilog netlists
|
||||
# - fabric hierarchy description for ICC2's hierarchical flow
|
||||
# - Timing/Design constraints
|
||||
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --constant_net_method route --absorb_buffer_luts off --clock_modeling ideal
|
||||
|
||||
# Read OpenFPGA architecture definition
|
||||
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
|
||||
|
||||
# Read OpenFPGA simulation settings
|
||||
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
|
||||
|
||||
# Annotate the OpenFPGA architecture to VPR data base
|
||||
# to debug use --verbose options
|
||||
link_openfpga_arch --sort_gsb_chan_node_in_edges
|
||||
|
||||
# Check and correct any naming conflicts in the BLIF netlist
|
||||
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
|
||||
|
||||
# Apply fix-up to clustering nets based on routing results
|
||||
pb_pin_fixup --verbose
|
||||
|
||||
# Apply fix-up to Look-Up Table truth tables based on packing results
|
||||
lut_truth_table_fixup
|
||||
|
||||
# Build the module graph
|
||||
# - Enabled compression on routing architecture modules
|
||||
# - Enable pin duplication on grid modules
|
||||
build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE}
|
||||
|
||||
# Repack the netlist to physical pbs
|
||||
# This must be done before bitstream generator and testbench generation
|
||||
# Strongly recommend it is done after all the fix-up have been applied
|
||||
repack
|
||||
|
||||
build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml
|
||||
|
||||
build_fabric_bitstream
|
||||
write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
|
||||
write_fabric_bitstream --format xml --file fabric_bitstream.xml
|
||||
|
||||
# Write the Verilog netlist for FPGA fabric
|
||||
# - Enable the use of explicit port mapping in Verilog netlist
|
||||
write_fabric_verilog \
|
||||
--file ./SRC \
|
||||
--explicit_port_mapping \
|
||||
--include_timing \
|
||||
--verbose
|
||||
|
||||
write_verilog_testbench \
|
||||
--file ./SRC \
|
||||
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
|
||||
--print_top_testbench \
|
||||
--print_preconfig_top_testbench \
|
||||
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
|
||||
--explicit_port_mapping
|
||||
|
||||
# Write the SDC files for PnR backend
|
||||
# - Turn on every options here
|
||||
write_pnr_sdc --file ./SDC
|
||||
|
||||
# Write SDC to disable timing for configure ports
|
||||
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
|
||||
|
||||
# Write the SDC to run timing analysis for a mapped FPGA fabric
|
||||
write_analysis_sdc --file ./SDC_analysis
|
||||
|
||||
# Finish and exit OpenFPGA
|
||||
exit
|
||||
|
||||
# Note :
|
||||
# To run verification at the end of the flow maintain source in ./SRC directory
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
# This script is designed to generate fabric Verilog netlists
|
||||
# with a fixed device layout
|
||||
# It will only output netlists to be used by backend tools,
|
||||
# i.e., Synopsys ICC2, including
|
||||
# - Verilog netlists
|
||||
# - fabric hierarchy description for ICC2's hierarchical flow
|
||||
# - Timing/Design constraints
|
||||
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --constant_net_method route --absorb_buffer_luts off --clock_modeling ideal
|
||||
|
||||
# Read OpenFPGA architecture definition
|
||||
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
|
||||
|
||||
# Read OpenFPGA simulation settings
|
||||
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
|
||||
|
||||
# Annotate the OpenFPGA architecture to VPR data base
|
||||
# to debug use --verbose options
|
||||
link_openfpga_arch --sort_gsb_chan_node_in_edges
|
||||
|
||||
# Check and correct any naming conflicts in the BLIF netlist
|
||||
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
|
||||
|
||||
# Apply fix-up to clustering nets based on routing results
|
||||
pb_pin_fixup --verbose
|
||||
|
||||
# Apply fix-up to Look-Up Table truth tables based on packing results
|
||||
lut_truth_table_fixup
|
||||
|
||||
# Build the module graph
|
||||
# - Enabled compression on routing architecture modules
|
||||
# - Enable pin duplication on grid modules
|
||||
build_fabric --compress_routing --duplicate_grid_pin
|
||||
# --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE}
|
||||
|
||||
# Repack the netlist to physical pbs
|
||||
# This must be done before bitstream generator and testbench generation
|
||||
# Strongly recommend it is done after all the fix-up have been applied
|
||||
repack
|
||||
|
||||
build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml
|
||||
|
||||
build_fabric_bitstream
|
||||
write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
|
||||
write_fabric_bitstream --format xml --file fabric_bitstream.xml
|
||||
|
||||
write_full_testbench --file ./SRC \
|
||||
--bitstream fabric_bitstream.bit
|
||||
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
|
||||
--explicit_port_mapping
|
||||
|
||||
# Finish and exit OpenFPGA
|
||||
exit
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
a 0.5 0.5
|
||||
b 0.5 0.5
|
||||
c 0.25 0.25
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
.model top
|
||||
.inputs a b
|
||||
.outputs c
|
||||
|
||||
.names a b c
|
||||
11 1
|
||||
|
||||
.end
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
`timescale 1ns / 1ps
|
||||
|
||||
module top(
|
||||
a,
|
||||
b,
|
||||
c);
|
||||
|
||||
input wire a;
|
||||
input wire b;
|
||||
output wire c;
|
||||
|
||||
assign c = a & b;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
#!/bin/bash
|
||||
cp user_project_wrapper_template.def user_project_wrapper_empty.def
|
||||
|
||||
sed -i '/^SPECIALNETS/,/END SPECIALNETS/d' user_project_wrapper_empty.def
|
||||
sed -i '/^VIAS/,/END VIAS/d' user_project_wrapper_empty.def
|
||||
sed -i '/^ROW ROW/d' user_project_wrapper_empty.def
|
||||
sed -i '/^TRACKS/d' user_project_wrapper_empty.def
|
||||
sed -i 's/user_project_wrapper/fpga_top/' user_project_wrapper_empty.def
|
||||
|
||||
VDD_LINES=$(grep "\- vdda\|vccd" user_project_wrapper_empty.def)
|
||||
VSS_LINES=$(grep "\- vssa\|vssd" user_project_wrapper_empty.def)
|
||||
|
||||
sed -i '/^ - v.*$/d' user_project_wrapper_empty.def
|
||||
|
||||
X="2920000"
|
||||
Y="3520000"
|
||||
|
||||
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/\-.*\(FIXED.*\) ;/+ PORT + \1/g")
|
||||
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/^.*met.*[0-9]\{6,\}.*//")
|
||||
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/\(.*met5\).*) ( \([0-9]*\) \([0-9]*\) )/\1 ( -5000 -\3 ) ( 5000 \3 )/g")
|
||||
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/\(.*met4\).*) ( \([0-9]*\) \([0-9]*\) )/\1 ( -\2 -5000 ) ( \2 5000 )/g")
|
||||
|
||||
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/FIXED ( \([0-9]*\) \([0-9]*\)\(.*met5\)/FIXED ( 2920000 \2 \3/g")
|
||||
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/FIXED ( \(-[0-9]*\) \([0-9]*\)\(.*met5\)/FIXED ( 0 \2 \3/g")
|
||||
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/FIXED ( \([0-9]*\) \([0-9]*\) )\(.*met4\)/FIXED ( \1 3520000 ) \3/g")
|
||||
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/FIXED ( \([0-9]*\) \(-[0-9]*\) )\(.*met4\)/FIXED ( \1 0 ) \3/g")
|
||||
|
||||
|
||||
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/\-.*\(FIXED.*\) ;/+ PORT + \1/g")
|
||||
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/^.*met.*[0-9]\{6,\}.*//")
|
||||
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/\(.*met5\).*) ( \([0-9]*\) \([0-9]*\) )/\1 ( -5000 -\3 ) ( 5000 \3 )/g")
|
||||
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/\(.*met4\).*) ( \([0-9]*\) \([0-9]*\) )/\1 ( -\2 -5000 ) ( \2 5000 )/g")
|
||||
|
||||
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/FIXED ( \([0-9]*\) \([0-9]*\)\(.*met5\)/FIXED ( 2920000 \2 \3/g")
|
||||
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/FIXED ( \(-[0-9]*\) \([0-9]*\)\(.*met5\)/FIXED ( 0 \2 \3/g")
|
||||
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/FIXED ( \([0-9]*\) \([0-9]*\) )\(.*met4\)/FIXED ( \1 3520000 ) \3/g")
|
||||
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/FIXED ( \([0-9]*\) \(-[0-9]*\) )\(.*met4\)/FIXED ( \1 0 ) \3/g")
|
||||
|
||||
sed -i '/END PINS/d' user_project_wrapper_empty.def
|
||||
sed -i '/END DESIGN/d' user_project_wrapper_empty.def
|
||||
echo " - VDD + NET VDD + SPECIAL + DIRECTION INPUT + USE POWER" >> user_project_wrapper_empty.def
|
||||
printf "${VDD_LINES} ;\n" >> user_project_wrapper_empty.def
|
||||
echo "- VSS + NET VSS + SPECIAL + DIRECTION INPUT + USE GROUND" >> user_project_wrapper_empty.def
|
||||
printf "${VSS_LINES} ;\n" >> user_project_wrapper_empty.def
|
||||
echo "END PINS" >> user_project_wrapper_empty.def
|
||||
echo "END DESIGN" >> user_project_wrapper_empty.def
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
`timescale 1ns/1ps
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
module EMBEDDED_IO_HD (
|
||||
input SOC_IN, //
|
||||
output SOC_OUT, //
|
||||
output SOC_DIR, //
|
||||
output FPGA_IN, //
|
||||
input FPGA_OUT, //
|
||||
input FPGA_DIR, //
|
||||
input IO_ISOL_N //
|
||||
);
|
||||
|
||||
wire SOC_DIR_N;
|
||||
|
||||
//
|
||||
sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE (.B_N(IO_ISOL_N),
|
||||
.A(FPGA_DIR),
|
||||
.X(SOC_DIR)
|
||||
);
|
||||
|
||||
//
|
||||
sky130_fd_sc_hd__inv_1 INV_SOC_DIR (.A(SOC_DIR), .Y(SOC_DIR_N));
|
||||
sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE (.TE_B(SOC_DIR_N),
|
||||
.A(SOC_IN),
|
||||
.Z(FPGA_IN)
|
||||
);
|
||||
|
||||
//
|
||||
sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE (.TE_B(SOC_DIR),
|
||||
.A(FPGA_OUT),
|
||||
.Z(SOC_OUT)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,483 @@
|
|||
/*
|
||||
*-------------------------------------------------------------
|
||||
*
|
||||
* A wrapper for the FPGA IP to fit the I/O interface of Caravel SoC
|
||||
*
|
||||
* The wrapper is a technology mapped netlist where the mode-switch
|
||||
* multiplexers are mapped to the Skywater 130nm
|
||||
* High-Density (HD) standard cells
|
||||
*
|
||||
*-------------------------------------------------------------
|
||||
*/
|
||||
|
||||
module fpga_top (
|
||||
//
|
||||
//
|
||||
inout vdda1, //
|
||||
inout vdda2, //
|
||||
inout vssa1, //
|
||||
inout vssa2, //
|
||||
inout vccd1, //
|
||||
inout vccd2, //
|
||||
inout vssd1, //
|
||||
inout vssd2, //
|
||||
|
||||
//
|
||||
input wb_clk_i,
|
||||
input wb_rst_i,
|
||||
input wbs_stb_i,
|
||||
input wbs_cyc_i,
|
||||
input wbs_we_i,
|
||||
input [3:0] wbs_sel_i,
|
||||
input [31:0] wbs_dat_i,
|
||||
input [31:0] wbs_adr_i,
|
||||
output wbs_ack_o,
|
||||
output [31:0] wbs_dat_o,
|
||||
|
||||
//
|
||||
input [127:0] la_data_in,
|
||||
output [127:0] la_data_out,
|
||||
input [127:0] la_oen,
|
||||
|
||||
//
|
||||
input [37:0] io_in,
|
||||
output [37:0] io_out,
|
||||
output [37:0] io_oeb
|
||||
);
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
//
|
||||
wire prog_clk;
|
||||
wire Test_en;
|
||||
wire IO_ISOL_N;
|
||||
wire clk;
|
||||
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
|
||||
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
|
||||
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
|
||||
wire ccff_head;
|
||||
wire ccff_tail;
|
||||
wire sc_head;
|
||||
wire sc_tail;
|
||||
wire pReset;
|
||||
wire Reset;
|
||||
|
||||
//
|
||||
wire wb_la_switch;
|
||||
wire wb_la_switch_b;
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV (.A(wb_la_switch), .Y(wb_la_switch_b));
|
||||
|
||||
//
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24];
|
||||
assign io_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0];
|
||||
assign io_oeb[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = io_in[23];
|
||||
assign io_out[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1];
|
||||
assign io_oeb[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = io_in[22];
|
||||
assign io_out[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2];
|
||||
assign io_oeb[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = io_in[21];
|
||||
assign io_out[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3];
|
||||
assign io_oeb[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = io_in[20];
|
||||
assign io_out[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4];
|
||||
assign io_oeb[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = io_in[19];
|
||||
assign io_out[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5];
|
||||
assign io_oeb[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = io_in[18];
|
||||
assign io_out[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6];
|
||||
assign io_oeb[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = io_in[17];
|
||||
assign io_out[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7];
|
||||
assign io_oeb[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = io_in[16];
|
||||
assign io_out[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8];
|
||||
assign io_oeb[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = io_in[15];
|
||||
assign io_out[15] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9];
|
||||
assign io_oeb[15] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = io_in[14];
|
||||
assign io_out[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10];
|
||||
assign io_oeb[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = io_in[13];
|
||||
assign io_out[13] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11];
|
||||
assign io_oeb[13] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11];
|
||||
assign ccff_head = io_in[12];
|
||||
assign io_out[12] = 1'b0;
|
||||
assign io_oeb[12] = 1'b1;
|
||||
assign io_out[11] = sc_tail;
|
||||
assign io_oeb[11] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = io_in[10];
|
||||
assign io_out[10] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12];
|
||||
assign io_oeb[10] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = io_in[9];
|
||||
assign io_out[9] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13];
|
||||
assign io_oeb[9] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = io_in[8];
|
||||
assign io_out[8] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14];
|
||||
assign io_oeb[8] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = io_in[7];
|
||||
assign io_out[7] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15];
|
||||
assign io_oeb[7] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = io_in[6];
|
||||
assign io_out[6] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16];
|
||||
assign io_oeb[6] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = io_in[5];
|
||||
assign io_out[5] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17];
|
||||
assign io_oeb[5] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = io_in[4];
|
||||
assign io_out[4] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18];
|
||||
assign io_oeb[4] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18];
|
||||
assign pReset = io_in[3];
|
||||
assign io_out[3] = 1'b0;
|
||||
assign io_oeb[3] = 1'b1;
|
||||
assign Reset = io_in[2];
|
||||
assign io_out[2] = 1'b0;
|
||||
assign io_oeb[2] = 1'b1;
|
||||
assign IO_ISOL_N = io_in[1];
|
||||
assign io_out[1] = 1'b0;
|
||||
assign io_oeb[1] = 1'b1;
|
||||
assign Test_en = io_in[0];
|
||||
assign io_out[0] = 1'b0;
|
||||
assign io_oeb[0] = 1'b1;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = la_data_in[127];
|
||||
assign la_data_out[127] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = la_data_in[126];
|
||||
assign la_data_out[126] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[125];
|
||||
assign la_data_out[125] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[124];
|
||||
assign la_data_out[124] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[123];
|
||||
assign la_data_out[123] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[122];
|
||||
assign la_data_out[122] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[121];
|
||||
assign la_data_out[121] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[120];
|
||||
assign la_data_out[120] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[119];
|
||||
assign la_data_out[119] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[118];
|
||||
assign la_data_out[118] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[117];
|
||||
assign la_data_out[117] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[116];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(wbs_dat_o[0]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(la_data_out[116]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[115];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(wbs_dat_o[1]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(la_data_out[115]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[114];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(wbs_dat_o[2]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(la_data_out[114]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[113];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(wbs_dat_o[3]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(la_data_out[113]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[112];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(wbs_dat_o[4]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(la_data_out[112]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[111];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(wbs_dat_o[5]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(la_data_out[111]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[110];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(wbs_dat_o[6]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(la_data_out[110]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[109];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(wbs_dat_o[7]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(la_data_out[109]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[108];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(wbs_dat_o[8]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(la_data_out[108]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[107];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(wbs_dat_o[9]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(la_data_out[107]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[106];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(wbs_dat_o[10]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(la_data_out[106]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[105];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(wbs_dat_o[11]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(la_data_out[105]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[104];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(wbs_dat_o[12]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(la_data_out[104]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[103];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(wbs_dat_o[13]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(la_data_out[103]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[102];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(wbs_dat_o[14]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(la_data_out[102]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[101];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(wbs_dat_o[15]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(la_data_out[101]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[100];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(wbs_dat_o[16]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(la_data_out[100]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[99];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(wbs_dat_o[17]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(la_data_out[99]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[98];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(wbs_dat_o[18]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(la_data_out[98]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[97];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(wbs_dat_o[19]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(la_data_out[97]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[96];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(wbs_dat_o[20]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(la_data_out[96]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[95];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(wbs_dat_o[21]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(la_data_out[95]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[94];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(wbs_dat_o[22]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(la_data_out[94]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[93];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(wbs_dat_o[23]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(la_data_out[93]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[92];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(wbs_dat_o[24]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(la_data_out[92]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[91];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(wbs_dat_o[25]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(la_data_out[91]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[90];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(wbs_dat_o[26]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(la_data_out[90]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[89];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(wbs_dat_o[27]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(la_data_out[89]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[88];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(wbs_dat_o[28]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(la_data_out[88]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[87];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(wbs_dat_o[29]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(la_data_out[87]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[86];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(wbs_dat_o[30]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(la_data_out[86]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[85];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(wbs_dat_o[31]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(la_data_out[85]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX (.S(wb_la_switch), .A1(wbs_dat_i[0]), .A0(la_data_in[84]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62]));
|
||||
assign la_data_out[84] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX (.S(wb_la_switch), .A1(wbs_dat_i[1]), .A0(la_data_in[83]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63]));
|
||||
assign la_data_out[83] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX (.S(wb_la_switch), .A1(wbs_dat_i[2]), .A0(la_data_in[82]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64]));
|
||||
assign la_data_out[82] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX (.S(wb_la_switch), .A1(wbs_dat_i[3]), .A0(la_data_in[81]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65]));
|
||||
assign la_data_out[81] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX (.S(wb_la_switch), .A1(wbs_dat_i[4]), .A0(la_data_in[80]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66]));
|
||||
assign la_data_out[80] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX (.S(wb_la_switch), .A1(wbs_dat_i[5]), .A0(la_data_in[79]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67]));
|
||||
assign la_data_out[79] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX (.S(wb_la_switch), .A1(wbs_dat_i[6]), .A0(la_data_in[78]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68]));
|
||||
assign la_data_out[78] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX (.S(wb_la_switch), .A1(wbs_dat_i[7]), .A0(la_data_in[77]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69]));
|
||||
assign la_data_out[77] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX (.S(wb_la_switch), .A1(wbs_dat_i[8]), .A0(la_data_in[76]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70]));
|
||||
assign la_data_out[76] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX (.S(wb_la_switch), .A1(wbs_dat_i[9]), .A0(la_data_in[75]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71]));
|
||||
assign la_data_out[75] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX (.S(wb_la_switch), .A1(wbs_dat_i[10]), .A0(la_data_in[74]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72]));
|
||||
assign la_data_out[74] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX (.S(wb_la_switch), .A1(wbs_dat_i[11]), .A0(la_data_in[73]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73]));
|
||||
assign la_data_out[73] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX (.S(wb_la_switch), .A1(wbs_dat_i[12]), .A0(la_data_in[72]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74]));
|
||||
assign la_data_out[72] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX (.S(wb_la_switch), .A1(wbs_dat_i[13]), .A0(la_data_in[71]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75]));
|
||||
assign la_data_out[71] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX (.S(wb_la_switch), .A1(wbs_dat_i[14]), .A0(la_data_in[70]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76]));
|
||||
assign la_data_out[70] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX (.S(wb_la_switch), .A1(wbs_dat_i[15]), .A0(la_data_in[69]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77]));
|
||||
assign la_data_out[69] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX (.S(wb_la_switch), .A1(wbs_dat_i[16]), .A0(la_data_in[68]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78]));
|
||||
assign la_data_out[68] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX (.S(wb_la_switch), .A1(wbs_dat_i[17]), .A0(la_data_in[67]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79]));
|
||||
assign la_data_out[67] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX (.S(wb_la_switch), .A1(wbs_dat_i[18]), .A0(la_data_in[66]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80]));
|
||||
assign la_data_out[66] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX (.S(wb_la_switch), .A1(wbs_dat_i[19]), .A0(la_data_in[65]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81]));
|
||||
assign la_data_out[65] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX (.S(wb_la_switch), .A1(wbs_dat_i[20]), .A0(la_data_in[64]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82]));
|
||||
assign la_data_out[64] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX (.S(wb_la_switch), .A1(wbs_dat_i[21]), .A0(la_data_in[63]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83]));
|
||||
assign la_data_out[63] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX (.S(wb_la_switch), .A1(wbs_dat_i[22]), .A0(la_data_in[62]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84]));
|
||||
assign la_data_out[62] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX (.S(wb_la_switch), .A1(wbs_dat_i[23]), .A0(la_data_in[61]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85]));
|
||||
assign la_data_out[61] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX (.S(wb_la_switch), .A1(wbs_dat_i[24]), .A0(la_data_in[60]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86]));
|
||||
assign la_data_out[60] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX (.S(wb_la_switch), .A1(wbs_dat_i[25]), .A0(la_data_in[59]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87]));
|
||||
assign la_data_out[59] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX (.S(wb_la_switch), .A1(wbs_dat_i[26]), .A0(la_data_in[58]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88]));
|
||||
assign la_data_out[58] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX (.S(wb_la_switch), .A1(wbs_dat_i[27]), .A0(la_data_in[57]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89]));
|
||||
assign la_data_out[57] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX (.S(wb_la_switch), .A1(wbs_dat_i[28]), .A0(la_data_in[56]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90]));
|
||||
assign la_data_out[56] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX (.S(wb_la_switch), .A1(wbs_dat_i[29]), .A0(la_data_in[55]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91]));
|
||||
assign la_data_out[55] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX (.S(wb_la_switch), .A1(wbs_dat_i[30]), .A0(la_data_in[54]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92]));
|
||||
assign la_data_out[54] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX (.S(wb_la_switch), .A1(wbs_dat_i[31]), .A0(la_data_in[53]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93]));
|
||||
assign la_data_out[53] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX (.S(wb_la_switch), .A1(wbs_adr_i[0]), .A0(la_data_in[52]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94]));
|
||||
assign la_data_out[52] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX (.S(wb_la_switch), .A1(wbs_adr_i[1]), .A0(la_data_in[51]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95]));
|
||||
assign la_data_out[51] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX (.S(wb_la_switch), .A1(wbs_adr_i[2]), .A0(la_data_in[50]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96]));
|
||||
assign la_data_out[50] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX (.S(wb_la_switch), .A1(wbs_adr_i[3]), .A0(la_data_in[49]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97]));
|
||||
assign la_data_out[49] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX (.S(wb_la_switch), .A1(wbs_adr_i[4]), .A0(la_data_in[48]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98]));
|
||||
assign la_data_out[48] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX (.S(wb_la_switch), .A1(wbs_adr_i[5]), .A0(la_data_in[47]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99]));
|
||||
assign la_data_out[47] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX (.S(wb_la_switch), .A1(wbs_adr_i[6]), .A0(la_data_in[46]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100]));
|
||||
assign la_data_out[46] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX (.S(wb_la_switch), .A1(wbs_adr_i[7]), .A0(la_data_in[45]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101]));
|
||||
assign la_data_out[45] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX (.S(wb_la_switch), .A1(wbs_adr_i[8]), .A0(la_data_in[44]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102]));
|
||||
assign la_data_out[44] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX (.S(wb_la_switch), .A1(wbs_adr_i[9]), .A0(la_data_in[43]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103]));
|
||||
assign la_data_out[43] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX (.S(wb_la_switch), .A1(wbs_adr_i[10]), .A0(la_data_in[42]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104]));
|
||||
assign la_data_out[42] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX (.S(wb_la_switch), .A1(wbs_adr_i[11]), .A0(la_data_in[41]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105]));
|
||||
assign la_data_out[41] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX (.S(wb_la_switch), .A1(wbs_adr_i[12]), .A0(la_data_in[40]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106]));
|
||||
assign la_data_out[40] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX (.S(wb_la_switch), .A1(wbs_adr_i[13]), .A0(la_data_in[39]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107]));
|
||||
assign la_data_out[39] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX (.S(wb_la_switch), .A1(wbs_adr_i[14]), .A0(la_data_in[38]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108]));
|
||||
assign la_data_out[38] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX (.S(wb_la_switch), .A1(wbs_adr_i[15]), .A0(la_data_in[37]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109]));
|
||||
assign la_data_out[37] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX (.S(wb_la_switch), .A1(wbs_adr_i[16]), .A0(la_data_in[36]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110]));
|
||||
assign la_data_out[36] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX (.S(wb_la_switch), .A1(wbs_adr_i[17]), .A0(la_data_in[35]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111]));
|
||||
assign la_data_out[35] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX (.S(wb_la_switch), .A1(wbs_adr_i[18]), .A0(la_data_in[34]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112]));
|
||||
assign la_data_out[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX (.S(wb_la_switch), .A1(wbs_adr_i[19]), .A0(la_data_in[33]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113]));
|
||||
assign la_data_out[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX (.S(wb_la_switch), .A1(wbs_adr_i[20]), .A0(la_data_in[32]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114]));
|
||||
assign la_data_out[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX (.S(wb_la_switch), .A1(wbs_adr_i[21]), .A0(la_data_in[31]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115]));
|
||||
assign la_data_out[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX (.S(wb_la_switch), .A1(wbs_adr_i[22]), .A0(la_data_in[30]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116]));
|
||||
assign la_data_out[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX (.S(wb_la_switch), .A1(wbs_adr_i[23]), .A0(la_data_in[29]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117]));
|
||||
assign la_data_out[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX (.S(wb_la_switch), .A1(wbs_adr_i[24]), .A0(la_data_in[28]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118]));
|
||||
assign la_data_out[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX (.S(wb_la_switch), .A1(wbs_adr_i[25]), .A0(la_data_in[27]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119]));
|
||||
assign la_data_out[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX (.S(wb_la_switch), .A1(wbs_adr_i[26]), .A0(la_data_in[26]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120]));
|
||||
assign la_data_out[26] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX (.S(wb_la_switch), .A1(wbs_adr_i[27]), .A0(la_data_in[25]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121]));
|
||||
assign la_data_out[25] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX (.S(wb_la_switch), .A1(wbs_adr_i[28]), .A0(la_data_in[24]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122]));
|
||||
assign la_data_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX (.S(wb_la_switch), .A1(wbs_adr_i[29]), .A0(la_data_in[23]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123]));
|
||||
assign la_data_out[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX (.S(wb_la_switch), .A1(wbs_adr_i[30]), .A0(la_data_in[22]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124]));
|
||||
assign la_data_out[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX (.S(wb_la_switch), .A1(wbs_adr_i[31]), .A0(la_data_in[21]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125]));
|
||||
assign la_data_out[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX (.S(wb_la_switch), .A1(wbs_sel_i[0]), .A0(la_data_in[20]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126]));
|
||||
assign la_data_out[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX (.S(wb_la_switch), .A1(wbs_sel_i[1]), .A0(la_data_in[19]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127]));
|
||||
assign la_data_out[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX (.S(wb_la_switch), .A1(wbs_sel_i[2]), .A0(la_data_in[18]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128]));
|
||||
assign la_data_out[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX (.S(wb_la_switch), .A1(wbs_sel_i[3]), .A0(la_data_in[17]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129]));
|
||||
assign la_data_out[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX (.S(wb_la_switch), .A1(wbs_we_i), .A0(la_data_in[16]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130]));
|
||||
assign la_data_out[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX (.S(wb_la_switch), .A1(wbs_stb_i), .A0(la_data_in[15]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131]));
|
||||
assign la_data_out[15] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX (.S(wb_la_switch), .A1(wbs_cyc_i), .A0(la_data_in[14]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132]));
|
||||
assign la_data_out[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[13];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(wbs_ack_o));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(la_data_out[13]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX (.S(wb_la_switch), .A1(wb_rst_i), .A0(la_data_in[12]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134]));
|
||||
assign la_data_out[12] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX (.S(wb_la_switch), .A1(wb_clk_i), .A0(la_data_in[11]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135]));
|
||||
assign la_data_out[11] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135];
|
||||
assign prog_clk = io_in[37];
|
||||
assign io_out[37] = 1'b0;
|
||||
assign io_oeb[37] = 1'b1;
|
||||
assign clk = io_in[36];
|
||||
assign io_out[36] = 1'b0;
|
||||
assign io_oeb[36] = 1'b1;
|
||||
assign io_out[35] = ccff_tail;
|
||||
assign io_oeb[35] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = io_in[34];
|
||||
assign io_out[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136];
|
||||
assign io_oeb[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = io_in[33];
|
||||
assign io_out[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137];
|
||||
assign io_oeb[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = io_in[32];
|
||||
assign io_out[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138];
|
||||
assign io_oeb[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = io_in[31];
|
||||
assign io_out[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139];
|
||||
assign io_oeb[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = io_in[30];
|
||||
assign io_out[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140];
|
||||
assign io_oeb[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = io_in[29];
|
||||
assign io_out[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141];
|
||||
assign io_oeb[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = io_in[28];
|
||||
assign io_out[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142];
|
||||
assign io_oeb[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = io_in[27];
|
||||
assign io_out[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143];
|
||||
assign io_oeb[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143];
|
||||
assign sc_head = io_in[26];
|
||||
assign io_out[26] = 1'b0;
|
||||
assign io_oeb[26] = 1'b1;
|
||||
//
|
||||
|
||||
//
|
||||
//
|
||||
assign wb_la_switch = io_in[25];
|
||||
assign io_out[25] = 1'b0;
|
||||
assign io_oeb[25] = 1'b1;
|
||||
|
||||
//
|
||||
|
||||
fpga_core fpga_core_uut(
|
||||
.prog_clk(prog_clk),
|
||||
.Test_en(Test_en),
|
||||
.clk(clk),
|
||||
.IO_ISOL_N(IO_ISOL_N),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
|
||||
.ccff_head(ccff_head),
|
||||
.ccff_tail(ccff_tail),
|
||||
.sc_head(sc_head),
|
||||
.sc_tail(sc_tail),
|
||||
.pReset(pReset),
|
||||
.Reset(Reset)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
`timescale 1ns/1ps
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
module sky130_fd_sc_hd__mux2_1_wrapper (
|
||||
input A0,
|
||||
input A1,
|
||||
input S,
|
||||
output X
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__mux2_1 MUX2 (.A0(A0),
|
||||
.A1(A1),
|
||||
.S(S),
|
||||
.X(X)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,41 @@
|
|||
##########################################################################################
|
||||
##########################################################################################
|
||||
|
||||
SHELL=bash
|
||||
PYTHON_EXEC=python3.8
|
||||
RERUN = 0
|
||||
TB = top
|
||||
OPTIONS =
|
||||
|
||||
.SILENT:
|
||||
.ONESHELL:
|
||||
|
||||
.PHONY: runOpenFPGA
|
||||
runOpenFPGA:
|
||||
SECONDS=0
|
||||
source config.sh
|
||||
# ===================== Check Tools =====================
|
||||
which python3.8 > /dev/null
|
||||
if [ $$? -eq 1 ]; then
|
||||
echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit;
|
||||
fi
|
||||
|
||||
# =================== Clean Previous Run =================================
|
||||
rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME}
|
||||
(cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf)
|
||||
|
||||
# ===================== Generate Netlist =================================
|
||||
(currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir &&
|
||||
run-task $${TASK_DIR_NAME} --remove_run_dir all
|
||||
run-task $${TASK_DIR_NAME} ${OPTIONS})
|
||||
|
||||
if [ $$? -eq 1 ]; then
|
||||
echo "X X X X X X Failed to generate netlist X X X X X X"; exit;
|
||||
fi
|
||||
|
||||
duration=$$SECONDS
|
||||
date > runOpenFPGA
|
||||
echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA
|
||||
|
||||
clean:
|
||||
rm -rf runOpenFPGA
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
FPGA1212_FLAT_HD_SKY_PNR
|
||||
====================
|
||||
|
||||
12x12 FPGA designed using hierarchical flow and `SKY130_FD_SC_HD`.
|
||||
Flat Module design style
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
|
||||
initial begin
|
||||
$dumpfile ("ccff_test.vcd");
|
||||
$dumpvars (1,
|
||||
io_in[37],
|
||||
io_in[36],
|
||||
fpga_core_uut.prog_clk,
|
||||
fpga_core_uut.Reset,
|
||||
fpga_core_uut.pReset,
|
||||
fpga_core_uut.sb_12__12_.ccff_head,
|
||||
fpga_core_uut.sb_12__12_.ccff_tail,
|
||||
fpga_core_uut.ccff_head,
|
||||
fpga_core_uut.ccff_tail
|
||||
);
|
||||
end
|
||||
|
||||
initial begin
|
||||
$dumpvars (0,
|
||||
fpga_core_uut.sb_12__12_,
|
||||
fpga_core_uut.sb_6__0_
|
||||
);
|
||||
end
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
|
||||
initial begin
|
||||
$dumpfile ("scff_test.vcd");
|
||||
$dumpvars (1,
|
||||
io_in[37],
|
||||
io_in[36],
|
||||
io_in[0],
|
||||
fpga_core_uut.scff_Wires,
|
||||
fpga_core_uut.Test_en,
|
||||
|
||||
fpga_core_uut.sb_0__12_.SC_IN_TOP,
|
||||
fpga_core_uut.sb_0__12_.SC_OUT_BOT,
|
||||
fpga_core_uut.grid_clb_1__12_.SC_IN_TOP,
|
||||
fpga_core_uut.grid_clb_1__12_.SC_OUT_BOT,
|
||||
sc_head,
|
||||
sc_tail
|
||||
);
|
||||
end
|
||||
|
||||
initial begin
|
||||
$dumpvars (0,
|
||||
fpga_core_uut.sb_12__12_);
|
||||
end
|
||||
|
|
@ -0,0 +1,615 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
`define FUNCTIONAL 1
|
||||
`define UNIT_DELAY #0.01
|
||||
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2b/sky130_fd_sc_hd__and2b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2b/sky130_fd_sc_hd__and2b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2b/sky130_fd_sc_hd__and2b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2b/sky130_fd_sc_hd__and2b.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and3/sky130_fd_sc_hd__and3_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and3/sky130_fd_sc_hd__and3_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and3/sky130_fd_sc_hd__and3_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and3/sky130_fd_sc_hd__and3.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4b/sky130_fd_sc_hd__and4b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4b/sky130_fd_sc_hd__and4b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4b/sky130_fd_sc_hd__and4b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4b/sky130_fd_sc_hd__and4b.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4/sky130_fd_sc_hd__and4_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4/sky130_fd_sc_hd__and4_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4/sky130_fd_sc_hd__and4_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4/sky130_fd_sc_hd__and4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_16.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_16.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s15/sky130_fd_sc_hd__clkdlybuf4s15_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s15/sky130_fd_sc_hd__clkdlybuf4s15_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s15/sky130_fd_sc_hd__clkdlybuf4s15.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s18/sky130_fd_sc_hd__clkdlybuf4s18_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s18/sky130_fd_sc_hd__clkdlybuf4s18_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s18/sky130_fd_sc_hd__clkdlybuf4s18.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s25/sky130_fd_sc_hd__clkdlybuf4s25_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s25/sky130_fd_sc_hd__clkdlybuf4s25_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s25/sky130_fd_sc_hd__clkdlybuf4s25.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap_12.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap_3.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap_6.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap.v"
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfsbp/sky130_fd_sc_hd__dfsbp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfsbp/sky130_fd_sc_hd__dfsbp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfsbp/sky130_fd_sc_hd__dfsbp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfstp/sky130_fd_sc_hd__dfstp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfstp/sky130_fd_sc_hd__dfstp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfstp/sky130_fd_sc_hd__dfstp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfstp/sky130_fd_sc_hd__dfstp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/diode/sky130_fd_sc_hd__diode_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/diode/sky130_fd_sc_hd__diode.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlclkp/sky130_fd_sc_hd__dlclkp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlclkp/sky130_fd_sc_hd__dlclkp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlclkp/sky130_fd_sc_hd__dlclkp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlclkp/sky130_fd_sc_hd__dlclkp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbn/sky130_fd_sc_hd__dlrbn_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbn/sky130_fd_sc_hd__dlrbn_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbn/sky130_fd_sc_hd__dlrbn.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbp/sky130_fd_sc_hd__dlrbp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbp/sky130_fd_sc_hd__dlrbp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbp/sky130_fd_sc_hd__dlrbp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtn/sky130_fd_sc_hd__dlrtn_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtn/sky130_fd_sc_hd__dlrtn_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtn/sky130_fd_sc_hd__dlrtn_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtn/sky130_fd_sc_hd__dlrtn.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtp/sky130_fd_sc_hd__dlrtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtp/sky130_fd_sc_hd__dlrtp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtp/sky130_fd_sc_hd__dlrtp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtp/sky130_fd_sc_hd__dlrtp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxbn/sky130_fd_sc_hd__dlxbn_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxbn/sky130_fd_sc_hd__dlxbn_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxbn/sky130_fd_sc_hd__dlxbn.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxbp/sky130_fd_sc_hd__dlxbp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxbp/sky130_fd_sc_hd__dlxbp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtn/sky130_fd_sc_hd__dlxtn_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtn/sky130_fd_sc_hd__dlxtn_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtn/sky130_fd_sc_hd__dlxtn_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtn/sky130_fd_sc_hd__dlxtn.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtp/sky130_fd_sc_hd__dlxtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtp/sky130_fd_sc_hd__dlxtp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s4s/sky130_fd_sc_hd__dlymetal6s4s_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s4s/sky130_fd_sc_hd__dlymetal6s4s.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/edfxbp/sky130_fd_sc_hd__edfxbp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/edfxbp/sky130_fd_sc_hd__edfxbp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/edfxtp/sky130_fd_sc_hd__edfxtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/edfxtp/sky130_fd_sc_hd__edfxtp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_0.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvp/sky130_fd_sc_hd__einvp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvp/sky130_fd_sc_hd__einvp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvp/sky130_fd_sc_hd__einvp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvp/sky130_fd_sc_hd__einvp_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvp/sky130_fd_sc_hd__einvp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fahcin/sky130_fd_sc_hd__fahcin_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fahcin/sky130_fd_sc_hd__fahcin.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fahcon/sky130_fd_sc_hd__fahcon_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fahcon/sky130_fd_sc_hd__fahcon.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fah/sky130_fd_sc_hd__fah_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fah/sky130_fd_sc_hd__fah.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fa/sky130_fd_sc_hd__fa_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fa/sky130_fd_sc_hd__fa_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fa/sky130_fd_sc_hd__fa_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fa/sky130_fd_sc_hd__fa.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fill/sky130_fd_sc_hd__fill_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fill/sky130_fd_sc_hd__fill_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fill/sky130_fd_sc_hd__fill_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fill/sky130_fd_sc_hd__fill_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fill/sky130_fd_sc_hd__fill.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ha/sky130_fd_sc_hd__ha_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ha/sky130_fd_sc_hd__ha_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ha/sky130_fd_sc_hd__ha_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ha/sky130_fd_sc_hd__ha.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv.v"
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/macro_sparecell/sky130_fd_sc_hd__macro_sparecell.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/maj3/sky130_fd_sc_hd__maj3_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/maj3/sky130_fd_sc_hd__maj3_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/maj3/sky130_fd_sc_hd__maj3_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/maj3/sky130_fd_sc_hd__maj3.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2i/sky130_fd_sc_hd__mux2i_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2i/sky130_fd_sc_hd__mux2i_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2i/sky130_fd_sc_hd__mux2i_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2i/sky130_fd_sc_hd__mux2i.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux4/sky130_fd_sc_hd__mux4_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux4/sky130_fd_sc_hd__mux4_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux4/sky130_fd_sc_hd__mux4_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux4/sky130_fd_sc_hd__mux4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2b/sky130_fd_sc_hd__nand2b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2b/sky130_fd_sc_hd__nand2b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2b/sky130_fd_sc_hd__nand2b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2b/sky130_fd_sc_hd__nand2b.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand3/sky130_fd_sc_hd__nand3_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand3/sky130_fd_sc_hd__nand3_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand3/sky130_fd_sc_hd__nand3_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand3/sky130_fd_sc_hd__nand3.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4b/sky130_fd_sc_hd__nand4b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4b/sky130_fd_sc_hd__nand4b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4b/sky130_fd_sc_hd__nand4b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4b/sky130_fd_sc_hd__nand4b.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4/sky130_fd_sc_hd__nand4_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4/sky130_fd_sc_hd__nand4_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4/sky130_fd_sc_hd__nand4_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4/sky130_fd_sc_hd__nand4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor3/sky130_fd_sc_hd__nor3_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor3/sky130_fd_sc_hd__nor3_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor3/sky130_fd_sc_hd__nor3_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor3/sky130_fd_sc_hd__nor3.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4b/sky130_fd_sc_hd__nor4b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4b/sky130_fd_sc_hd__nor4b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4b/sky130_fd_sc_hd__nor4b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4b/sky130_fd_sc_hd__nor4b.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4/sky130_fd_sc_hd__nor4_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4/sky130_fd_sc_hd__nor4_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4/sky130_fd_sc_hd__nor4_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4/sky130_fd_sc_hd__nor4.v"
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfsbp/sky130_fd_sc_hd__sdfsbp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfsbp/sky130_fd_sc_hd__sdfsbp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfsbp/sky130_fd_sc_hd__sdfsbp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfstp/sky130_fd_sc_hd__sdfstp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfstp/sky130_fd_sc_hd__sdfstp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfstp/sky130_fd_sc_hd__sdfstp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfstp/sky130_fd_sc_hd__sdfstp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdlclkp/sky130_fd_sc_hd__sdlclkp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdlclkp/sky130_fd_sc_hd__sdlclkp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdlclkp/sky130_fd_sc_hd__sdlclkp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdlclkp/sky130_fd_sc_hd__sdlclkp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxbp/sky130_fd_sc_hd__sedfxbp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxbp/sky130_fd_sc_hd__sedfxbp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxbp/sky130_fd_sc_hd__sedfxbp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxtp/sky130_fd_sc_hd__sedfxtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxtp/sky130_fd_sc_hd__sedfxtp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxtp/sky130_fd_sc_hd__sedfxtp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxtp/sky130_fd_sc_hd__sedfxtp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tap/sky130_fd_sc_hd__tap_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tap/sky130_fd_sc_hd__tap_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tap/sky130_fd_sc_hd__tap.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvgnd2/sky130_fd_sc_hd__tapvgnd2_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvgnd2/sky130_fd_sc_hd__tapvgnd2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvgnd/sky130_fd_sc_hd__tapvgnd_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvgnd/sky130_fd_sc_hd__tapvgnd.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvpwrvgnd/sky130_fd_sc_hd__tapvpwrvgnd_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvpwrvgnd/sky130_fd_sc_hd__tapvpwrvgnd.v"
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
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|
||||
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|
||||
//
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4bb/sky130_fd_sc_hd__or4bb_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4bb/sky130_fd_sc_hd__or4bb_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4bb/sky130_fd_sc_hd__or4bb_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4bb/sky130_fd_sc_hd__or4bb.v"
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3b/sky130_fd_sc_hd__or3b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3b/sky130_fd_sc_hd__or3b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3b/sky130_fd_sc_hd__or3b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3b/sky130_fd_sc_hd__or3b.v"
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2b/sky130_fd_sc_hd__or2b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2b/sky130_fd_sc_hd__or2b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2b/sky130_fd_sc_hd__or2b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2b/sky130_fd_sc_hd__or2b.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3/sky130_fd_sc_hd__or3_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3/sky130_fd_sc_hd__or3_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3/sky130_fd_sc_hd__or3_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3/sky130_fd_sc_hd__or3.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4b/sky130_fd_sc_hd__or4b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4b/sky130_fd_sc_hd__or4b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4b/sky130_fd_sc_hd__or4b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4b/sky130_fd_sc_hd__or4b.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4/sky130_fd_sc_hd__or4_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4/sky130_fd_sc_hd__or4_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4/sky130_fd_sc_hd__or4_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4/sky130_fd_sc_hd__or4.v"
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
|
||||
initial begin
|
||||
$dumpfile ("ccff_test.vcd");
|
||||
$dumpvars (1, prog_clk_pad,
|
||||
prog_clk,
|
||||
ccff_head_pad,
|
||||
ccff_head,
|
||||
fpga_core_uut.sb_2__2_.ccff_tail,
|
||||
fpga_core_uut.cbx_2__2_.ccff_tail,
|
||||
fpga_core_uut.grid_io_top_2__3_.ccff_tail,
|
||||
fpga_core_uut.sb_1__2_.ccff_tail,
|
||||
fpga_core_uut.cbx_1__2_.ccff_tail,
|
||||
fpga_core_uut.grid_io_top_1__3_.ccff_tail,
|
||||
fpga_core_uut.sb_0__2_.ccff_tail,
|
||||
fpga_core_uut.cby_0__2_.ccff_tail,
|
||||
fpga_core_uut.grid_io_left_0__2_.ccff_tail,
|
||||
fpga_core_uut.grid_clb_1__2_.ccff_tail,
|
||||
fpga_core_uut.cby_1__2_.ccff_tail,
|
||||
fpga_core_uut.grid_clb_2__2_.ccff_tail,
|
||||
fpga_core_uut.cby_2__2_.ccff_tail,
|
||||
fpga_core_uut.grid_io_right_3__2_.ccff_tail,
|
||||
fpga_core_uut.sb_2__1_.ccff_tail,
|
||||
fpga_core_uut.cbx_2__1_.ccff_tail,
|
||||
fpga_core_uut.sb_1__1_.ccff_tail,
|
||||
fpga_core_uut.cbx_1__1_.ccff_tail,
|
||||
fpga_core_uut.sb_0__1_.ccff_tail,
|
||||
fpga_core_uut.cby_0__1_.ccff_tail,
|
||||
fpga_core_uut.grid_io_left_0__1_.ccff_tail,
|
||||
fpga_core_uut.grid_clb_1__1_.ccff_tail,
|
||||
fpga_core_uut.cby_1__1_.ccff_tail,
|
||||
fpga_core_uut.grid_clb_2__1_.ccff_tail,
|
||||
fpga_core_uut.cby_2__1_.ccff_tail,
|
||||
fpga_core_uut.grid_io_right_3__1_.ccff_tail,
|
||||
fpga_core_uut.sb_2__0_.ccff_tail,
|
||||
fpga_core_uut.cbx_2__0_.ccff_tail,
|
||||
fpga_core_uut.grid_io_bottom_2__0_.ccff_tail,
|
||||
fpga_core_uut.sb_1__0_.ccff_tail,
|
||||
fpga_core_uut.cbx_1__0_.ccff_tail,
|
||||
fpga_core_uut.grid_io_bottom_1__0_.ccff_tail,
|
||||
fpga_core_uut.sb_0__0_.ccff_tail,
|
||||
ccff_tail_pad,
|
||||
ccff_tail);
|
||||
end
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
|
||||
## = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
## Verification makefile for FPGA1212_RESET_HD_SKY_PNR (Caravel-QLSOFA-HD)
|
||||
## = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
SHELL=bash
|
||||
PYTHON_EXEC=python3.8
|
||||
RERUN = 0
|
||||
TB = top
|
||||
OPTIONS =
|
||||
SIM = modelsim
|
||||
TEST_FILE = fpga_reset_hd_sky_pnr
|
||||
|
||||
.SILENT:
|
||||
.ONESHELL:
|
||||
|
||||
## Copy all the POSTPnR files from realease directory
|
||||
UpdatePostPnRNetlist:
|
||||
source ../config.sh
|
||||
DESIGN_NAME=$${TOP_MODULE:-$${DESIGN_NAME}}
|
||||
echo "Collecting files $${DESIGN_NAME}"
|
||||
cp ../pnr/$${DESIGN_NAME}/outputs_icc2/$${DESIGN_NAME}_icv_in_design.pt.v . || \
|
||||
cp ../$${DESIGN_NAME}/outputs_icc2/$${DESIGN_NAME}_icv_in_design.pt.v . || :
|
||||
|
||||
|
||||
## Create symbolic links and run test
|
||||
RunPostPnRTest:
|
||||
source ../config.sh
|
||||
INCLUDE_POSTPNR=$${INCLUDE_POSTPNR:-include_postpnr}
|
||||
DESIGN_NAME=$${TOP_MODULE:-$${DESIGN_NAME}}
|
||||
VerificationFile=$${TEST_FILE:-${TEST_FILE}}
|
||||
# = = = = = = = = = = = = = = Log Information = = = = = = = = = = = =
|
||||
echo "DESIGN_NAME = $${DESIGN_NAME}"
|
||||
echo "VerificationFile = $${DESIGN_NAME}"
|
||||
echo "INCLUDE_FILE = $${INCLUDE_POSTPNR}"
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
echo $${VerificationFile}
|
||||
if [ ! -f "./$${VerificationFile}.py" ]; then
|
||||
echo "Test file not found $${VerificationFile}.py"
|
||||
fi
|
||||
echo "Using test file $${VerificationFile}.py"
|
||||
Tests=`grep -A 1 "^@cocotb.test" ./$${VerificationFile}.py | grep "def" | sed "s/.*def \(.*\)(.*/\1/g"`
|
||||
select RUN_TB in $${Tests}
|
||||
do
|
||||
echo "Running $${RUN_TB} Test"
|
||||
if [[ -d "$${RUN_TB}_run" ]] && [[ -z "$${RERUN}" ]]; then
|
||||
echo "Skipping copying source, which will skip the compilations";
|
||||
cp *_tests.py ./$${RUN_TB}_run;
|
||||
cd $${RUN_TB}_run; break;
|
||||
fi
|
||||
|
||||
# = = = = = = = = = = = Prepare Netlist = = = = = = = = = = = = = =
|
||||
# = = = = = = = = = = = Copy python test = = = = = = = = = = = = =
|
||||
mkdir -p "$${RUN_TB}_run"
|
||||
cp $${VerificationFile}.py ./$${RUN_TB}_run
|
||||
cp $${DESIGN_NAME}_icv_in_design.pt.v ./$${RUN_TB}_run/$${DESIGN_NAME}_cocosim.v
|
||||
|
||||
TaskDir=`readlink -f ../*_Verilog/TaskConfigCopy`
|
||||
TaskDir2=`readlink -f ../*_task`
|
||||
if [ -d "$$TaskDir" ]; then
|
||||
rm -rf ./$${RUN_TB}_run/TaskConfigCopy && ln -s $${TaskDir} ./$${RUN_TB}_run
|
||||
elif [ -d "$$TaskDir2" ]; then
|
||||
TaskDir=`readlink -f ../*_task`
|
||||
rm -rf ./$${RUN_TB}_run/TaskConfigCopy && ln -s $${TaskDir} ./$${RUN_TB}_run/TaskConfigCopy
|
||||
else
|
||||
echo "Task configuration directory not found"
|
||||
fi
|
||||
# = = = = = = = = = = = Enter Run Directory = = = = = = = = = = = = =
|
||||
cd $${RUN_TB}_run
|
||||
cp ../INIT/$${INCLUDE_POSTPNR}.v ./fabric_netlists_cocosim.v
|
||||
echo "\`include \"$$(readlink -f $${DESIGN_NAME}_cocosim.v)\"" >> ./fabric_netlists_cocosim.v
|
||||
|
||||
# = = = = = = = = = = = Insert Init Signals = = = = = = = = = = = =
|
||||
if test -f "../INIT/$${RUN_TB}_init.v"; then
|
||||
echo "Found Initialization file [../INIT/$${RUN_TB}_init.v]"
|
||||
modLineNo=$$(grep -n "module fpga_top" $${DESIGN_NAME}_cocosim.v | cut -f1 -d:)
|
||||
echo $${modLineNo}
|
||||
sed -i "$${modLineNo},\$${/endmodule/d}" $${DESIGN_NAME}_cocosim.v
|
||||
cat ../INIT/$${RUN_TB}_init.v >> $${DESIGN_NAME}_cocosim.v
|
||||
printf "\nendmodule" >> $${DESIGN_NAME}_cocosim.v
|
||||
else
|
||||
echo "No Initialization file found [../INIT/$${RUN_TB}_init.v]"
|
||||
fi
|
||||
|
||||
# = = = = = = = = Create Makefile to run = = = = = = = = = = = = = =
|
||||
echo "TOPLEVEL_LANG = verilog" > Makefile
|
||||
echo "VERILOG_SOURCES = fabric_netlists_cocosim.v" >> Makefile
|
||||
echo "TOPLEVEL = $${DESIGN_NAME}" >> Makefile
|
||||
echo "MODULE = $${VerificationFile}" >> Makefile
|
||||
echo "TESTCASE = $${RUN_TB}" >> Makefile
|
||||
echo "" >> Makefile
|
||||
echo "include $(shell cocotb-config --makefiles)/Makefile.sim" >> Makefile
|
||||
break
|
||||
done
|
||||
if [ -z "$$DRY_RUN" ]; then make SIM=$${SIM:-${SIM}}; fi
|
||||
|
|
@ -0,0 +1,349 @@
|
|||
import random
|
||||
import os
|
||||
import sys
|
||||
import glob
|
||||
import math
|
||||
import cocotb
|
||||
import logging
|
||||
import filecmp
|
||||
from logging.handlers import RotatingFileHandler
|
||||
from collections import OrderedDict
|
||||
from pprint import pprint
|
||||
from xml.dom import minidom
|
||||
from cocotb.binary import BinaryValue
|
||||
from cocotb.log import SimLogFormatter
|
||||
from cocotb.clock import Clock
|
||||
from cocotb import wavedrom
|
||||
from cocotb.utils import get_sim_time
|
||||
from cocotb.handle import Force, Release, Deposit
|
||||
from cocotb.monitors import Monitor
|
||||
from cocotb.scoreboard import Scoreboard
|
||||
from cocotb.result import SimTimeoutError, TestFailure, SimTimeoutError, TestSuccess
|
||||
from cocotb.triggers import FallingEdge, RisingEdge, Timer, ClockCycles, with_timeout, First
|
||||
|
||||
root_logger = logging.getLogger()
|
||||
|
||||
|
||||
file_handler = RotatingFileHandler(
|
||||
"run.log", maxBytes=(5 * 1024 * 1024), backupCount=2)
|
||||
root_logger.addHandler(file_handler)
|
||||
|
||||
# Caravel interface pin mapping
|
||||
FromPinAlias = {
|
||||
"prog_clk": "io_in[37]",
|
||||
"clk": "io_in[36]",
|
||||
"pReset": "io_in[3]",
|
||||
"Reset": "io_in[2]",
|
||||
"test_en": "io_in[0]",
|
||||
"sc_head": "io_in[26]",
|
||||
"sc_tail": "io_in[11]",
|
||||
"ccff_head": "io_in[12]",
|
||||
"ccff_tail": "io_in[35]",
|
||||
}
|
||||
|
||||
|
||||
def getFromPinAlias(dut, pinName):
|
||||
''' Get DUT pin from alias '''
|
||||
return eval(f"dut.{FromPinAlias[pinName]}")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def ConfigChainTestFull(dut):
|
||||
# = = = = = = = Get Design Variable = = = = = = = = = = = = = = = = =
|
||||
PConf = getConfig()
|
||||
clk = getFromPinAlias(dut, "clk")
|
||||
prog_clk = getFromPinAlias(dut, "prog_clk")
|
||||
test_en = getFromPinAlias(dut, "test_en")
|
||||
pReset = getFromPinAlias(dut, "pReset")
|
||||
Reset = getFromPinAlias(dut, "Reset")
|
||||
ccff_head = getFromPinAlias(dut, "ccff_head")
|
||||
ccff_tail = getFromPinAlias(dut, "ccff_tail")
|
||||
PCLK_PERIOD = 10 # in nanoseconds
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
clk <= 0 # Disable prog clock
|
||||
Reset <= 0 # Disable reset
|
||||
pReset <= 0 # Reset all configuration FF
|
||||
pclock = Clock(prog_clk, PCLK_PERIOD*0.5, units="ns")
|
||||
cocotb.fork(pclock.start()) # Start the clock
|
||||
|
||||
# Clock Preamble Ticks 2
|
||||
await ClockCycles(prog_clk, 2)
|
||||
await FallingEdge(prog_clk)
|
||||
pReset <= 1
|
||||
|
||||
# Pass 1 bit logic to CCFF chain
|
||||
ccff_head <= 1
|
||||
await FallingEdge(prog_clk)
|
||||
ccff_head <= 0
|
||||
|
||||
# Check CCFF_tail of each module in sequence
|
||||
CCFFChain = filter(lambda x: not "grid_io" in x, CreateCCFFChain())
|
||||
try:
|
||||
start_ccff_time = get_sim_time(units='ns')
|
||||
for ModuleName in CCFFChain:
|
||||
InstPtr = eval(f"dut.fpga_core_uut.{ModuleName}.ccff_tail")
|
||||
|
||||
# Wait for tick
|
||||
start_time_ns = get_sim_time(units='ns')
|
||||
await with_timeout(FallingEdge(InstPtr), 200*PCLK_PERIOD, 'ns')
|
||||
edge_time_ns = get_sim_time(units='ns')
|
||||
|
||||
# Verify
|
||||
CLKTick = math.ceil((edge_time_ns-start_time_ns)/PCLK_PERIOD)
|
||||
dut._log.info(
|
||||
f"Signal received at {ModuleName} at {CLKTick}")
|
||||
if (CLKTick != 8):
|
||||
TestFailure(
|
||||
f"Expected 8 ticks on module {ModuleName} received {CLKTick}")
|
||||
end_ccff_time = get_sim_time(units='ns')
|
||||
await ClockCycles(prog_clk, 10)
|
||||
TotalClock = math.ceil((end_ccff_time-start_ccff_time)/PCLK_PERIOD)
|
||||
dut._log.info(f"Simulation Finished in clocks {TotalClock}")
|
||||
except SimTimeoutError:
|
||||
raise TestFailure(f"Failed to receive signal on {ModuleName}")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def ScanChainTestFull(dut):
|
||||
# = = = = = = = Get Design Variable = = = = = = = = = = = = = = = = =
|
||||
PConf = getConfig()
|
||||
clk = getFromPinAlias(dut, "clk")
|
||||
prog_clk = getFromPinAlias(dut, "prog_clk")
|
||||
pReset = getFromPinAlias(dut, "pReset")
|
||||
Reset = getFromPinAlias(dut, "Reset")
|
||||
test_en = getFromPinAlias(dut, "test_en")
|
||||
sc_head = getFromPinAlias(dut, "sc_head")
|
||||
sc_tail = getFromPinAlias(dut, "sc_tail")
|
||||
CLK_PERIOD = 10 # in nanoseconds
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
prog_clk <= 0 # Disable prog clock
|
||||
pReset <= 0 # Disable programming reset
|
||||
Reset <= 0 # Disable reset
|
||||
clock = Clock(clk, CLK_PERIOD*0.5, units="ns")
|
||||
cocotb.fork(clock.start()) # Start the clock
|
||||
|
||||
# Clock Preamble Ticks 2
|
||||
await ClockCycles(clk, 2)
|
||||
|
||||
# Setup control signals
|
||||
await FallingEdge(clk)
|
||||
test_en <= 1
|
||||
Reset <= 1
|
||||
|
||||
# Pass 1 bit logic to SCFF chain
|
||||
sc_head <= 1
|
||||
await FallingEdge(clk)
|
||||
sc_head <= 0
|
||||
|
||||
try:
|
||||
start_scff_time = get_sim_time(units='ns')
|
||||
for X in range(1, 1+PConf["FPGA_SIZE_X"]):
|
||||
Yrange = range(1, 1+PConf["FPGA_SIZE_X"])
|
||||
Yrange = reversed(Yrange) if (X % 2) else Yrange
|
||||
for Y in Yrange:
|
||||
ModuleName = f"grid_clb_{X}__{Y}_"
|
||||
PinName = "SC_OUT_BOT" if (X % 2) else "SC_OUT_TOP"
|
||||
InstPtr = eval(f"dut.fpga_core_uut.{ModuleName}.{PinName}")
|
||||
# Wait for tick
|
||||
start_time_ns = get_sim_time(units='ns')
|
||||
await with_timeout(FallingEdge(InstPtr), 50*CLK_PERIOD, 'ns')
|
||||
edge_time_ns = get_sim_time(units='ns')
|
||||
|
||||
# Verify
|
||||
CLKTick = math.ceil((edge_time_ns-start_time_ns)/CLK_PERIOD)
|
||||
dut._log.info(
|
||||
f"Signal received at {ModuleName} at {CLKTick}")
|
||||
if (CLKTick != 8):
|
||||
TestFailure(
|
||||
f"Expected 8 ticks on module {ModuleName} received {CLKTick}")
|
||||
end_scff_time = get_sim_time(units='ns')
|
||||
TotalClock = math.ceil((end_scff_time-start_scff_time)/CLK_PERIOD)
|
||||
await ClockCycles(clk, 10)
|
||||
dut._log.info(f"Simulation Finished in clocks {TotalClock}")
|
||||
dut._log.info(f"Per Grid {TotalClock/(PConf['FPGA_SIZE_X']**2)}")
|
||||
except SimTimeoutError:
|
||||
raise TestFailure(f"Failed to receive signal on {ModuleName}")
|
||||
|
||||
|
||||
# ###================================================================
|
||||
# = = = = = = = = = = Utils Functions = = = = = = = = = = = = = = = =
|
||||
# ###================================================================
|
||||
|
||||
|
||||
def getConfig():
|
||||
"""
|
||||
return config.sh varaibles with default values
|
||||
"""
|
||||
return {
|
||||
"TECHNOLOGY": os.environ.get('TECHNOLOGY', 'skywater'),
|
||||
"PROJ_NAME": os.environ.get('PROJ_NAME', None),
|
||||
"DESIGN_STYLE": os.environ.get('DESIGN_STYLE', "hier"),
|
||||
"FPGA_SIZE_X": int(os.environ.get('FPGA_SIZE_X', 0)),
|
||||
"FPGA_SIZE_Y": int(os.environ.get('FPGA_SIZE_Y', 0)),
|
||||
}
|
||||
|
||||
|
||||
@cocotb.coroutine
|
||||
async def ProgramPhase(dut, BitFile, maxCycles=sys.maxsize):
|
||||
dut.pReset_pad = 0
|
||||
bitCount = 0
|
||||
with open(BitFile, "r") as fp:
|
||||
dut._log.info(f"Bitfile opened : {BitFile}")
|
||||
while bitCount < maxCycles:
|
||||
c = fp.read(1)
|
||||
if not c in ["0", "1"]:
|
||||
dut._log.info(f"Configured device with {bitCount} bits")
|
||||
break
|
||||
bitCount += 1
|
||||
if (bitCount % 50) == 0:
|
||||
dut._log.info(f"Writen {bitCount} bits")
|
||||
dut.ccff_head_pad = int(c)
|
||||
await FallingEdge(dut.prog_clk_pad)
|
||||
|
||||
|
||||
@cocotb.coroutine
|
||||
async def AutoConfigure(dut, BitFile, ccPaths, BitstreamLen):
|
||||
TotalBitsCount = 0
|
||||
PreviousSync = 0
|
||||
# Locking Signal
|
||||
with open(BitFile, "r") as fp:
|
||||
dut._log.info(f"Bitfile opened {BitFile}")
|
||||
syncPts = math.ceil(BitstreamLen/4800)
|
||||
InitialBits = [int(i) for i in list(fp.read(syncPts+1))]
|
||||
dut._log.info(f"Will make total {syncPts} sync {InitialBits}")
|
||||
for inst, eachModule in ccPaths.items():
|
||||
BitsCount = 0
|
||||
for eachPath in eachModule:
|
||||
size = eachPath["width"]
|
||||
BitsCount += size
|
||||
try:
|
||||
Stream = fp.read(size)
|
||||
bits = int(Stream, 2)
|
||||
except:
|
||||
dut._log.info(f"Padding Zero")
|
||||
bits = 0
|
||||
eachPath["obj"] <= Force(bits)
|
||||
TotalBitsCount += BitsCount
|
||||
dut._log.info(f"Configured {inst} with {BitsCount} bits ")
|
||||
dut.ccff_head_pad <= InitialBits.pop()
|
||||
await FallingEdge(dut.prog_clk_pad)
|
||||
|
||||
# Releasing Signals
|
||||
PreviousSync = 0
|
||||
TotalBitsCount = 0
|
||||
for inst, eachModule in ccPaths.items():
|
||||
for eachPath in eachModule:
|
||||
eachPath["obj"] <= Release()
|
||||
TotalBitsCount += eachPath["width"]
|
||||
if (TotalBitsCount-PreviousSync) > 4800:
|
||||
dut.ccff_head_pad <= InitialBits.pop()
|
||||
await FallingEdge(dut.prog_clk_pad)
|
||||
PreviousSync = TotalBitsCount
|
||||
dut._log.info(f"Releasing config of {inst}")
|
||||
dut.ccff_head_pad <= InitialBits.pop()
|
||||
await FallingEdge(dut.prog_clk_pad)
|
||||
dut._log.info(f"Configured {TotalBitsCount} bits")
|
||||
|
||||
|
||||
def SaveConfiguration(CFFPaths, filename, style="default"):
|
||||
lineW = 0
|
||||
with open(filename, "w") as fp:
|
||||
for _, eachModule in CFFPaths.items():
|
||||
for eachPath in eachModule:
|
||||
val = eachPath["obj"].value.binstr
|
||||
if style == 'default':
|
||||
val = "\n".join(list(val))
|
||||
fp.write(val+"\n")
|
||||
elif style == "bitstream":
|
||||
fp.write(val)
|
||||
elif style == "detailed":
|
||||
fp.write(f"{eachPath['name']} {val}\n")
|
||||
elif style == "adjusted":
|
||||
for eachC in val:
|
||||
fp.write(eachC)
|
||||
lineW += 1
|
||||
if (lineW == 32):
|
||||
fp.write("\n")
|
||||
lineW = 0
|
||||
|
||||
|
||||
def CreateCCFFChain():
|
||||
CCFFChain = []
|
||||
mydoc = minidom.parse(
|
||||
glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0])
|
||||
items = mydoc.getElementsByTagName('key')
|
||||
for elem in items:
|
||||
CCFFChain.append(elem.attributes['alias'].value)
|
||||
return CCFFChain
|
||||
|
||||
|
||||
def returnPaths(Node, PathList):
|
||||
Nodes = [e for e in Node.childNodes if not isinstance(e, minidom.Text)]
|
||||
# pprint(Nodes)
|
||||
for eachN in Nodes:
|
||||
eachNChild = [
|
||||
e for e in eachN.childNodes if not isinstance(e, minidom.Text)]
|
||||
Bitstream = [e for e in eachNChild if e.tagName == "bitstream"]
|
||||
if Bitstream:
|
||||
Hier = eachN.getElementsByTagName("hierarchy")[0]
|
||||
path = [each.attributes["name"].value
|
||||
for each in Hier.getElementsByTagName("instance")]
|
||||
path = ".".join(path).replace('fpga_top', 'dut.fpga_core_uut')
|
||||
|
||||
bitEles = Bitstream[0].getElementsByTagName("bit")
|
||||
ports = [path + "." + each.attributes["memory_port"].value.split("[")[0]
|
||||
for each in bitEles[:1]]
|
||||
length = len(bitEles)
|
||||
value = "".join([e.attributes["value"].value for e in bitEles])
|
||||
PathList.append({
|
||||
"name": ports[0],
|
||||
"width": length,
|
||||
"value": value
|
||||
})
|
||||
elif eachN.tagName == "bitstream_block":
|
||||
returnPaths(eachN, PathList)
|
||||
|
||||
|
||||
def get_modules():
|
||||
FabricKey = minidom.parse(
|
||||
glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0])
|
||||
items = FabricKey.getElementsByTagName('key')
|
||||
return [elem.attributes['alias'].value for elem in items]
|
||||
|
||||
|
||||
def CreateCCFFChainPaths(dut):
|
||||
BitstreamXML = minidom.parse(
|
||||
glob.glob("./TESTBENCH/top/fabric_indepenent_bitstream.xml")[0])
|
||||
|
||||
ModulesDict = {}
|
||||
BT_BLocks = BitstreamXML.getElementsByTagName('bitstream_block')
|
||||
for element in BT_BLocks:
|
||||
if element.getAttribute('hierarchy_level') == "1":
|
||||
ModulesDict[element.attributes['name'].value] = element
|
||||
|
||||
FabricKey = minidom.parse(
|
||||
glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0])
|
||||
items = FabricKey.getElementsByTagName('key')
|
||||
|
||||
pathList = OrderedDict()
|
||||
chainLength = 0
|
||||
|
||||
for elem in items:
|
||||
modulePaths = []
|
||||
moduleLen = 0
|
||||
inst = elem.attributes['alias'].value
|
||||
returnPaths(ModulesDict[inst], modulePaths)
|
||||
for eachEle in modulePaths:
|
||||
eachEle["obj"] = eval(eachEle["name"])
|
||||
moduleLen += eachEle["width"]
|
||||
pathList[inst] = modulePaths
|
||||
chainLength += moduleLen
|
||||
return (chainLength, pathList)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
CC = CreateCCFFChainPaths(None)
|
||||
pprint(CC["grid_clb_1__2_"][:5])
|
||||
pprint(len(CC["grid_clb_1__2_"]))
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# = = = = = = = = = = = = = = Variables Sections = = = = = = = = = = = = = = =
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
export PROJ_NAME=FPGA1212_SOFA_PLUS_HD # Project Name
|
||||
export FPGA_SIZE_X=12 # Grid X Size
|
||||
export FPGA_SIZE_Y=12 # Grid Y Size
|
||||
# Design Style [hier/flat], mostly hier
|
||||
export DESIGN_STYLE=hier
|
||||
export TECHNOLOGY="skywater"
|
||||
|
||||
# Complete Chip (fpga_top) or eFPGA (fpga_core)
|
||||
export DESIGN_NAME=fpga_core
|
||||
|
||||
# Pin Information Source Automatic or Sheet
|
||||
export PIN_MAP=Automatic
|
||||
export PIN_MAP_CSV_SPREADSHEET_LINK="" # Required only if PIN_MAP==Sheet
|
||||
|
||||
# Core Dimension, requires if DESIGN_NAME=fpga_core
|
||||
# if DESIGN_NAME=fpga_top its Optional if defined it overrides the
|
||||
# Calculated DIE_DIMENSION
|
||||
export DIE_DIMENSION=3200
|
||||
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Derived Or Fixed Variables
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
export OPENFPGA_ENGINE_PATH=${OPENFPGA_PATH}
|
||||
export TASK_DIR_NAME=${PROJ_NAME}_task
|
||||
export VERILOG_PROJ_DIR=${PROJ_NAME}_Verilog
|
||||
export SPY_HACK_FILE=${TASK_DIR_NAME}/spy_hack.txt
|
||||
export POST_OPENFPGA_SCRIPT=./PostOpenFPGAScript.sh
|
||||
export RESTRUCT_NETLIST=../utils/RestructureNetlistSkywater.py
|
||||
export POST_GENERATION_SCRIPT=./generate_scandef_and_case_analysis.sh
|
||||
|
||||
export TAPEOUT_DIRECTORY=/research/ece/lnis/USERS/DARPA_ERI/Tapeout/SOFA
|
||||
export TAPEOUT_SCRIPT=
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Restructure Netlist Varaibles
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# export RESTRUCTURE_skipClockRestructure=""
|
||||
# export RESTRUCTURE_Skeleton=""
|
||||
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# PNR RELATED FLOW
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
export INIT_DESIGN_INPUT="ASCII"
|
||||
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Extra variables availble during flow (suuffix FLOWVAR_)
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
export FLOWVAR_STANDARD_CELLS="sc_hd"
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
# Run VPR for the 'and' design
|
||||
#--write_rr_graph example_rr_graph.xml
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --constant_net_method route
|
||||
|
||||
# Read OpenFPGA architecture definition
|
||||
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
|
||||
|
||||
# Read OpenFPGA simulation settings
|
||||
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
|
||||
|
||||
# Annotate the OpenFPGA architecture to VPR data base
|
||||
# to debug use --verbose options
|
||||
link_openfpga_arch --sort_gsb_chan_node_in_edges
|
||||
|
||||
# Check and correct any naming conflicts in the BLIF netlist
|
||||
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
|
||||
|
||||
# Apply fix-up to clustering nets based on routing results
|
||||
pb_pin_fixup --verbose
|
||||
|
||||
# Apply fix-up to Look-Up Table truth tables based on packing results
|
||||
lut_truth_table_fixup
|
||||
|
||||
# Build the module graph
|
||||
# - Enabled compression on routing architecture modules
|
||||
# - Enable pin duplication on grid modules
|
||||
build_fabric --compress_routing #--verbose
|
||||
|
||||
# Write the fabric hierarchy of module graph to a file
|
||||
# This is used by hierarchical PnR flows
|
||||
write_fabric_hierarchy --file ./fabric_hierarchy.txt
|
||||
|
||||
# Repack the netlist to physical pbs
|
||||
# This must be done before bitstream generator and testbench generation
|
||||
# Strongly recommend it is done after all the fix-up have been applied
|
||||
repack #--verbose
|
||||
|
||||
# Build the bitstream
|
||||
# - Output the fabric-independent bitstream to a file
|
||||
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
|
||||
|
||||
# Build fabric-dependent bitstream
|
||||
build_fabric_bitstream --verbose
|
||||
|
||||
# Write fabric-dependent bitstream
|
||||
write_fabric_bitstream --file fabric_bitstream.xml --format xml
|
||||
|
||||
# Write the Verilog netlist for FPGA fabric
|
||||
# - Enable the use of explicit port mapping in Verilog netlist
|
||||
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
|
||||
|
||||
# Write the Verilog testbench for FPGA fabric
|
||||
# - We suggest the use of same output directory as fabric Verilog netlists
|
||||
# - Must specify the reference benchmark file if you want to output any testbenches
|
||||
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
|
||||
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
|
||||
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
|
||||
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator #--explicit_port_mapping
|
||||
|
||||
# Write the SDC files for PnR backend
|
||||
# - Turn on every options here
|
||||
write_pnr_sdc --file ./SDC
|
||||
|
||||
# Write SDC to disable timing for configure ports
|
||||
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
|
||||
|
||||
# Write the SDC to run timing analysis for a mapped FPGA fabric
|
||||
write_analysis_sdc --file ./SDC_analysis
|
||||
|
||||
# Finish and exit OpenFPGA
|
||||
exit
|
||||
|
||||
# Note :
|
||||
# To run verification at the end of the flow maintain source in ./SRC directory
|
||||
Loading…
Reference in New Issue