diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
index 5fb44c4..e85ac4a 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -182,13 +182,14 @@
-
+
+
@@ -220,7 +221,7 @@
-
+
diff --git a/DOC/source/arch/figures/embedded_io_schematic.png b/DOC/source/arch/figures/embedded_io_schematic.png
new file mode 100644
index 0000000..261f452
Binary files /dev/null and b/DOC/source/arch/figures/embedded_io_schematic.png differ
diff --git a/DOC/source/arch/index.rst b/DOC/source/arch/index.rst
index 027c942..d28ed8e 100644
--- a/DOC/source/arch/index.rst
+++ b/DOC/source/arch/index.rst
@@ -4,8 +4,8 @@
.. toctree::
:maxdepth: 2
- io_resource
-
fpga_arch
+ io_resource
+
clb_arch
diff --git a/DOC/source/arch/io_resource.rst b/DOC/source/arch/io_resource.rst
index f93f780..9b29a08 100644
--- a/DOC/source/arch/io_resource.rst
+++ b/DOC/source/arch/io_resource.rst
@@ -64,3 +64,30 @@ When the logic analyzer interface is enabled, the FPGA can operate in debug mode
:alt: I/O arrangement of FPGA IP when interfacing logic analyzer
I/O arrangement of *High-Density* (HD) FPGA IP when interfacing logic analyzer
+
+.. _io_resource_circuit:
+
+FPGA I/O Circuit
+~~~~~~~~~~~~~~~~
+
+As shown in :numref:`fig_embedded_io_schematic`, the I/O circuit used in the I/O tiles of the FPGA fabric (see :numref:`fig_fpga_arch`) is an digital I/O cell with
+
+- An **active-low** I/O isolation signal ``IO_ISOL_N`` to set the I/O in input mode. This is to avoid any unexpected output signals to damage circuits outside the FPGA due to configurable memories are not properly initialized.
+
+ .. warning:: This feature may not be needed if the configurable memory cell has a built-in set/reset functionality!
+
+- An internal protection circuitry to ensure clean signals at all the SOC I/O ports. This is to avoid
+
+ - ``SOC_OUT`` port outputs any random signal when the I/O is in input mode
+ - ``FPGA_IN`` port is driven by any random signal when the I/O is output mode
+
+- An internal configurable memory element to control the direction of I/O cell
+
+.. _fig_embedded_io_schematic:
+
+.. figure:: ./figures/embedded_io_schematic.png
+ :scale: 30%
+ :alt: Schematic of embedded I/O cell used in FPGA
+
+ Schematic of embedded I/O cell used in FPGA
+
diff --git a/HDL/common/digital_io_behavorial.v b/HDL/common/digital_io_behavorial.v
new file mode 100644
index 0000000..18c50bc
--- /dev/null
+++ b/HDL/common/digital_io_behavorial.v
@@ -0,0 +1,46 @@
+//-----------------------------------------------------
+// This file includes behavorial modeling
+// for digital I/O cells
+// These cells may not be directly used for physical design
+// Synthesis tools may be needed
+//-----------------------------------------------------
+`timescale 1ns/1ps
+
+//-----------------------------------------------------
+// Function : A minimum input pad
+//-----------------------------------------------------
+module GPIN (
+ inout A, // External PAD signal
+ output Y // Data input
+);
+ assign Y = A;
+endmodule
+
+//-----------------------------------------------------
+// Function : A minimum output pad
+//-----------------------------------------------------
+module GPOUT (
+ inout Y, // External PAD signal
+ input A // Data output
+);
+ assign Y = A;
+endmodule
+
+//-----------------------------------------------------
+// Function : A minimum embedded I/O
+// just an overlay to interface other components
+//-----------------------------------------------------
+module EMBEDDED_IO (
+ input SOC_IN, // Input to drive the inpad signal
+ output SOC_OUT, // Output the outpad signal
+ output SOC_DIR, // Output the directionality
+ output FPGA_IN, // Input data to FPGA
+ input FPGA_OUT, // Output data from FPGA
+ input FPGA_DIR // direction control
+);
+
+ assign FPGA_IN = SOC_IN;
+ assign SOC_OUT = FPGA_OUT;
+ assign SOC_DIR = FPGA_DIR;
+endmodule
+
diff --git a/HDL/common/digital_io_hd.v b/HDL/common/digital_io_hd.v
index a5ba600..c626404 100644
--- a/HDL/common/digital_io_hd.v
+++ b/HDL/common/digital_io_hd.v
@@ -1,57 +1,52 @@
`timescale 1ns/1ps
-module GPIO (A, IE, OE, Y, in, out, mem_out);
- output A;
- output IE;
- output OE;
- output Y;
- input in;
- output out;
- input mem_out;
-
- assign A = in;
- assign out = Y;
- assign IE = mem_out;
- sky130_fd_sc_hd__inv_1 ie_oe_inv (
- .A (mem_out),
- .Y (OE) );
-endmodule
-
//-----------------------------------------------------
-// Function : A minimum input pad
+// Function : An embedded I/O with
+// - An I/O isolation signal to set
+// the I/O in input mode. This is to avoid
+// any unexpected output signals to damage
+// circuits outside the FPGA due to configurable
+// memories are not properly initialized
+// This feature may not be needed if the configurable
+// memory cell has a built-in set/reset functionality
+// - Internal protection circuitry to ensure
+// clean signals at all the SOC I/O ports
+// This is to avoid
+// - output any random signal
+// when the I/O is in input mode, also avoid
+// - driven by any random signal
+// when the I/O is output mode
+//
+// Note: This cell is built with Standard Cells from HD library
+// It is already technology mapped and can be directly used
+// for physical design
//-----------------------------------------------------
-module GPIN (
- inout A, // External PAD signal
- output Y // Data input
-);
- assign Y = A;
-endmodule
-
-//-----------------------------------------------------
-// Function : A minimum output pad
-//-----------------------------------------------------
-module GPOUT (
- inout Y, // External PAD signal
- input A // Data output
-);
- assign Y = A;
-endmodule
-
-//-----------------------------------------------------
-// Function : A minimum embedded I/O
-// just an overlay to interface other components
-//-----------------------------------------------------
-module EMBEDDED_IO (
- input SOC_IN, // Input to drive the inpad signal
+module EMBEDDED_IO_HD (
+ input SOC_IN, // Input to drive the inpad signal
output SOC_OUT, // Output the outpad signal
output SOC_DIR, // Output the directionality
output FPGA_IN, // Input data to FPGA
input FPGA_OUT, // Output data from FPGA
- input FPGA_DIR // direction control
+ input FPGA_DIR, // direction control
+ input IO_ISOL_N // Isolation enable signal
);
- assign FPGA_IN = SOC_IN;
- assign SOC_OUT = FPGA_OUT;
- assign SOC_DIR = FPGA_DIR;
+ sky130_fd_sc_hd__and2_0 ISOL_EN_GATE (.A(IO_ISOL_N),
+ .B(FPGA_DIR),
+ .X(SOC_DIR)
+ );
+
+ // Use drive-strength 2 for a high fan-out from global routing architecture
+ sky130_fd_sc_hd__and2_2 IN_PROTECT_GATE (.A(SOC_DIR),
+ .B(SOC_IN),
+ .X(FPGA_IN)
+ );
+
+ // Use drive-strength 1 for a potential high fan-out from SoC components
+ sky130_fd_sc_hd__and2b_1 OUT_PROTECT_GATE (.A_N(SOC_DIR),
+ .B(FPGA_OUT),
+ .X(SOC_OUT)
+ );
+
endmodule