mirror of https://github.com/lnis-uofu/SOFA.git
[MSIM] Now modelsim verification is multithreaded
This commit is contained in:
tangxifan
parent
67e0c94c66
commit
2f741ecc15
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@ -16,6 +16,8 @@ import argparse
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import logging
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import subprocess
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import glob
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import threading
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import run_post_pnr_msim_test
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#####################################################################
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# Initialize logger
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@ -64,15 +66,16 @@ num_sim_finished = 0
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msim_testrun_script_abspath = os.path.abspath(__file__)
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msim_testrun_script_abspath = re.sub(os.path.basename(msim_testrun_script_abspath), "run_post_pnr_msim_test.py", msim_testrun_script_abspath)
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threads = []
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for testbench_file in testbench_files:
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# Find testbench name
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testbench_name = re.findall("(\w+)_include_netlists.v", os.path.basename(testbench_file))[0]
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cmd = "python3 " + msim_testrun_script_abspath \
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+ " --verilog_testbench " + testbench_file \
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+ " --project_path " + msim_task_dir_abspath + "/" + testbench_name \
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+ " --testbench_name " + testbench_name + "_autocheck_top_tb"
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subprocess.run(cmd, shell=True, check=True)
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num_sim_finished += 1
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process = threading.Thread(target=run_post_pnr_msim_test.run_msim, args=(testbench_file, msim_task_dir_abspath + "/" + testbench_name, testbench_name + "_autocheck_top_tb",))
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process.start()
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threads.append(process)
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for process in threads:
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process.join()
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logging.info("Done")
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logging.info("Finish " + str(num_sim_finished) + " ModelSim simulations")
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logging.info("Finish " + str(len(threads)) + " ModelSim simulations")
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@ -6,6 +6,7 @@
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# - Analyze output log files and return succeed or failure
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#####################################################################
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import sys
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import os
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from os.path import dirname, abspath, isfile
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import shutil
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@ -18,138 +19,150 @@ import subprocess
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# Initialize logger
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#####################################################################
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logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.INFO)
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#####################################################################
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# Main function of this script, so that it can be called by other scripts
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#####################################################################
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def main(args):
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#####################################################################
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# Parse the options
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#####################################################################
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parser = argparse.ArgumentParser(description='Run ModelSim verification for a testbench')
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parser.add_argument('--verilog_testbench', required=True,
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help='Specify the file path for the Verilog testbench as input')
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parser.add_argument('--project_path', required=True,
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help='Specify the file path to create the ModelSim project')
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parser.add_argument('--testbench_name', required=True,
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help='Specify the top-level module of the testbench')
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args = parser.parse_args(args)
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run_msim(args.verilog_testbench, args.project_path, args.testbench_name)
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#####################################################################
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# Parse the options
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# Main function of this script, so that it can be called by other scripts
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#####################################################################
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parser = argparse.ArgumentParser(description='Run ModelSim verification for a testbench')
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parser.add_argument('--verilog_testbench', required=True,
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help='Specify the file path for the Verilog testbench as input')
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parser.add_argument('--project_path', required=True,
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help='Specify the file path to create the ModelSim project')
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parser.add_argument('--testbench_name', required=True,
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help='Specify the top-level module of the testbench')
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args = parser.parse_args()
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def run_msim(verilog_testbench, project_path, testbench_name):
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#####################################################################
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# Check options:
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# - Input testbench file must be valid
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# Otherwise, error out
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# - If the modelsim project path does not exist, create it
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#####################################################################
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if not isfile(verilog_testbench):
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logging.error("Invalid Verilog testbench: " + verilog_testbench + "\nFile does not exist!\n")
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exit(1)
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project_abs_path = os.path.abspath(project_path)
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if not os.path.isdir(project_abs_path):
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logging.debug("Creating ModelSim project directory : " + project_abs_path + " ...\n")
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os.makedirs(project_abs_path, exist_ok=True)
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logging.debug("Done\n")
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#####################################################################
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# Create the Tcl script for Modelsim
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#####################################################################
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# Get modelsim process tcl file path
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msim_proc_tcl_path = os.path.abspath(__file__)
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msim_proc_tcl_path = re.sub(os.path.basename(msim_proc_tcl_path), "modelsim_proc.tcl", msim_proc_tcl_path)
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if not isfile(msim_proc_tcl_path):
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logging.error("Invalid process script for ModelSim: " + msim_proc_tcl_path + "\nFile does not exist!\n")
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exit(1)
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# Create output file handler
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tcl_file_path = project_abs_path + "/" + os.path.basename(testbench_name) + ".tcl"
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logging.debug("Generating Tcl script for ModelSim: " + tcl_file_path)
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tcl_file = open(tcl_file_path, "w")
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# A string buffer to write tcl content
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tcl_lines = []
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tcl_lines.append("echo \"==============================\"")
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tcl_lines.append("pwd")
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tcl_lines.append("echo \"==============================\"")
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tcl_lines.append("\n")
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tcl_lines.append("set project_name " + testbench_name)
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tcl_lines.append("set top_tb " + testbench_name)
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tcl_lines.append("\n")
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tcl_lines.append("set project_path \"" + project_abs_path + "\"")
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tcl_lines.append("set verilog_files \"" + os.path.abspath(verilog_testbench) + "\"")
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tcl_lines.append("\n")
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tcl_lines.append("source " + msim_proc_tcl_path)
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tcl_lines.append("\n")
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tcl_lines.append("try {")
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tcl_lines.append("\ttop_create_new_project $project_name $verilog_files $project_path $top_tb")
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tcl_lines.append("} finally {")
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tcl_lines.append("\tquit")
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tcl_lines.append("}")
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for line in tcl_lines:
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tcl_file.write(line + "\n")
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tcl_file.close()
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logging.debug("Done")
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#####################################################################
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# Run ModelSim simulation
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#####################################################################
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curr_dir = os.getcwd()
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# Change to the project directory
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os.chdir(project_abs_path)
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logging.debug("Changed to directory: " + project_abs_path)
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# Run ModelSim
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vsim_log_file_path = project_abs_path + "/vsim_run_log"
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vsim_bin = "/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/bin/vsim"
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vsim_cmd = vsim_bin + " -c -do " + os.path.abspath(tcl_file_path) + " > " + vsim_log_file_path
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logging.debug("Running modelsim by : " + vsim_cmd)
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subprocess.run(vsim_cmd, shell=True, check=True)
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# Go back to current directory
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os.chdir(curr_dir)
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#####################################################################
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# Parse log files and report any errors
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#####################################################################
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vsim_log_file = open(vsim_log_file_path, "r")
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# Error counter
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num_err = 0
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num_err_lines_found = 0
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verification_passed = False
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for line in vsim_log_file:
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# Check errors from self-testing testbench output
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if line.startswith("# Simulation finish with") :
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num_sim_err = int(re.findall("# Simulation finish with(\s+)(\d+) errors", line)[0][1])
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num_err_lines_found += 1
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if (0 < num_sim_err) :
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logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n")
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# Add to total errors
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num_err += num_sim_err
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if line.startswith("# Simulation Failed with") :
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print (line)
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num_sim_err = int(re.findall("# Simulation Failed with(\s+)(\d+) error\(s\)", line)[0][1])
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num_err_lines_found += 1
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if (0 < num_sim_err) :
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logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n")
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# Add to total errors
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num_err += num_sim_err
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# Check total errors by Modelsim
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if line.startswith("# Errors:") :
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num_msim_err = int(re.findall("# Errors:(\s)(\d+),", line)[0][1])
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num_err_lines_found += 1
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num_err += num_msim_err
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vsim_log_file.close()
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if (0 == num_err_lines_found) :
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logging.error("No error lines found!Something wrong in setting up modelsim simulation\n")
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elif (0 < num_err) :
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logging.error("ModelSim failed with " + str(num_err) + " errors!\n")
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else :
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verification_passed = True
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if (verification_passed) :
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logging.info(testbench_name + "...[Passed]\n")
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else :
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logging.error(testbench_name + "...[Failed]\n")
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#####################################################################
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# Check options:
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# - Input testbench file must be valid
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# Otherwise, error out
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# - If the modelsim project path does not exist, create it
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#####################################################################
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if not isfile(args.verilog_testbench):
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logging.error("Invalid Verilog testbench: " + args.verilog_testbench + "\nFile does not exist!\n")
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exit(1)
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project_abs_path = os.path.abspath(args.project_path)
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if not os.path.isdir(project_abs_path):
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logging.debug("Creating ModelSim project directory : " + project_abs_path + " ...\n")
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os.makedirs(project_abs_path, exist_ok=True)
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logging.debug("Done\n")
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#####################################################################
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# Create the Tcl script for Modelsim
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#####################################################################
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# Get modelsim process tcl file path
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msim_proc_tcl_path = os.path.abspath(__file__)
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msim_proc_tcl_path = re.sub(os.path.basename(msim_proc_tcl_path), "modelsim_proc.tcl", msim_proc_tcl_path)
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if not isfile(msim_proc_tcl_path):
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logging.error("Invalid process script for ModelSim: " + msim_proc_tcl_path + "\nFile does not exist!\n")
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exit(1)
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# Create output file handler
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tcl_file_path = project_abs_path + "/" + os.path.basename(args.testbench_name) + ".tcl"
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logging.debug("Generating Tcl script for ModelSim: " + tcl_file_path)
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tcl_file = open(tcl_file_path, "w")
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# A string buffer to write tcl content
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tcl_lines = []
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tcl_lines.append("echo \"==============================\"")
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tcl_lines.append("pwd")
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tcl_lines.append("echo \"==============================\"")
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tcl_lines.append("\n")
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tcl_lines.append("set project_name " + args.testbench_name)
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tcl_lines.append("set top_tb " + args.testbench_name)
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tcl_lines.append("\n")
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tcl_lines.append("set project_path \"" + project_abs_path + "\"")
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tcl_lines.append("set verilog_files \"" + os.path.abspath(args.verilog_testbench) + "\"")
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tcl_lines.append("\n")
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tcl_lines.append("source " + msim_proc_tcl_path)
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tcl_lines.append("\n")
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tcl_lines.append("try {")
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tcl_lines.append("\ttop_create_new_project $project_name $verilog_files $project_path $top_tb")
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tcl_lines.append("} finally {")
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tcl_lines.append("\tquit")
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tcl_lines.append("}")
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for line in tcl_lines:
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tcl_file.write(line + "\n")
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tcl_file.close()
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logging.debug("Done")
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#####################################################################
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# Run ModelSim simulation
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#####################################################################
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curr_dir = os.getcwd()
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# Change to the project directory
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os.chdir(project_abs_path)
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logging.debug("Changed to directory: " + project_abs_path)
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# Run ModelSim
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vsim_log_file_path = project_abs_path + "/vsim_run_log"
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vsim_bin = "/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/bin/vsim"
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vsim_cmd = vsim_bin + " -c -do " + os.path.abspath(tcl_file_path) + " > " + vsim_log_file_path
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logging.debug("Running modelsim by : " + vsim_cmd)
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subprocess.run(vsim_cmd, shell=True, check=True)
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# Go back to current directory
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os.chdir(curr_dir)
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#####################################################################
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# Parse log files and report any errors
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#####################################################################
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vsim_log_file = open(vsim_log_file_path, "r")
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# Error counter
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num_err = 0
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num_err_lines_found = 0
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verification_passed = False
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for line in vsim_log_file:
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# Check errors from self-testing testbench output
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if line.startswith("# Simulation finish with") :
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num_sim_err = int(re.findall("# Simulation finish with(\s+)(\d+) errors", line)[0][1])
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num_err_lines_found += 1
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if (0 < num_sim_err) :
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logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n")
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# Add to total errors
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num_err += num_sim_err
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if line.startswith("# Simulation Failed with") :
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print (line)
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num_sim_err = int(re.findall("# Simulation Failed with(\s+)(\d+) error\(s\)", line)[0][1])
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num_err_lines_found += 1
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if (0 < num_sim_err) :
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logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n")
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# Add to total errors
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num_err += num_sim_err
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# Check total errors by Modelsim
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if line.startswith("# Errors:") :
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num_msim_err = int(re.findall("# Errors:(\s)(\d+),", line)[0][1])
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num_err_lines_found += 1
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num_err += num_msim_err
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vsim_log_file.close()
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if (0 == num_err_lines_found) :
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logging.error("No error lines found!Something wrong in setting up modelsim simulation\n")
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elif (0 < num_err) :
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logging.error("ModelSim failed with " + str(num_err) + " errors!\n")
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else :
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verification_passed = True
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if (verification_passed) :
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logging.info(args.testbench_name + "...[Passed]\n")
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else :
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logging.error(args.testbench_name + "...[Failed]\n")
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if __name__ == "__main__":
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main(sys.argv[1:])
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