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SOFA
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Merge branch 'master' into ganesh_dev

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ganeshgore 2021-04-06 22:31:40 -06:00 committed by GitHub
parent f4b5080c0c b653f4ef82
commit 2f4005cde9
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2 changed files with 56 additions and 18 deletions
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54
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task_benchmarks.conf Normal file
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@ -0,0 +1,54 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=60
[ARCHITECTURES]
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS]
bench0=${PATH:TASK_DIR}/BENCHMARK/and2/and2.v
bench1=${PATH:TASK_DIR}/BENCHMARK/and2_latch/and2_latch.v
bench2=${PATH:TASK_DIR}/BENCHMARK/bin2bcd/bin2bcd.v
bench3=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
bench4=${PATH:TASK_DIR}/BENCHMARK/routing_test/routing_test.v
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5=${PATH:TASK_DIR}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
bench6=${PATH:TASK_DIR}/BENCHMARK/simon_bit_serial/rtl/*.v
bench7=${PATH:TASK_DIR}/BENCHMARK/and2_or2/and2_or2.v
[SYNTHESIS_PARAM]
bench0_top = and2
bench1_top = and2_latch
bench2_top = bin2bcd
bench3_top = counter
bench4_top = routing_test
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5_top = rs_decoder_top
bench6_top = top_module
bench7_top = and2_or2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=

20
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task_simulation.conf
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@ -29,26 +29,10 @@ openfpga_vpr_route_chan_width=60
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS]
bench0=${PATH:TASK_DIR}/BENCHMARK/and2/and2.v
bench1=${PATH:TASK_DIR}/BENCHMARK/and2_latch/and2_latch.v
bench2=${PATH:TASK_DIR}/BENCHMARK/bin2bcd/bin2bcd.v
bench3=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
bench4=${PATH:TASK_DIR}/BENCHMARK/routing_test/routing_test.v
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5=${PATH:TASK_DIR}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
bench6=${PATH:TASK_DIR}/BENCHMARK/simon_bit_serial/rtl/*.v
bench7=${PATH:TASK_DIR}/BENCHMARK/and2_or2/and2_or2.v
bench0=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
[SYNTHESIS_PARAM]
bench0_top = and2
bench1_top = and2_latch
bench2_top = bin2bcd
bench3_top = counter
bench4_top = routing_test
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5_top = rs_decoder_top
bench6_top = top_module
bench7_top = and2_or2
bench0_top = counter
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=