diff --git a/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.png b/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.png
index fa97946..f234225 100644
Binary files a/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.png and b/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.png differ
diff --git a/DOC/source/arch/figures/fpga_io_map_wishbone_mode.png b/DOC/source/arch/figures/fpga_io_map_wishbone_mode.png
index daf6652..ac02459 100644
Binary files a/DOC/source/arch/figures/fpga_io_map_wishbone_mode.png and b/DOC/source/arch/figures/fpga_io_map_wishbone_mode.png differ
diff --git a/DOC/source/arch/figures/fpga_io_switch.png b/DOC/source/arch/figures/fpga_io_switch.png
index f01d04b..542dee3 100644
Binary files a/DOC/source/arch/figures/fpga_io_switch.png and b/DOC/source/arch/figures/fpga_io_switch.png differ
diff --git a/DOC/source/arch/io_resource.rst b/DOC/source/arch/io_resource.rst
index 9b29a08..a693225 100644
--- a/DOC/source/arch/io_resource.rst
+++ b/DOC/source/arch/io_resource.rst
@@ -12,11 +12,11 @@ The *High-Density* (HD) FPGA IP has 144 I/O pins as shown in :numref:`fig_fpga_i
 
 Among the 144 I/Os, 
 
-- **30 external I/Os** are accessible through the Caravel SoC's *General-Purpose I/Os* (GPIOs).
+- **29 external I/Os** are accessible through the Caravel SoC's *General-Purpose I/Os* (GPIOs).
 
-- **114 internal I/Os** are accessible through the Caravel SOC's logic analyzer and wishbone interfaces, which are controlled by the RISC-V processor. See :ref:`io_resource_debug` and :ref:`io_resource_accelerator` for details. 
+- **115 internal I/Os** are accessible through the Caravel SOC's logic analyzer and wishbone interfaces, which are controlled by the RISC-V processor. See :ref:`io_resource_debug` and :ref:`io_resource_accelerator` for details. 
 
-.. note:: The connectivity of the 114 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes. 
+.. note:: The connectivity of the 115 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes. 
 
 .. _fig_fpga_io_switch:
 
@@ -35,7 +35,7 @@ Accelerator Mode
 When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor.
 :numref:`fig_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations. 
 
-.. note:: Not all the 114 internal I/Os are used by the Wishbone interface. Especially, the I/O[122:131] are not connected.
+.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[122:131] are not connected.
 
 .. warning:: The FPGA does not contain a Wishbone slave IP. Users have to implement a soft Wishbone slave when use the FPGA as an accelerator.
 
@@ -55,7 +55,7 @@ Debug Mode
 When the logic analyzer interface is enabled, the FPGA can operate in debug mode, whose internal signals can be readback through the registers of the RISC-V processor.
 :numref:`fig_fpga_io_map_logic_analyzer_mode` illustrates the detailed I/O arrangement for the FPGA, where the logic analyzer signals are connected to fixed FPGA I/O locations. 
 
-.. note:: The logic analyzer is 128-bit, while 114 bits can drive or be driven by the FPGA I/O. The other 14 bits are connected to internal spots of the FPGA fabric, monitoring critical signal activities of the FPGA in debugging purpose.
+.. note:: The logic analyzer is 128-bit, while 115 bits can drive or be driven by the FPGA I/O. The other 14 bits are connected to internal spots of the FPGA fabric, monitoring critical signal activities of the FPGA in debugging purpose.
 
 .. _fig_fpga_io_map_logic_analyzer_mode:
 
diff --git a/DOC/source/device/dc_ac_character.rst b/DOC/source/device/dc_ac_character.rst
index 6b22aee..1e7b3b2 100644
--- a/DOC/source/device/dc_ac_character.rst
+++ b/DOC/source/device/dc_ac_character.rst
@@ -13,7 +13,7 @@ I/O usage and port information
   +-----------+------------------------------------------------------------------------+-------------+
   | I/O Type  | Description                                                            | No. of Pins |
   +===========+========================================================================+=============+
-  | Data I/O  | Datapath I/Os of FPGA fabric                                           | 30          |
+  | Data I/O  | Datapath I/Os of FPGA fabric                                           | 29          |
   +-----------+------------------------------------------------------------------------+-------------+
   | Clk       | Operating clock of FPGA core                                           | 1           |
   +-----------+------------------------------------------------------------------------+-------------+
@@ -29,6 +29,8 @@ I/O usage and port information
   +-----------+------------------------------------------------------------------------+-------------+
   | SCout     | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1           |
   +-----------+------------------------------------------------------------------------+-------------+
+  | IO_ISLO_N | Active-low signal to enable I/O datapath isolation from external ports | 1           |
+  +-----------+------------------------------------------------------------------------+-------------+
   | Total     |                                                                        | 37          |
   +-----------+------------------------------------------------------------------------+-------------+