From 2aa8f8142135abeb411f9ee4ec8892699801a82c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 30 Nov 2020 21:25:02 -0700 Subject: [PATCH] [CI] Add more tests --- .github/workflows/quick_test.sh | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/.github/workflows/quick_test.sh b/.github/workflows/quick_test.sh index c1ba391..0f953d9 100755 --- a/.github/workflows/quick_test.sh +++ b/.github/workflows/quick_test.sh @@ -5,4 +5,16 @@ set -e ############################################### # OpenFPGA Shell with VPR8 ############################################## + +############################################## +# Initialize the repository +# - Generate final version of architecture files +# - Run FPGA tasks to validate netlist generations python3 SCRIPT/repo_setup.py --openfpga_root_path ./OpenFPGA + +############################################## +# Generate post-PnR testbenches +python3 generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.0.json +python3 generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.1.json +python3 generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.0.json +python3 generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.1.json