diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga
index 8b7f99a..f2e45ea 100644
--- a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga
+++ b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga
@@ -54,6 +54,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_verilog_testbench --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/verilog_testbench \
+  --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} \
   --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
   --print_top_testbench \
   --print_preconfig_top_testbench \
diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_testbench/config/task_template.conf
index 11170b0..ae0ece2 100644
--- a/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_testbench/config/task_template.conf
+++ b/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_testbench/config/task_template.conf
@@ -22,6 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
 openfpga_vpr_device_layout=2x2
 openfpga_vpr_route_chan_width=40
 openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_FPGA_2x2_fdms_cc
+openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_FPGA_2x2_fdms_cc/SRC/fabric_netlists.v
 
 [ARCHITECTURES]
 arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml
diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_ndafdms_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_ndafdms_2x2/generate_testbench/config/task_template.conf
index 5ee6b6b..0315787 100644
--- a/SCRIPT/skywater_openfpga_task/k4_cc_ndafdms_2x2/generate_testbench/config/task_template.conf
+++ b/SCRIPT/skywater_openfpga_task/k4_cc_ndafdms_2x2/generate_testbench/config/task_template.conf
@@ -22,6 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
 openfpga_vpr_device_layout=2x2
 openfpga_vpr_route_chan_width=40
 openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_FPGA_2x2_ndafdms_cc
+openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_FPGA_2x2_fdms_cc/SRC/fabric_netlists.v
 
 [ARCHITECTURES]
 arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml