mirror of https://github.com/lnis-uofu/SOFA.git
Fixed scan-chain connections
This commit is contained in:
Ganesh Gore
parent
31a73a42ba
commit
229b8e22b4
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@ -1,43 +1,48 @@
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commit 48b2bff0d909e2c6d0740d2a5386123eb238349f
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commit 55f7a2c187139d471143f91dc368bb1497e2eb78
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Merge: 1f3e656f 93e7107d
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Author: Laboratory for Nano Integrated Systems (LNIS) <40280375+LNIS-Projects@users.noreply.github.com>
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Date: Wed Nov 4 21:55:37 2020 -0700
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Merge pull request #116 from LNIS-Projects/dev
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Extended I/O Support for SoC I/O interface
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commit 93e7107d800259ad9031c6b5d4572e8a971c6403
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Author: tangxifan <tangxifan@gmail.com>
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Date: Sun Sep 27 20:08:11 2020 -0600
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Date: Wed Nov 4 20:59:34 2020 -0700
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[OpenFPGA Tool] Update fabric key data structure to support regions
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[Test] Add new test to CI
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commit bbdea4a46b7aadd8a6f0fc45abdd39d1cc6d3057
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commit bce8233019cec3b7f778befd9457c9c637b05c6c
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Author: tangxifan <tangxifan@gmail.com>
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Date: Sun Sep 27 19:23:13 2020 -0600
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Date: Wed Nov 4 20:58:58 2020 -0700
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[Regression Test] Remove out-of-update sub modules
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[Arch] Bug fix in caravel arch
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commit e95eacfbd9ec5e8d9aecab7572d4bad5265d9590
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Merge: 32c43ffb 94047037
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commit 6b48ee7f0bd6c86181cdbbb468c4cf8e7af5c4c6
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Author: tangxifan <tangxifan@gmail.com>
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Date: Sun Sep 27 17:01:57 2020 -0600
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Date: Wed Nov 4 20:58:40 2020 -0700
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Merge branch 'dev' into ganesh_dev
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[Test] Add new test for caravel io support
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commit 94047037c570b6a432fea8f363a5147df9bc918d
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commit c85edb4738a24c394b5eeefb08586da7bd4ead6a
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Author: tangxifan <tangxifan@gmail.com>
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Date: Sun Sep 27 14:33:14 2020 -0600
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Date: Wed Nov 4 20:52:47 2020 -0700
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[OpenFPGA Tool] Streamline codes in openfpga arch parser
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commit 94a1324f0527276546c3b2571b1a1b7700a473f7
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Author: tangxifan <tangxifan@gmail.com>
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Date: Sat Sep 26 14:31:57 2020 -0600
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[Documentation] Remove deprecated XML syntax
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On branch dev
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Your branch is up to date with 'origin/dev'.
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[Arch] Bug fix for embedded io arch
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On branch master
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Your branch is up to date with 'origin/master'.
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Untracked files:
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(use "git add <file>..." to include in what will be committed)
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openfpga/openfpga
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openfpga_flow/tasks/FPGA1212_FC_HD_SKY_task
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openfpga_flow/tasks/FPGA1212_HIER_SKY_SC_MS_task
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openfpga_flow/tasks/FPGA128128_FLAT_task
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openfpga_flow/tasks/FPGA1616_FLAT_task
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openfpga_flow/tasks/FPGA22_FLAT_task
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openfpga_flow/tasks/FPGA22_FRAME_task
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openfpga_flow/tasks/FPGA22_HIER_SKY_SC_MS_task
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openfpga_flow/tasks/FPGA22_HIER_SKY_task
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openfpga_flow/tasks/FPGA22_HIER_task
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openfpga_flow/tasks/FPGA22_MB_task
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@ -1,18 +1,17 @@
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module fpga_core
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(
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input [0:0] prog_clk,
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input [0:0] Test_en,
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input [0:0] clk,
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input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN,
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output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT,
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output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR,
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input [0:0] ccff_head,
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output [0:0] ccff_tail,
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input sc_head,
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output sc_tail
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);
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( prog_clk, Test_en, clk, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, ccff_head, ccff_tail, sc_head, sc_tail );
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input [0:0] prog_clk;
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input [0:0] Test_en;
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input [0:0] clk;
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input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN;
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output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT;
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output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR;
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input [0:0] ccff_head;
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output [0:0] ccff_tail;
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input sc_head;
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output sc_tail;
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wire [0:0] cbx_1__0__0_bottom_grid_pin_0_;
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wire [0:0] cbx_1__0__0_bottom_grid_pin_10_;
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@ -425,8 +424,6 @@ module fpga_core
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wire [0:19] sb_2__2__0_chanx_left_out;
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wire [0:19] sb_2__2__0_chany_bottom_out;
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wire [1:0] UNCONN;
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wire [2:0] sc_out_wires;
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wire [2:0] sc_in_wires;
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wire [12:0] scff_Wires;
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grid_clb
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@ -434,7 +431,6 @@ module fpga_core
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(
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.SC_OUT_BOT(scff_Wires[5]),
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.SC_IN_TOP(scff_Wires[3]),
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.top_width_0_height_0__pin_33_(sc_in_wires[0]),
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.prog_clk(prog_clk[0]),
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.Test_en(Test_en[0]),
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.clk(clk[0]),
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@ -506,7 +502,6 @@ module fpga_core
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.right_width_0_height_0__pin_49_upper(grid_clb_0_right_width_0_height_0__pin_49_upper[0]),
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.right_width_0_height_0__pin_49_lower(grid_clb_0_right_width_0_height_0__pin_49_lower[0]),
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.bottom_width_0_height_0__pin_50_(grid_clb_0_bottom_width_0_height_0__pin_50_[0]),
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.bottom_width_0_height_0__pin_51_(grid_clb_0_bottom_width_0_height_0__pin_51_[0]),
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.ccff_tail(grid_clb_0_ccff_tail[0])
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);
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@ -516,7 +511,6 @@ module fpga_core
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(
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.SC_OUT_BOT(scff_Wires[2]),
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.SC_IN_TOP(scff_Wires[1]),
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.bottom_width_0_height_0__pin_51_(sc_out_wires[0]),
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.prog_clk(prog_clk[0]),
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.Test_en(Test_en[0]),
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.clk(clk[0]),
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@ -537,7 +531,6 @@ module fpga_core
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.top_width_0_height_0__pin_14_(cbx_1__2__0_bottom_grid_pin_14_[0]),
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.top_width_0_height_0__pin_15_(cbx_1__2__0_bottom_grid_pin_15_[0]),
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.top_width_0_height_0__pin_32_(grid_clb_1__2__undriven_top_width_0_height_0__pin_32_[0]),
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.top_width_0_height_0__pin_33_(grid_clb_1__2__undriven_top_width_0_height_0__pin_33_[0]),
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.right_width_0_height_0__pin_16_(cby_1__1__1_left_grid_pin_16_[0]),
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.right_width_0_height_0__pin_17_(cby_1__1__1_left_grid_pin_17_[0]),
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.right_width_0_height_0__pin_18_(cby_1__1__1_left_grid_pin_18_[0]),
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@ -598,7 +591,6 @@ module fpga_core
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(
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.SC_OUT_TOP(scff_Wires[9]),
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.SC_IN_BOT(scff_Wires[8]),
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.top_width_0_height_0__pin_33_(sc_in_wires[1]),
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.prog_clk(prog_clk[0]),
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.Test_en(Test_en[0]),
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.clk(clk[0]),
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@ -670,7 +662,6 @@ module fpga_core
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.right_width_0_height_0__pin_49_upper(grid_clb_2_right_width_0_height_0__pin_49_upper[0]),
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.right_width_0_height_0__pin_49_lower(grid_clb_2_right_width_0_height_0__pin_49_lower[0]),
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.bottom_width_0_height_0__pin_50_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_[0]),
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.bottom_width_0_height_0__pin_51_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_[0]),
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.ccff_tail(grid_clb_2_ccff_tail[0])
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);
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@ -680,7 +671,6 @@ module fpga_core
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(
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.SC_OUT_TOP(scff_Wires[11]),
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.SC_IN_BOT(scff_Wires[10]),
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.bottom_width_0_height_0__pin_51_(sc_out_wires[1]),
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.prog_clk(prog_clk[0]),
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.Test_en(Test_en[0]),
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.clk(clk[0]),
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@ -701,7 +691,6 @@ module fpga_core
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.top_width_0_height_0__pin_14_(cbx_1__2__1_bottom_grid_pin_14_[0]),
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.top_width_0_height_0__pin_15_(cbx_1__2__1_bottom_grid_pin_15_[0]),
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.top_width_0_height_0__pin_32_(direct_interc_2_out[0]),
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.top_width_0_height_0__pin_33_(direct_interc_5_out[0]),
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.right_width_0_height_0__pin_16_(cby_2__1__1_left_grid_pin_16_[0]),
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.right_width_0_height_0__pin_17_(cby_2__1__1_left_grid_pin_17_[0]),
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.right_width_0_height_0__pin_18_(cby_2__1__1_left_grid_pin_18_[0]),
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@ -1145,8 +1134,6 @@ module fpga_core
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(
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.SC_OUT_BOT(scff_Wires[3]),
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.SC_IN_TOP(scff_Wires[2]),
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.CLB_SC_OUT(sc_in_wires[0]),
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.CLB_SC_IN(sc_out_wires[0]),
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.prog_clk(prog_clk[0]),
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.chanx_left_in(sb_0__1__0_chanx_right_out[0:19]),
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.chanx_right_in(sb_1__1__0_chanx_left_out[0:19]),
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@ -1178,8 +1165,6 @@ module fpga_core
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(
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.SC_OUT_TOP(scff_Wires[10]),
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.SC_IN_BOT(scff_Wires[9]),
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.CLB_SC_OUT(sc_in_wires[1]),
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.CLB_SC_IN(sc_out_wires[1]),
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.prog_clk(prog_clk[0]),
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.chanx_left_in(sb_1__1__0_chanx_right_out[0:19]),
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.chanx_right_in(sb_2__1__0_chanx_left_out[0:19]),
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@ -1,86 +1,85 @@
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module grid_clb
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(
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input [0:0] prog_clk,
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input [0:0] Test_en,
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input [0:0] clk,
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input [0:0] top_width_0_height_0__pin_0_,
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input [0:0] top_width_0_height_0__pin_1_,
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input [0:0] top_width_0_height_0__pin_2_,
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input [0:0] top_width_0_height_0__pin_3_,
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input [0:0] top_width_0_height_0__pin_4_,
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input [0:0] top_width_0_height_0__pin_5_,
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input [0:0] top_width_0_height_0__pin_6_,
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input [0:0] top_width_0_height_0__pin_7_,
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input [0:0] top_width_0_height_0__pin_8_,
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input [0:0] top_width_0_height_0__pin_9_,
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input [0:0] top_width_0_height_0__pin_10_,
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input [0:0] top_width_0_height_0__pin_11_,
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input [0:0] top_width_0_height_0__pin_12_,
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input [0:0] top_width_0_height_0__pin_13_,
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input [0:0] top_width_0_height_0__pin_14_,
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input [0:0] top_width_0_height_0__pin_15_,
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input [0:0] top_width_0_height_0__pin_32_,
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input [0:0] top_width_0_height_0__pin_33_,
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input [0:0] right_width_0_height_0__pin_16_,
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input [0:0] right_width_0_height_0__pin_17_,
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input [0:0] right_width_0_height_0__pin_18_,
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input [0:0] right_width_0_height_0__pin_19_,
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input [0:0] right_width_0_height_0__pin_20_,
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input [0:0] right_width_0_height_0__pin_21_,
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input [0:0] right_width_0_height_0__pin_22_,
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input [0:0] right_width_0_height_0__pin_23_,
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input [0:0] right_width_0_height_0__pin_24_,
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input [0:0] right_width_0_height_0__pin_25_,
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input [0:0] right_width_0_height_0__pin_26_,
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input [0:0] right_width_0_height_0__pin_27_,
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input [0:0] right_width_0_height_0__pin_28_,
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input [0:0] right_width_0_height_0__pin_29_,
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input [0:0] right_width_0_height_0__pin_30_,
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input [0:0] right_width_0_height_0__pin_31_,
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input [0:0] left_width_0_height_0__pin_52_,
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input [0:0] ccff_head,
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output [0:0] top_width_0_height_0__pin_34_upper,
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output [0:0] top_width_0_height_0__pin_34_lower,
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output [0:0] top_width_0_height_0__pin_35_upper,
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output [0:0] top_width_0_height_0__pin_35_lower,
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output [0:0] top_width_0_height_0__pin_36_upper,
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output [0:0] top_width_0_height_0__pin_36_lower,
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output [0:0] top_width_0_height_0__pin_37_upper,
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output [0:0] top_width_0_height_0__pin_37_lower,
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output [0:0] top_width_0_height_0__pin_38_upper,
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output [0:0] top_width_0_height_0__pin_38_lower,
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output [0:0] top_width_0_height_0__pin_39_upper,
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output [0:0] top_width_0_height_0__pin_39_lower,
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output [0:0] top_width_0_height_0__pin_40_upper,
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output [0:0] top_width_0_height_0__pin_40_lower,
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output [0:0] top_width_0_height_0__pin_41_upper,
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output [0:0] top_width_0_height_0__pin_41_lower,
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output [0:0] right_width_0_height_0__pin_42_upper,
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output [0:0] right_width_0_height_0__pin_42_lower,
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output [0:0] right_width_0_height_0__pin_43_upper,
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output [0:0] right_width_0_height_0__pin_43_lower,
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output [0:0] right_width_0_height_0__pin_44_upper,
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output [0:0] right_width_0_height_0__pin_44_lower,
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output [0:0] right_width_0_height_0__pin_45_upper,
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output [0:0] right_width_0_height_0__pin_45_lower,
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output [0:0] right_width_0_height_0__pin_46_upper,
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output [0:0] right_width_0_height_0__pin_46_lower,
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output [0:0] right_width_0_height_0__pin_47_upper,
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output [0:0] right_width_0_height_0__pin_47_lower,
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output [0:0] right_width_0_height_0__pin_48_upper,
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output [0:0] right_width_0_height_0__pin_48_lower,
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output [0:0] right_width_0_height_0__pin_49_upper,
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output [0:0] right_width_0_height_0__pin_49_lower,
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output [0:0] bottom_width_0_height_0__pin_50_,
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output [0:0] bottom_width_0_height_0__pin_51_,
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output [0:0] ccff_tail,
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input SC_IN_TOP,
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input SC_IN_BOT,
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output SC_OUT_TOP,
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output SC_OUT_BOT
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);
|
||||
( prog_clk, Test_en, clk, top_width_0_height_0__pin_0_, top_width_0_height_0__pin_1_, top_width_0_height_0__pin_2_, top_width_0_height_0__pin_3_, top_width_0_height_0__pin_4_, top_width_0_height_0__pin_5_, top_width_0_height_0__pin_6_, top_width_0_height_0__pin_7_, top_width_0_height_0__pin_8_, top_width_0_height_0__pin_9_, top_width_0_height_0__pin_10_, top_width_0_height_0__pin_11_, top_width_0_height_0__pin_12_, top_width_0_height_0__pin_13_, top_width_0_height_0__pin_14_, top_width_0_height_0__pin_15_, top_width_0_height_0__pin_32_, top_width_0_height_0__pin_33_, right_width_0_height_0__pin_16_, right_width_0_height_0__pin_17_, right_width_0_height_0__pin_18_, right_width_0_height_0__pin_19_, right_width_0_height_0__pin_20_, right_width_0_height_0__pin_21_, right_width_0_height_0__pin_22_, right_width_0_height_0__pin_23_, right_width_0_height_0__pin_24_, right_width_0_height_0__pin_25_, right_width_0_height_0__pin_26_, right_width_0_height_0__pin_27_, right_width_0_height_0__pin_28_, right_width_0_height_0__pin_29_, right_width_0_height_0__pin_30_, right_width_0_height_0__pin_31_, left_width_0_height_0__pin_52_, ccff_head, top_width_0_height_0__pin_34_upper, top_width_0_height_0__pin_34_lower, top_width_0_height_0__pin_35_upper, top_width_0_height_0__pin_35_lower, top_width_0_height_0__pin_36_upper, top_width_0_height_0__pin_36_lower, top_width_0_height_0__pin_37_upper, top_width_0_height_0__pin_37_lower, top_width_0_height_0__pin_38_upper, top_width_0_height_0__pin_38_lower, top_width_0_height_0__pin_39_upper, top_width_0_height_0__pin_39_lower, top_width_0_height_0__pin_40_upper, top_width_0_height_0__pin_40_lower, top_width_0_height_0__pin_41_upper, top_width_0_height_0__pin_41_lower, right_width_0_height_0__pin_42_upper, right_width_0_height_0__pin_42_lower, right_width_0_height_0__pin_43_upper, right_width_0_height_0__pin_43_lower, right_width_0_height_0__pin_44_upper, right_width_0_height_0__pin_44_lower, right_width_0_height_0__pin_45_upper, right_width_0_height_0__pin_45_lower, right_width_0_height_0__pin_46_upper, right_width_0_height_0__pin_46_lower, right_width_0_height_0__pin_47_upper, right_width_0_height_0__pin_47_lower, right_width_0_height_0__pin_48_upper, right_width_0_height_0__pin_48_lower, right_width_0_height_0__pin_49_upper, right_width_0_height_0__pin_49_lower, bottom_width_0_height_0__pin_50_, bottom_width_0_height_0__pin_51_, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
|
||||
input [0:0] prog_clk;
|
||||
input [0:0] Test_en;
|
||||
input [0:0] clk;
|
||||
input [0:0] top_width_0_height_0__pin_0_;
|
||||
input [0:0] top_width_0_height_0__pin_1_;
|
||||
input [0:0] top_width_0_height_0__pin_2_;
|
||||
input [0:0] top_width_0_height_0__pin_3_;
|
||||
input [0:0] top_width_0_height_0__pin_4_;
|
||||
input [0:0] top_width_0_height_0__pin_5_;
|
||||
input [0:0] top_width_0_height_0__pin_6_;
|
||||
input [0:0] top_width_0_height_0__pin_7_;
|
||||
input [0:0] top_width_0_height_0__pin_8_;
|
||||
input [0:0] top_width_0_height_0__pin_9_;
|
||||
input [0:0] top_width_0_height_0__pin_10_;
|
||||
input [0:0] top_width_0_height_0__pin_11_;
|
||||
input [0:0] top_width_0_height_0__pin_12_;
|
||||
input [0:0] top_width_0_height_0__pin_13_;
|
||||
input [0:0] top_width_0_height_0__pin_14_;
|
||||
input [0:0] top_width_0_height_0__pin_15_;
|
||||
input [0:0] top_width_0_height_0__pin_32_;
|
||||
input [0:0] top_width_0_height_0__pin_33_;
|
||||
input [0:0] right_width_0_height_0__pin_16_;
|
||||
input [0:0] right_width_0_height_0__pin_17_;
|
||||
input [0:0] right_width_0_height_0__pin_18_;
|
||||
input [0:0] right_width_0_height_0__pin_19_;
|
||||
input [0:0] right_width_0_height_0__pin_20_;
|
||||
input [0:0] right_width_0_height_0__pin_21_;
|
||||
input [0:0] right_width_0_height_0__pin_22_;
|
||||
input [0:0] right_width_0_height_0__pin_23_;
|
||||
input [0:0] right_width_0_height_0__pin_24_;
|
||||
input [0:0] right_width_0_height_0__pin_25_;
|
||||
input [0:0] right_width_0_height_0__pin_26_;
|
||||
input [0:0] right_width_0_height_0__pin_27_;
|
||||
input [0:0] right_width_0_height_0__pin_28_;
|
||||
input [0:0] right_width_0_height_0__pin_29_;
|
||||
input [0:0] right_width_0_height_0__pin_30_;
|
||||
input [0:0] right_width_0_height_0__pin_31_;
|
||||
input [0:0] left_width_0_height_0__pin_52_;
|
||||
input [0:0] ccff_head;
|
||||
output [0:0] top_width_0_height_0__pin_34_upper;
|
||||
output [0:0] top_width_0_height_0__pin_34_lower;
|
||||
output [0:0] top_width_0_height_0__pin_35_upper;
|
||||
output [0:0] top_width_0_height_0__pin_35_lower;
|
||||
output [0:0] top_width_0_height_0__pin_36_upper;
|
||||
output [0:0] top_width_0_height_0__pin_36_lower;
|
||||
output [0:0] top_width_0_height_0__pin_37_upper;
|
||||
output [0:0] top_width_0_height_0__pin_37_lower;
|
||||
output [0:0] top_width_0_height_0__pin_38_upper;
|
||||
output [0:0] top_width_0_height_0__pin_38_lower;
|
||||
output [0:0] top_width_0_height_0__pin_39_upper;
|
||||
output [0:0] top_width_0_height_0__pin_39_lower;
|
||||
output [0:0] top_width_0_height_0__pin_40_upper;
|
||||
output [0:0] top_width_0_height_0__pin_40_lower;
|
||||
output [0:0] top_width_0_height_0__pin_41_upper;
|
||||
output [0:0] top_width_0_height_0__pin_41_lower;
|
||||
output [0:0] right_width_0_height_0__pin_42_upper;
|
||||
output [0:0] right_width_0_height_0__pin_42_lower;
|
||||
output [0:0] right_width_0_height_0__pin_43_upper;
|
||||
output [0:0] right_width_0_height_0__pin_43_lower;
|
||||
output [0:0] right_width_0_height_0__pin_44_upper;
|
||||
output [0:0] right_width_0_height_0__pin_44_lower;
|
||||
output [0:0] right_width_0_height_0__pin_45_upper;
|
||||
output [0:0] right_width_0_height_0__pin_45_lower;
|
||||
output [0:0] right_width_0_height_0__pin_46_upper;
|
||||
output [0:0] right_width_0_height_0__pin_46_lower;
|
||||
output [0:0] right_width_0_height_0__pin_47_upper;
|
||||
output [0:0] right_width_0_height_0__pin_47_lower;
|
||||
output [0:0] right_width_0_height_0__pin_48_upper;
|
||||
output [0:0] right_width_0_height_0__pin_48_lower;
|
||||
output [0:0] right_width_0_height_0__pin_49_upper;
|
||||
output [0:0] right_width_0_height_0__pin_49_lower;
|
||||
output [0:0] bottom_width_0_height_0__pin_50_;
|
||||
output [0:0] bottom_width_0_height_0__pin_51_;
|
||||
output [0:0] ccff_tail;
|
||||
input SC_IN_TOP;
|
||||
input SC_IN_BOT;
|
||||
output SC_OUT_TOP;
|
||||
output SC_OUT_BOT;
|
||||
|
||||
assign top_width_0_height_0__pin_34_lower[0] = top_width_0_height_0__pin_34_upper[0];
|
||||
assign top_width_0_height_0__pin_35_lower[0] = top_width_0_height_0__pin_35_upper[0];
|
||||
|
|
|
|||
|
|
@ -1,46 +1,45 @@
|
|||
|
||||
|
||||
module cbx_1__0_
|
||||
(
|
||||
input [0:0] prog_clk,
|
||||
input [0:19] chanx_left_in,
|
||||
input [0:19] chanx_right_in,
|
||||
input [0:0] ccff_head,
|
||||
output [0:19] chanx_left_out,
|
||||
output [0:19] chanx_right_out,
|
||||
output [0:0] bottom_grid_pin_0_,
|
||||
output [0:0] bottom_grid_pin_2_,
|
||||
output [0:0] bottom_grid_pin_4_,
|
||||
output [0:0] bottom_grid_pin_6_,
|
||||
output [0:0] bottom_grid_pin_8_,
|
||||
output [0:0] bottom_grid_pin_10_,
|
||||
output [0:0] ccff_tail,
|
||||
input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN,
|
||||
output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT,
|
||||
output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR,
|
||||
input [0:0] top_width_0_height_0__pin_0_,
|
||||
input [0:0] top_width_0_height_0__pin_2_,
|
||||
input [0:0] top_width_0_height_0__pin_4_,
|
||||
input [0:0] top_width_0_height_0__pin_6_,
|
||||
input [0:0] top_width_0_height_0__pin_8_,
|
||||
input [0:0] top_width_0_height_0__pin_10_,
|
||||
output [0:0] top_width_0_height_0__pin_1_upper,
|
||||
output [0:0] top_width_0_height_0__pin_1_lower,
|
||||
output [0:0] top_width_0_height_0__pin_3_upper,
|
||||
output [0:0] top_width_0_height_0__pin_3_lower,
|
||||
output [0:0] top_width_0_height_0__pin_5_upper,
|
||||
output [0:0] top_width_0_height_0__pin_5_lower,
|
||||
output [0:0] top_width_0_height_0__pin_7_upper,
|
||||
output [0:0] top_width_0_height_0__pin_7_lower,
|
||||
output [0:0] top_width_0_height_0__pin_9_upper,
|
||||
output [0:0] top_width_0_height_0__pin_9_lower,
|
||||
output [0:0] top_width_0_height_0__pin_11_upper,
|
||||
output [0:0] top_width_0_height_0__pin_11_lower,
|
||||
input SC_IN_TOP,
|
||||
input SC_IN_BOT,
|
||||
output SC_OUT_TOP,
|
||||
output SC_OUT_BOT
|
||||
);
|
||||
( prog_clk, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, bottom_grid_pin_0_, bottom_grid_pin_2_, bottom_grid_pin_4_, bottom_grid_pin_6_, bottom_grid_pin_8_, bottom_grid_pin_10_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, top_width_0_height_0__pin_0_, top_width_0_height_0__pin_2_, top_width_0_height_0__pin_4_, top_width_0_height_0__pin_6_, top_width_0_height_0__pin_8_, top_width_0_height_0__pin_10_, top_width_0_height_0__pin_1_upper, top_width_0_height_0__pin_1_lower, top_width_0_height_0__pin_3_upper, top_width_0_height_0__pin_3_lower, top_width_0_height_0__pin_5_upper, top_width_0_height_0__pin_5_lower, top_width_0_height_0__pin_7_upper, top_width_0_height_0__pin_7_lower, top_width_0_height_0__pin_9_upper, top_width_0_height_0__pin_9_lower, top_width_0_height_0__pin_11_upper, top_width_0_height_0__pin_11_lower, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
|
||||
input [0:0] prog_clk;
|
||||
input [0:19] chanx_left_in;
|
||||
input [0:19] chanx_right_in;
|
||||
input [0:0] ccff_head;
|
||||
output [0:19] chanx_left_out;
|
||||
output [0:19] chanx_right_out;
|
||||
output [0:0] bottom_grid_pin_0_;
|
||||
output [0:0] bottom_grid_pin_2_;
|
||||
output [0:0] bottom_grid_pin_4_;
|
||||
output [0:0] bottom_grid_pin_6_;
|
||||
output [0:0] bottom_grid_pin_8_;
|
||||
output [0:0] bottom_grid_pin_10_;
|
||||
output [0:0] ccff_tail;
|
||||
input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN;
|
||||
output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT;
|
||||
output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR;
|
||||
input [0:0] top_width_0_height_0__pin_0_;
|
||||
input [0:0] top_width_0_height_0__pin_2_;
|
||||
input [0:0] top_width_0_height_0__pin_4_;
|
||||
input [0:0] top_width_0_height_0__pin_6_;
|
||||
input [0:0] top_width_0_height_0__pin_8_;
|
||||
input [0:0] top_width_0_height_0__pin_10_;
|
||||
output [0:0] top_width_0_height_0__pin_1_upper;
|
||||
output [0:0] top_width_0_height_0__pin_1_lower;
|
||||
output [0:0] top_width_0_height_0__pin_3_upper;
|
||||
output [0:0] top_width_0_height_0__pin_3_lower;
|
||||
output [0:0] top_width_0_height_0__pin_5_upper;
|
||||
output [0:0] top_width_0_height_0__pin_5_lower;
|
||||
output [0:0] top_width_0_height_0__pin_7_upper;
|
||||
output [0:0] top_width_0_height_0__pin_7_lower;
|
||||
output [0:0] top_width_0_height_0__pin_9_upper;
|
||||
output [0:0] top_width_0_height_0__pin_9_lower;
|
||||
output [0:0] top_width_0_height_0__pin_11_upper;
|
||||
output [0:0] top_width_0_height_0__pin_11_lower;
|
||||
input SC_IN_TOP;
|
||||
input SC_IN_BOT;
|
||||
output SC_OUT_TOP;
|
||||
output SC_OUT_BOT;
|
||||
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
|
||||
|
|
|
|||
|
|
@ -1,37 +1,34 @@
|
|||
|
||||
|
||||
module cbx_1__1_
|
||||
(
|
||||
input [0:0] prog_clk,
|
||||
input [0:19] chanx_left_in,
|
||||
input [0:19] chanx_right_in,
|
||||
input [0:0] ccff_head,
|
||||
output [0:19] chanx_left_out,
|
||||
output [0:19] chanx_right_out,
|
||||
output [0:0] bottom_grid_pin_0_,
|
||||
output [0:0] bottom_grid_pin_1_,
|
||||
output [0:0] bottom_grid_pin_2_,
|
||||
output [0:0] bottom_grid_pin_3_,
|
||||
output [0:0] bottom_grid_pin_4_,
|
||||
output [0:0] bottom_grid_pin_5_,
|
||||
output [0:0] bottom_grid_pin_6_,
|
||||
output [0:0] bottom_grid_pin_7_,
|
||||
output [0:0] bottom_grid_pin_8_,
|
||||
output [0:0] bottom_grid_pin_9_,
|
||||
output [0:0] bottom_grid_pin_10_,
|
||||
output [0:0] bottom_grid_pin_11_,
|
||||
output [0:0] bottom_grid_pin_12_,
|
||||
output [0:0] bottom_grid_pin_13_,
|
||||
output [0:0] bottom_grid_pin_14_,
|
||||
output [0:0] bottom_grid_pin_15_,
|
||||
output [0:0] ccff_tail,
|
||||
input CLB_SC_IN,
|
||||
output CLB_SC_OUT,
|
||||
input SC_IN_TOP,
|
||||
input SC_IN_BOT,
|
||||
output SC_OUT_TOP,
|
||||
output SC_OUT_BOT
|
||||
);
|
||||
( prog_clk, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, bottom_grid_pin_0_, bottom_grid_pin_1_, bottom_grid_pin_2_, bottom_grid_pin_3_, bottom_grid_pin_4_, bottom_grid_pin_5_, bottom_grid_pin_6_, bottom_grid_pin_7_, bottom_grid_pin_8_, bottom_grid_pin_9_, bottom_grid_pin_10_, bottom_grid_pin_11_, bottom_grid_pin_12_, bottom_grid_pin_13_, bottom_grid_pin_14_, bottom_grid_pin_15_, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
|
||||
input [0:0] prog_clk;
|
||||
input [0:19] chanx_left_in;
|
||||
input [0:19] chanx_right_in;
|
||||
input [0:0] ccff_head;
|
||||
output [0:19] chanx_left_out;
|
||||
output [0:19] chanx_right_out;
|
||||
output [0:0] bottom_grid_pin_0_;
|
||||
output [0:0] bottom_grid_pin_1_;
|
||||
output [0:0] bottom_grid_pin_2_;
|
||||
output [0:0] bottom_grid_pin_3_;
|
||||
output [0:0] bottom_grid_pin_4_;
|
||||
output [0:0] bottom_grid_pin_5_;
|
||||
output [0:0] bottom_grid_pin_6_;
|
||||
output [0:0] bottom_grid_pin_7_;
|
||||
output [0:0] bottom_grid_pin_8_;
|
||||
output [0:0] bottom_grid_pin_9_;
|
||||
output [0:0] bottom_grid_pin_10_;
|
||||
output [0:0] bottom_grid_pin_11_;
|
||||
output [0:0] bottom_grid_pin_12_;
|
||||
output [0:0] bottom_grid_pin_13_;
|
||||
output [0:0] bottom_grid_pin_14_;
|
||||
output [0:0] bottom_grid_pin_15_;
|
||||
output [0:0] ccff_tail;
|
||||
input SC_IN_TOP;
|
||||
input SC_IN_BOT;
|
||||
output SC_OUT_TOP;
|
||||
output SC_OUT_BOT;
|
||||
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
|
||||
|
|
@ -120,7 +117,6 @@ module cbx_1__1_
|
|||
assign chanx_left_out[17] = chanx_right_in[17];
|
||||
assign chanx_left_out[18] = chanx_right_in[18];
|
||||
assign chanx_left_out[19] = chanx_right_in[19];
|
||||
assign CLB_SC_OUT = CLB_SC_IN;
|
||||
assign SC_IN_TOP = SC_IN_BOT;
|
||||
assign SC_OUT_TOP = SC_OUT_BOT;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,42 +1,41 @@
|
|||
|
||||
|
||||
module cbx_1__2_
|
||||
(
|
||||
input [0:0] prog_clk,
|
||||
input [0:19] chanx_left_in,
|
||||
input [0:19] chanx_right_in,
|
||||
input [0:0] ccff_head,
|
||||
output [0:19] chanx_left_out,
|
||||
output [0:19] chanx_right_out,
|
||||
output [0:0] top_grid_pin_0_,
|
||||
output [0:0] bottom_grid_pin_0_,
|
||||
output [0:0] bottom_grid_pin_1_,
|
||||
output [0:0] bottom_grid_pin_2_,
|
||||
output [0:0] bottom_grid_pin_3_,
|
||||
output [0:0] bottom_grid_pin_4_,
|
||||
output [0:0] bottom_grid_pin_5_,
|
||||
output [0:0] bottom_grid_pin_6_,
|
||||
output [0:0] bottom_grid_pin_7_,
|
||||
output [0:0] bottom_grid_pin_8_,
|
||||
output [0:0] bottom_grid_pin_9_,
|
||||
output [0:0] bottom_grid_pin_10_,
|
||||
output [0:0] bottom_grid_pin_11_,
|
||||
output [0:0] bottom_grid_pin_12_,
|
||||
output [0:0] bottom_grid_pin_13_,
|
||||
output [0:0] bottom_grid_pin_14_,
|
||||
output [0:0] bottom_grid_pin_15_,
|
||||
output [0:0] ccff_tail,
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN,
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT,
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR,
|
||||
input [0:0] bottom_width_0_height_0__pin_0_,
|
||||
output [0:0] bottom_width_0_height_0__pin_1_upper,
|
||||
output [0:0] bottom_width_0_height_0__pin_1_lower,
|
||||
input SC_IN_TOP,
|
||||
input SC_IN_BOT,
|
||||
output SC_OUT_TOP,
|
||||
output SC_OUT_BOT
|
||||
);
|
||||
( prog_clk, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, top_grid_pin_0_, bottom_grid_pin_0_, bottom_grid_pin_1_, bottom_grid_pin_2_, bottom_grid_pin_3_, bottom_grid_pin_4_, bottom_grid_pin_5_, bottom_grid_pin_6_, bottom_grid_pin_7_, bottom_grid_pin_8_, bottom_grid_pin_9_, bottom_grid_pin_10_, bottom_grid_pin_11_, bottom_grid_pin_12_, bottom_grid_pin_13_, bottom_grid_pin_14_, bottom_grid_pin_15_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, bottom_width_0_height_0__pin_0_, bottom_width_0_height_0__pin_1_upper, bottom_width_0_height_0__pin_1_lower, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
|
||||
input [0:0] prog_clk;
|
||||
input [0:19] chanx_left_in;
|
||||
input [0:19] chanx_right_in;
|
||||
input [0:0] ccff_head;
|
||||
output [0:19] chanx_left_out;
|
||||
output [0:19] chanx_right_out;
|
||||
output [0:0] top_grid_pin_0_;
|
||||
output [0:0] bottom_grid_pin_0_;
|
||||
output [0:0] bottom_grid_pin_1_;
|
||||
output [0:0] bottom_grid_pin_2_;
|
||||
output [0:0] bottom_grid_pin_3_;
|
||||
output [0:0] bottom_grid_pin_4_;
|
||||
output [0:0] bottom_grid_pin_5_;
|
||||
output [0:0] bottom_grid_pin_6_;
|
||||
output [0:0] bottom_grid_pin_7_;
|
||||
output [0:0] bottom_grid_pin_8_;
|
||||
output [0:0] bottom_grid_pin_9_;
|
||||
output [0:0] bottom_grid_pin_10_;
|
||||
output [0:0] bottom_grid_pin_11_;
|
||||
output [0:0] bottom_grid_pin_12_;
|
||||
output [0:0] bottom_grid_pin_13_;
|
||||
output [0:0] bottom_grid_pin_14_;
|
||||
output [0:0] bottom_grid_pin_15_;
|
||||
output [0:0] ccff_tail;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
|
||||
input [0:0] bottom_width_0_height_0__pin_0_;
|
||||
output [0:0] bottom_width_0_height_0__pin_1_upper;
|
||||
output [0:0] bottom_width_0_height_0__pin_1_lower;
|
||||
input SC_IN_TOP;
|
||||
input SC_IN_BOT;
|
||||
output SC_OUT_TOP;
|
||||
output SC_OUT_BOT;
|
||||
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
|
||||
|
|
|
|||
|
|
@ -1,22 +1,21 @@
|
|||
|
||||
|
||||
module cby_0__1_
|
||||
(
|
||||
input [0:0] prog_clk,
|
||||
input [0:19] chany_bottom_in,
|
||||
input [0:19] chany_top_in,
|
||||
input [0:0] ccff_head,
|
||||
output [0:19] chany_bottom_out,
|
||||
output [0:19] chany_top_out,
|
||||
output [0:0] left_grid_pin_0_,
|
||||
output [0:0] ccff_tail,
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN,
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT,
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR,
|
||||
input [0:0] right_width_0_height_0__pin_0_,
|
||||
output [0:0] right_width_0_height_0__pin_1_upper,
|
||||
output [0:0] right_width_0_height_0__pin_1_lower
|
||||
);
|
||||
( prog_clk, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, left_grid_pin_0_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, right_width_0_height_0__pin_0_, right_width_0_height_0__pin_1_upper, right_width_0_height_0__pin_1_lower );
|
||||
input [0:0] prog_clk;
|
||||
input [0:19] chany_bottom_in;
|
||||
input [0:19] chany_top_in;
|
||||
input [0:0] ccff_head;
|
||||
output [0:19] chany_bottom_out;
|
||||
output [0:19] chany_top_out;
|
||||
output [0:0] left_grid_pin_0_;
|
||||
output [0:0] ccff_tail;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
|
||||
input [0:0] right_width_0_height_0__pin_0_;
|
||||
output [0:0] right_width_0_height_0__pin_1_upper;
|
||||
output [0:0] right_width_0_height_0__pin_1_lower;
|
||||
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
|
||||
|
|
|
|||
|
|
@ -1,31 +1,30 @@
|
|||
|
||||
|
||||
module cby_1__1_
|
||||
(
|
||||
input [0:0] prog_clk,
|
||||
input [0:19] chany_bottom_in,
|
||||
input [0:19] chany_top_in,
|
||||
input [0:0] ccff_head,
|
||||
output [0:19] chany_bottom_out,
|
||||
output [0:19] chany_top_out,
|
||||
output [0:0] left_grid_pin_16_,
|
||||
output [0:0] left_grid_pin_17_,
|
||||
output [0:0] left_grid_pin_18_,
|
||||
output [0:0] left_grid_pin_19_,
|
||||
output [0:0] left_grid_pin_20_,
|
||||
output [0:0] left_grid_pin_21_,
|
||||
output [0:0] left_grid_pin_22_,
|
||||
output [0:0] left_grid_pin_23_,
|
||||
output [0:0] left_grid_pin_24_,
|
||||
output [0:0] left_grid_pin_25_,
|
||||
output [0:0] left_grid_pin_26_,
|
||||
output [0:0] left_grid_pin_27_,
|
||||
output [0:0] left_grid_pin_28_,
|
||||
output [0:0] left_grid_pin_29_,
|
||||
output [0:0] left_grid_pin_30_,
|
||||
output [0:0] left_grid_pin_31_,
|
||||
output [0:0] ccff_tail
|
||||
);
|
||||
( prog_clk, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, left_grid_pin_16_, left_grid_pin_17_, left_grid_pin_18_, left_grid_pin_19_, left_grid_pin_20_, left_grid_pin_21_, left_grid_pin_22_, left_grid_pin_23_, left_grid_pin_24_, left_grid_pin_25_, left_grid_pin_26_, left_grid_pin_27_, left_grid_pin_28_, left_grid_pin_29_, left_grid_pin_30_, left_grid_pin_31_, ccff_tail );
|
||||
input [0:0] prog_clk;
|
||||
input [0:19] chany_bottom_in;
|
||||
input [0:19] chany_top_in;
|
||||
input [0:0] ccff_head;
|
||||
output [0:19] chany_bottom_out;
|
||||
output [0:19] chany_top_out;
|
||||
output [0:0] left_grid_pin_16_;
|
||||
output [0:0] left_grid_pin_17_;
|
||||
output [0:0] left_grid_pin_18_;
|
||||
output [0:0] left_grid_pin_19_;
|
||||
output [0:0] left_grid_pin_20_;
|
||||
output [0:0] left_grid_pin_21_;
|
||||
output [0:0] left_grid_pin_22_;
|
||||
output [0:0] left_grid_pin_23_;
|
||||
output [0:0] left_grid_pin_24_;
|
||||
output [0:0] left_grid_pin_25_;
|
||||
output [0:0] left_grid_pin_26_;
|
||||
output [0:0] left_grid_pin_27_;
|
||||
output [0:0] left_grid_pin_28_;
|
||||
output [0:0] left_grid_pin_29_;
|
||||
output [0:0] left_grid_pin_30_;
|
||||
output [0:0] left_grid_pin_31_;
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
|
||||
|
|
|
|||
|
|
@ -1,38 +1,37 @@
|
|||
|
||||
|
||||
module cby_2__1_
|
||||
(
|
||||
input [0:0] prog_clk,
|
||||
input [0:19] chany_bottom_in,
|
||||
input [0:19] chany_top_in,
|
||||
input [0:0] ccff_head,
|
||||
output [0:19] chany_bottom_out,
|
||||
output [0:19] chany_top_out,
|
||||
output [0:0] right_grid_pin_0_,
|
||||
output [0:0] left_grid_pin_16_,
|
||||
output [0:0] left_grid_pin_17_,
|
||||
output [0:0] left_grid_pin_18_,
|
||||
output [0:0] left_grid_pin_19_,
|
||||
output [0:0] left_grid_pin_20_,
|
||||
output [0:0] left_grid_pin_21_,
|
||||
output [0:0] left_grid_pin_22_,
|
||||
output [0:0] left_grid_pin_23_,
|
||||
output [0:0] left_grid_pin_24_,
|
||||
output [0:0] left_grid_pin_25_,
|
||||
output [0:0] left_grid_pin_26_,
|
||||
output [0:0] left_grid_pin_27_,
|
||||
output [0:0] left_grid_pin_28_,
|
||||
output [0:0] left_grid_pin_29_,
|
||||
output [0:0] left_grid_pin_30_,
|
||||
output [0:0] left_grid_pin_31_,
|
||||
output [0:0] ccff_tail,
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN,
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT,
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR,
|
||||
input [0:0] left_width_0_height_0__pin_0_,
|
||||
output [0:0] left_width_0_height_0__pin_1_upper,
|
||||
output [0:0] left_width_0_height_0__pin_1_lower
|
||||
);
|
||||
( prog_clk, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, right_grid_pin_0_, left_grid_pin_16_, left_grid_pin_17_, left_grid_pin_18_, left_grid_pin_19_, left_grid_pin_20_, left_grid_pin_21_, left_grid_pin_22_, left_grid_pin_23_, left_grid_pin_24_, left_grid_pin_25_, left_grid_pin_26_, left_grid_pin_27_, left_grid_pin_28_, left_grid_pin_29_, left_grid_pin_30_, left_grid_pin_31_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, left_width_0_height_0__pin_0_, left_width_0_height_0__pin_1_upper, left_width_0_height_0__pin_1_lower );
|
||||
input [0:0] prog_clk;
|
||||
input [0:19] chany_bottom_in;
|
||||
input [0:19] chany_top_in;
|
||||
input [0:0] ccff_head;
|
||||
output [0:19] chany_bottom_out;
|
||||
output [0:19] chany_top_out;
|
||||
output [0:0] right_grid_pin_0_;
|
||||
output [0:0] left_grid_pin_16_;
|
||||
output [0:0] left_grid_pin_17_;
|
||||
output [0:0] left_grid_pin_18_;
|
||||
output [0:0] left_grid_pin_19_;
|
||||
output [0:0] left_grid_pin_20_;
|
||||
output [0:0] left_grid_pin_21_;
|
||||
output [0:0] left_grid_pin_22_;
|
||||
output [0:0] left_grid_pin_23_;
|
||||
output [0:0] left_grid_pin_24_;
|
||||
output [0:0] left_grid_pin_25_;
|
||||
output [0:0] left_grid_pin_26_;
|
||||
output [0:0] left_grid_pin_27_;
|
||||
output [0:0] left_grid_pin_28_;
|
||||
output [0:0] left_grid_pin_29_;
|
||||
output [0:0] left_grid_pin_30_;
|
||||
output [0:0] left_grid_pin_31_;
|
||||
output [0:0] ccff_tail;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
|
||||
input [0:0] left_width_0_height_0__pin_0_;
|
||||
output [0:0] left_width_0_height_0__pin_1_upper;
|
||||
output [0:0] left_width_0_height_0__pin_1_lower;
|
||||
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
|
||||
|
|
|
|||
|
|
@ -1,22 +1,21 @@
|
|||
|
||||
|
||||
module sb_0__0_
|
||||
(
|
||||
input [0:0] prog_clk,
|
||||
input [0:19] chany_top_in,
|
||||
input [0:0] top_left_grid_pin_1_,
|
||||
input [0:19] chanx_right_in,
|
||||
input [0:0] right_bottom_grid_pin_1_,
|
||||
input [0:0] right_bottom_grid_pin_3_,
|
||||
input [0:0] right_bottom_grid_pin_5_,
|
||||
input [0:0] right_bottom_grid_pin_7_,
|
||||
input [0:0] right_bottom_grid_pin_9_,
|
||||
input [0:0] right_bottom_grid_pin_11_,
|
||||
input [0:0] ccff_head,
|
||||
output [0:19] chany_top_out,
|
||||
output [0:19] chanx_right_out,
|
||||
output [0:0] ccff_tail
|
||||
);
|
||||
( prog_clk, chany_top_in, top_left_grid_pin_1_, chanx_right_in, right_bottom_grid_pin_1_, right_bottom_grid_pin_3_, right_bottom_grid_pin_5_, right_bottom_grid_pin_7_, right_bottom_grid_pin_9_, right_bottom_grid_pin_11_, ccff_head, chany_top_out, chanx_right_out, ccff_tail );
|
||||
input [0:0] prog_clk;
|
||||
input [0:19] chany_top_in;
|
||||
input [0:0] top_left_grid_pin_1_;
|
||||
input [0:19] chanx_right_in;
|
||||
input [0:0] right_bottom_grid_pin_1_;
|
||||
input [0:0] right_bottom_grid_pin_3_;
|
||||
input [0:0] right_bottom_grid_pin_5_;
|
||||
input [0:0] right_bottom_grid_pin_7_;
|
||||
input [0:0] right_bottom_grid_pin_9_;
|
||||
input [0:0] right_bottom_grid_pin_11_;
|
||||
input [0:0] ccff_head;
|
||||
output [0:19] chany_top_out;
|
||||
output [0:19] chanx_right_out;
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
|
||||
|
|
|
|||
|
|
@ -1,27 +1,26 @@
|
|||
|
||||
|
||||
module sb_0__1_
|
||||
(
|
||||
input [0:0] prog_clk,
|
||||
input [0:19] chany_top_in,
|
||||
input [0:0] top_left_grid_pin_1_,
|
||||
input [0:19] chanx_right_in,
|
||||
input [0:0] right_bottom_grid_pin_34_,
|
||||
input [0:0] right_bottom_grid_pin_35_,
|
||||
input [0:0] right_bottom_grid_pin_36_,
|
||||
input [0:0] right_bottom_grid_pin_37_,
|
||||
input [0:0] right_bottom_grid_pin_38_,
|
||||
input [0:0] right_bottom_grid_pin_39_,
|
||||
input [0:0] right_bottom_grid_pin_40_,
|
||||
input [0:0] right_bottom_grid_pin_41_,
|
||||
input [0:19] chany_bottom_in,
|
||||
input [0:0] bottom_left_grid_pin_1_,
|
||||
input [0:0] ccff_head,
|
||||
output [0:19] chany_top_out,
|
||||
output [0:19] chanx_right_out,
|
||||
output [0:19] chany_bottom_out,
|
||||
output [0:0] ccff_tail
|
||||
);
|
||||
( prog_clk, chany_top_in, top_left_grid_pin_1_, chanx_right_in, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_1_, ccff_head, chany_top_out, chanx_right_out, chany_bottom_out, ccff_tail );
|
||||
input [0:0] prog_clk;
|
||||
input [0:19] chany_top_in;
|
||||
input [0:0] top_left_grid_pin_1_;
|
||||
input [0:19] chanx_right_in;
|
||||
input [0:0] right_bottom_grid_pin_34_;
|
||||
input [0:0] right_bottom_grid_pin_35_;
|
||||
input [0:0] right_bottom_grid_pin_36_;
|
||||
input [0:0] right_bottom_grid_pin_37_;
|
||||
input [0:0] right_bottom_grid_pin_38_;
|
||||
input [0:0] right_bottom_grid_pin_39_;
|
||||
input [0:0] right_bottom_grid_pin_40_;
|
||||
input [0:0] right_bottom_grid_pin_41_;
|
||||
input [0:19] chany_bottom_in;
|
||||
input [0:0] bottom_left_grid_pin_1_;
|
||||
input [0:0] ccff_head;
|
||||
output [0:19] chany_top_out;
|
||||
output [0:19] chanx_right_out;
|
||||
output [0:19] chany_bottom_out;
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
|
||||
|
|
|
|||
|
|
@ -1,29 +1,28 @@
|
|||
|
||||
|
||||
module sb_0__2_
|
||||
(
|
||||
input [0:0] prog_clk,
|
||||
input [0:19] chanx_right_in,
|
||||
input [0:0] right_top_grid_pin_1_,
|
||||
input [0:0] right_bottom_grid_pin_34_,
|
||||
input [0:0] right_bottom_grid_pin_35_,
|
||||
input [0:0] right_bottom_grid_pin_36_,
|
||||
input [0:0] right_bottom_grid_pin_37_,
|
||||
input [0:0] right_bottom_grid_pin_38_,
|
||||
input [0:0] right_bottom_grid_pin_39_,
|
||||
input [0:0] right_bottom_grid_pin_40_,
|
||||
input [0:0] right_bottom_grid_pin_41_,
|
||||
input [0:19] chany_bottom_in,
|
||||
input [0:0] bottom_left_grid_pin_1_,
|
||||
input [0:0] ccff_head,
|
||||
output [0:19] chanx_right_out,
|
||||
output [0:19] chany_bottom_out,
|
||||
output [0:0] ccff_tail,
|
||||
input SC_IN_TOP,
|
||||
input SC_IN_BOT,
|
||||
output SC_OUT_TOP,
|
||||
output SC_OUT_BOT
|
||||
);
|
||||
( prog_clk, chanx_right_in, right_top_grid_pin_1_, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_1_, ccff_head, chanx_right_out, chany_bottom_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
|
||||
input [0:0] prog_clk;
|
||||
input [0:19] chanx_right_in;
|
||||
input [0:0] right_top_grid_pin_1_;
|
||||
input [0:0] right_bottom_grid_pin_34_;
|
||||
input [0:0] right_bottom_grid_pin_35_;
|
||||
input [0:0] right_bottom_grid_pin_36_;
|
||||
input [0:0] right_bottom_grid_pin_37_;
|
||||
input [0:0] right_bottom_grid_pin_38_;
|
||||
input [0:0] right_bottom_grid_pin_39_;
|
||||
input [0:0] right_bottom_grid_pin_40_;
|
||||
input [0:0] right_bottom_grid_pin_41_;
|
||||
input [0:19] chany_bottom_in;
|
||||
input [0:0] bottom_left_grid_pin_1_;
|
||||
input [0:0] ccff_head;
|
||||
output [0:19] chanx_right_out;
|
||||
output [0:19] chany_bottom_out;
|
||||
output [0:0] ccff_tail;
|
||||
input SC_IN_TOP;
|
||||
input SC_IN_BOT;
|
||||
output SC_OUT_TOP;
|
||||
output SC_OUT_BOT;
|
||||
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
|
||||
|
|
|
|||
|
|
@ -1,41 +1,40 @@
|
|||
|
||||
|
||||
module sb_1__0_
|
||||
(
|
||||
input [0:0] prog_clk,
|
||||
input [0:19] chany_top_in,
|
||||
input [0:0] top_left_grid_pin_42_,
|
||||
input [0:0] top_left_grid_pin_43_,
|
||||
input [0:0] top_left_grid_pin_44_,
|
||||
input [0:0] top_left_grid_pin_45_,
|
||||
input [0:0] top_left_grid_pin_46_,
|
||||
input [0:0] top_left_grid_pin_47_,
|
||||
input [0:0] top_left_grid_pin_48_,
|
||||
input [0:0] top_left_grid_pin_49_,
|
||||
input [0:19] chanx_right_in,
|
||||
input [0:0] right_bottom_grid_pin_1_,
|
||||
input [0:0] right_bottom_grid_pin_3_,
|
||||
input [0:0] right_bottom_grid_pin_5_,
|
||||
input [0:0] right_bottom_grid_pin_7_,
|
||||
input [0:0] right_bottom_grid_pin_9_,
|
||||
input [0:0] right_bottom_grid_pin_11_,
|
||||
input [0:19] chanx_left_in,
|
||||
input [0:0] left_bottom_grid_pin_1_,
|
||||
input [0:0] left_bottom_grid_pin_3_,
|
||||
input [0:0] left_bottom_grid_pin_5_,
|
||||
input [0:0] left_bottom_grid_pin_7_,
|
||||
input [0:0] left_bottom_grid_pin_9_,
|
||||
input [0:0] left_bottom_grid_pin_11_,
|
||||
input [0:0] ccff_head,
|
||||
output [0:19] chany_top_out,
|
||||
output [0:19] chanx_right_out,
|
||||
output [0:19] chanx_left_out,
|
||||
output [0:0] ccff_tail,
|
||||
input SC_IN_TOP,
|
||||
input SC_IN_BOT,
|
||||
output SC_OUT_TOP,
|
||||
output SC_OUT_BOT
|
||||
);
|
||||
( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, chanx_right_in, right_bottom_grid_pin_1_, right_bottom_grid_pin_3_, right_bottom_grid_pin_5_, right_bottom_grid_pin_7_, right_bottom_grid_pin_9_, right_bottom_grid_pin_11_, chanx_left_in, left_bottom_grid_pin_1_, left_bottom_grid_pin_3_, left_bottom_grid_pin_5_, left_bottom_grid_pin_7_, left_bottom_grid_pin_9_, left_bottom_grid_pin_11_, ccff_head, chany_top_out, chanx_right_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
|
||||
input [0:0] prog_clk;
|
||||
input [0:19] chany_top_in;
|
||||
input [0:0] top_left_grid_pin_42_;
|
||||
input [0:0] top_left_grid_pin_43_;
|
||||
input [0:0] top_left_grid_pin_44_;
|
||||
input [0:0] top_left_grid_pin_45_;
|
||||
input [0:0] top_left_grid_pin_46_;
|
||||
input [0:0] top_left_grid_pin_47_;
|
||||
input [0:0] top_left_grid_pin_48_;
|
||||
input [0:0] top_left_grid_pin_49_;
|
||||
input [0:19] chanx_right_in;
|
||||
input [0:0] right_bottom_grid_pin_1_;
|
||||
input [0:0] right_bottom_grid_pin_3_;
|
||||
input [0:0] right_bottom_grid_pin_5_;
|
||||
input [0:0] right_bottom_grid_pin_7_;
|
||||
input [0:0] right_bottom_grid_pin_9_;
|
||||
input [0:0] right_bottom_grid_pin_11_;
|
||||
input [0:19] chanx_left_in;
|
||||
input [0:0] left_bottom_grid_pin_1_;
|
||||
input [0:0] left_bottom_grid_pin_3_;
|
||||
input [0:0] left_bottom_grid_pin_5_;
|
||||
input [0:0] left_bottom_grid_pin_7_;
|
||||
input [0:0] left_bottom_grid_pin_9_;
|
||||
input [0:0] left_bottom_grid_pin_11_;
|
||||
input [0:0] ccff_head;
|
||||
output [0:19] chany_top_out;
|
||||
output [0:19] chanx_right_out;
|
||||
output [0:19] chanx_left_out;
|
||||
output [0:0] ccff_tail;
|
||||
input SC_IN_TOP;
|
||||
input SC_IN_BOT;
|
||||
output SC_OUT_TOP;
|
||||
output SC_OUT_BOT;
|
||||
|
||||
wire [0:3] mux_tree_tapbuf_size11_0_sram;
|
||||
wire [0:3] mux_tree_tapbuf_size11_0_sram_inv;
|
||||
|
|
|
|||
|
|
@ -1,51 +1,50 @@
|
|||
|
||||
|
||||
module sb_1__1_
|
||||
(
|
||||
input [0:0] prog_clk,
|
||||
input [0:19] chany_top_in,
|
||||
input [0:0] top_left_grid_pin_42_,
|
||||
input [0:0] top_left_grid_pin_43_,
|
||||
input [0:0] top_left_grid_pin_44_,
|
||||
input [0:0] top_left_grid_pin_45_,
|
||||
input [0:0] top_left_grid_pin_46_,
|
||||
input [0:0] top_left_grid_pin_47_,
|
||||
input [0:0] top_left_grid_pin_48_,
|
||||
input [0:0] top_left_grid_pin_49_,
|
||||
input [0:19] chanx_right_in,
|
||||
input [0:0] right_bottom_grid_pin_34_,
|
||||
input [0:0] right_bottom_grid_pin_35_,
|
||||
input [0:0] right_bottom_grid_pin_36_,
|
||||
input [0:0] right_bottom_grid_pin_37_,
|
||||
input [0:0] right_bottom_grid_pin_38_,
|
||||
input [0:0] right_bottom_grid_pin_39_,
|
||||
input [0:0] right_bottom_grid_pin_40_,
|
||||
input [0:0] right_bottom_grid_pin_41_,
|
||||
input [0:19] chany_bottom_in,
|
||||
input [0:0] bottom_left_grid_pin_42_,
|
||||
input [0:0] bottom_left_grid_pin_43_,
|
||||
input [0:0] bottom_left_grid_pin_44_,
|
||||
input [0:0] bottom_left_grid_pin_45_,
|
||||
input [0:0] bottom_left_grid_pin_46_,
|
||||
input [0:0] bottom_left_grid_pin_47_,
|
||||
input [0:0] bottom_left_grid_pin_48_,
|
||||
input [0:0] bottom_left_grid_pin_49_,
|
||||
input [0:19] chanx_left_in,
|
||||
input [0:0] left_bottom_grid_pin_34_,
|
||||
input [0:0] left_bottom_grid_pin_35_,
|
||||
input [0:0] left_bottom_grid_pin_36_,
|
||||
input [0:0] left_bottom_grid_pin_37_,
|
||||
input [0:0] left_bottom_grid_pin_38_,
|
||||
input [0:0] left_bottom_grid_pin_39_,
|
||||
input [0:0] left_bottom_grid_pin_40_,
|
||||
input [0:0] left_bottom_grid_pin_41_,
|
||||
input [0:0] ccff_head,
|
||||
output [0:19] chany_top_out,
|
||||
output [0:19] chanx_right_out,
|
||||
output [0:19] chany_bottom_out,
|
||||
output [0:19] chanx_left_out,
|
||||
output [0:0] ccff_tail
|
||||
);
|
||||
( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, chanx_right_in, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_top_out, chanx_right_out, chany_bottom_out, chanx_left_out, ccff_tail );
|
||||
input [0:0] prog_clk;
|
||||
input [0:19] chany_top_in;
|
||||
input [0:0] top_left_grid_pin_42_;
|
||||
input [0:0] top_left_grid_pin_43_;
|
||||
input [0:0] top_left_grid_pin_44_;
|
||||
input [0:0] top_left_grid_pin_45_;
|
||||
input [0:0] top_left_grid_pin_46_;
|
||||
input [0:0] top_left_grid_pin_47_;
|
||||
input [0:0] top_left_grid_pin_48_;
|
||||
input [0:0] top_left_grid_pin_49_;
|
||||
input [0:19] chanx_right_in;
|
||||
input [0:0] right_bottom_grid_pin_34_;
|
||||
input [0:0] right_bottom_grid_pin_35_;
|
||||
input [0:0] right_bottom_grid_pin_36_;
|
||||
input [0:0] right_bottom_grid_pin_37_;
|
||||
input [0:0] right_bottom_grid_pin_38_;
|
||||
input [0:0] right_bottom_grid_pin_39_;
|
||||
input [0:0] right_bottom_grid_pin_40_;
|
||||
input [0:0] right_bottom_grid_pin_41_;
|
||||
input [0:19] chany_bottom_in;
|
||||
input [0:0] bottom_left_grid_pin_42_;
|
||||
input [0:0] bottom_left_grid_pin_43_;
|
||||
input [0:0] bottom_left_grid_pin_44_;
|
||||
input [0:0] bottom_left_grid_pin_45_;
|
||||
input [0:0] bottom_left_grid_pin_46_;
|
||||
input [0:0] bottom_left_grid_pin_47_;
|
||||
input [0:0] bottom_left_grid_pin_48_;
|
||||
input [0:0] bottom_left_grid_pin_49_;
|
||||
input [0:19] chanx_left_in;
|
||||
input [0:0] left_bottom_grid_pin_34_;
|
||||
input [0:0] left_bottom_grid_pin_35_;
|
||||
input [0:0] left_bottom_grid_pin_36_;
|
||||
input [0:0] left_bottom_grid_pin_37_;
|
||||
input [0:0] left_bottom_grid_pin_38_;
|
||||
input [0:0] left_bottom_grid_pin_39_;
|
||||
input [0:0] left_bottom_grid_pin_40_;
|
||||
input [0:0] left_bottom_grid_pin_41_;
|
||||
input [0:0] ccff_head;
|
||||
output [0:19] chany_top_out;
|
||||
output [0:19] chanx_right_out;
|
||||
output [0:19] chany_bottom_out;
|
||||
output [0:19] chanx_left_out;
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
|
||||
|
|
|
|||
|
|
@ -1,47 +1,46 @@
|
|||
|
||||
|
||||
module sb_1__2_
|
||||
(
|
||||
input [0:0] prog_clk,
|
||||
input [0:19] chanx_right_in,
|
||||
input [0:0] right_top_grid_pin_1_,
|
||||
input [0:0] right_bottom_grid_pin_34_,
|
||||
input [0:0] right_bottom_grid_pin_35_,
|
||||
input [0:0] right_bottom_grid_pin_36_,
|
||||
input [0:0] right_bottom_grid_pin_37_,
|
||||
input [0:0] right_bottom_grid_pin_38_,
|
||||
input [0:0] right_bottom_grid_pin_39_,
|
||||
input [0:0] right_bottom_grid_pin_40_,
|
||||
input [0:0] right_bottom_grid_pin_41_,
|
||||
input [0:19] chany_bottom_in,
|
||||
input [0:0] bottom_left_grid_pin_42_,
|
||||
input [0:0] bottom_left_grid_pin_43_,
|
||||
input [0:0] bottom_left_grid_pin_44_,
|
||||
input [0:0] bottom_left_grid_pin_45_,
|
||||
input [0:0] bottom_left_grid_pin_46_,
|
||||
input [0:0] bottom_left_grid_pin_47_,
|
||||
input [0:0] bottom_left_grid_pin_48_,
|
||||
input [0:0] bottom_left_grid_pin_49_,
|
||||
input [0:19] chanx_left_in,
|
||||
input [0:0] left_top_grid_pin_1_,
|
||||
input [0:0] left_bottom_grid_pin_34_,
|
||||
input [0:0] left_bottom_grid_pin_35_,
|
||||
input [0:0] left_bottom_grid_pin_36_,
|
||||
input [0:0] left_bottom_grid_pin_37_,
|
||||
input [0:0] left_bottom_grid_pin_38_,
|
||||
input [0:0] left_bottom_grid_pin_39_,
|
||||
input [0:0] left_bottom_grid_pin_40_,
|
||||
input [0:0] left_bottom_grid_pin_41_,
|
||||
input [0:0] ccff_head,
|
||||
output [0:19] chanx_right_out,
|
||||
output [0:19] chany_bottom_out,
|
||||
output [0:19] chanx_left_out,
|
||||
output [0:0] ccff_tail,
|
||||
input SC_IN_TOP,
|
||||
input SC_IN_BOT,
|
||||
output SC_OUT_TOP,
|
||||
output SC_OUT_BOT
|
||||
);
|
||||
( prog_clk, chanx_right_in, right_top_grid_pin_1_, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_top_grid_pin_1_, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chanx_right_out, chany_bottom_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
|
||||
input [0:0] prog_clk;
|
||||
input [0:19] chanx_right_in;
|
||||
input [0:0] right_top_grid_pin_1_;
|
||||
input [0:0] right_bottom_grid_pin_34_;
|
||||
input [0:0] right_bottom_grid_pin_35_;
|
||||
input [0:0] right_bottom_grid_pin_36_;
|
||||
input [0:0] right_bottom_grid_pin_37_;
|
||||
input [0:0] right_bottom_grid_pin_38_;
|
||||
input [0:0] right_bottom_grid_pin_39_;
|
||||
input [0:0] right_bottom_grid_pin_40_;
|
||||
input [0:0] right_bottom_grid_pin_41_;
|
||||
input [0:19] chany_bottom_in;
|
||||
input [0:0] bottom_left_grid_pin_42_;
|
||||
input [0:0] bottom_left_grid_pin_43_;
|
||||
input [0:0] bottom_left_grid_pin_44_;
|
||||
input [0:0] bottom_left_grid_pin_45_;
|
||||
input [0:0] bottom_left_grid_pin_46_;
|
||||
input [0:0] bottom_left_grid_pin_47_;
|
||||
input [0:0] bottom_left_grid_pin_48_;
|
||||
input [0:0] bottom_left_grid_pin_49_;
|
||||
input [0:19] chanx_left_in;
|
||||
input [0:0] left_top_grid_pin_1_;
|
||||
input [0:0] left_bottom_grid_pin_34_;
|
||||
input [0:0] left_bottom_grid_pin_35_;
|
||||
input [0:0] left_bottom_grid_pin_36_;
|
||||
input [0:0] left_bottom_grid_pin_37_;
|
||||
input [0:0] left_bottom_grid_pin_38_;
|
||||
input [0:0] left_bottom_grid_pin_39_;
|
||||
input [0:0] left_bottom_grid_pin_40_;
|
||||
input [0:0] left_bottom_grid_pin_41_;
|
||||
input [0:0] ccff_head;
|
||||
output [0:19] chanx_right_out;
|
||||
output [0:19] chany_bottom_out;
|
||||
output [0:19] chanx_left_out;
|
||||
output [0:0] ccff_tail;
|
||||
input SC_IN_TOP;
|
||||
input SC_IN_BOT;
|
||||
output SC_OUT_TOP;
|
||||
output SC_OUT_BOT;
|
||||
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
|
||||
|
|
|
|||
|
|
@ -1,30 +1,29 @@
|
|||
|
||||
|
||||
module sb_2__0_
|
||||
(
|
||||
input [0:0] prog_clk,
|
||||
input [0:19] chany_top_in,
|
||||
input [0:0] top_left_grid_pin_42_,
|
||||
input [0:0] top_left_grid_pin_43_,
|
||||
input [0:0] top_left_grid_pin_44_,
|
||||
input [0:0] top_left_grid_pin_45_,
|
||||
input [0:0] top_left_grid_pin_46_,
|
||||
input [0:0] top_left_grid_pin_47_,
|
||||
input [0:0] top_left_grid_pin_48_,
|
||||
input [0:0] top_left_grid_pin_49_,
|
||||
input [0:0] top_right_grid_pin_1_,
|
||||
input [0:19] chanx_left_in,
|
||||
input [0:0] left_bottom_grid_pin_1_,
|
||||
input [0:0] left_bottom_grid_pin_3_,
|
||||
input [0:0] left_bottom_grid_pin_5_,
|
||||
input [0:0] left_bottom_grid_pin_7_,
|
||||
input [0:0] left_bottom_grid_pin_9_,
|
||||
input [0:0] left_bottom_grid_pin_11_,
|
||||
input [0:0] ccff_head,
|
||||
output [0:19] chany_top_out,
|
||||
output [0:19] chanx_left_out,
|
||||
output [0:0] ccff_tail
|
||||
);
|
||||
( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, top_right_grid_pin_1_, chanx_left_in, left_bottom_grid_pin_1_, left_bottom_grid_pin_3_, left_bottom_grid_pin_5_, left_bottom_grid_pin_7_, left_bottom_grid_pin_9_, left_bottom_grid_pin_11_, ccff_head, chany_top_out, chanx_left_out, ccff_tail );
|
||||
input [0:0] prog_clk;
|
||||
input [0:19] chany_top_in;
|
||||
input [0:0] top_left_grid_pin_42_;
|
||||
input [0:0] top_left_grid_pin_43_;
|
||||
input [0:0] top_left_grid_pin_44_;
|
||||
input [0:0] top_left_grid_pin_45_;
|
||||
input [0:0] top_left_grid_pin_46_;
|
||||
input [0:0] top_left_grid_pin_47_;
|
||||
input [0:0] top_left_grid_pin_48_;
|
||||
input [0:0] top_left_grid_pin_49_;
|
||||
input [0:0] top_right_grid_pin_1_;
|
||||
input [0:19] chanx_left_in;
|
||||
input [0:0] left_bottom_grid_pin_1_;
|
||||
input [0:0] left_bottom_grid_pin_3_;
|
||||
input [0:0] left_bottom_grid_pin_5_;
|
||||
input [0:0] left_bottom_grid_pin_7_;
|
||||
input [0:0] left_bottom_grid_pin_9_;
|
||||
input [0:0] left_bottom_grid_pin_11_;
|
||||
input [0:0] ccff_head;
|
||||
output [0:19] chany_top_out;
|
||||
output [0:19] chanx_left_out;
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
|
||||
|
|
|
|||
|
|
@ -1,43 +1,42 @@
|
|||
|
||||
|
||||
module sb_2__1_
|
||||
(
|
||||
input [0:0] prog_clk,
|
||||
input [0:19] chany_top_in,
|
||||
input [0:0] top_left_grid_pin_42_,
|
||||
input [0:0] top_left_grid_pin_43_,
|
||||
input [0:0] top_left_grid_pin_44_,
|
||||
input [0:0] top_left_grid_pin_45_,
|
||||
input [0:0] top_left_grid_pin_46_,
|
||||
input [0:0] top_left_grid_pin_47_,
|
||||
input [0:0] top_left_grid_pin_48_,
|
||||
input [0:0] top_left_grid_pin_49_,
|
||||
input [0:0] top_right_grid_pin_1_,
|
||||
input [0:19] chany_bottom_in,
|
||||
input [0:0] bottom_right_grid_pin_1_,
|
||||
input [0:0] bottom_left_grid_pin_42_,
|
||||
input [0:0] bottom_left_grid_pin_43_,
|
||||
input [0:0] bottom_left_grid_pin_44_,
|
||||
input [0:0] bottom_left_grid_pin_45_,
|
||||
input [0:0] bottom_left_grid_pin_46_,
|
||||
input [0:0] bottom_left_grid_pin_47_,
|
||||
input [0:0] bottom_left_grid_pin_48_,
|
||||
input [0:0] bottom_left_grid_pin_49_,
|
||||
input [0:19] chanx_left_in,
|
||||
input [0:0] left_bottom_grid_pin_34_,
|
||||
input [0:0] left_bottom_grid_pin_35_,
|
||||
input [0:0] left_bottom_grid_pin_36_,
|
||||
input [0:0] left_bottom_grid_pin_37_,
|
||||
input [0:0] left_bottom_grid_pin_38_,
|
||||
input [0:0] left_bottom_grid_pin_39_,
|
||||
input [0:0] left_bottom_grid_pin_40_,
|
||||
input [0:0] left_bottom_grid_pin_41_,
|
||||
input [0:0] ccff_head,
|
||||
output [0:19] chany_top_out,
|
||||
output [0:19] chany_bottom_out,
|
||||
output [0:19] chanx_left_out,
|
||||
output [0:0] ccff_tail
|
||||
);
|
||||
( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, top_right_grid_pin_1_, chany_bottom_in, bottom_right_grid_pin_1_, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_top_out, chany_bottom_out, chanx_left_out, ccff_tail );
|
||||
input [0:0] prog_clk;
|
||||
input [0:19] chany_top_in;
|
||||
input [0:0] top_left_grid_pin_42_;
|
||||
input [0:0] top_left_grid_pin_43_;
|
||||
input [0:0] top_left_grid_pin_44_;
|
||||
input [0:0] top_left_grid_pin_45_;
|
||||
input [0:0] top_left_grid_pin_46_;
|
||||
input [0:0] top_left_grid_pin_47_;
|
||||
input [0:0] top_left_grid_pin_48_;
|
||||
input [0:0] top_left_grid_pin_49_;
|
||||
input [0:0] top_right_grid_pin_1_;
|
||||
input [0:19] chany_bottom_in;
|
||||
input [0:0] bottom_right_grid_pin_1_;
|
||||
input [0:0] bottom_left_grid_pin_42_;
|
||||
input [0:0] bottom_left_grid_pin_43_;
|
||||
input [0:0] bottom_left_grid_pin_44_;
|
||||
input [0:0] bottom_left_grid_pin_45_;
|
||||
input [0:0] bottom_left_grid_pin_46_;
|
||||
input [0:0] bottom_left_grid_pin_47_;
|
||||
input [0:0] bottom_left_grid_pin_48_;
|
||||
input [0:0] bottom_left_grid_pin_49_;
|
||||
input [0:19] chanx_left_in;
|
||||
input [0:0] left_bottom_grid_pin_34_;
|
||||
input [0:0] left_bottom_grid_pin_35_;
|
||||
input [0:0] left_bottom_grid_pin_36_;
|
||||
input [0:0] left_bottom_grid_pin_37_;
|
||||
input [0:0] left_bottom_grid_pin_38_;
|
||||
input [0:0] left_bottom_grid_pin_39_;
|
||||
input [0:0] left_bottom_grid_pin_40_;
|
||||
input [0:0] left_bottom_grid_pin_41_;
|
||||
input [0:0] ccff_head;
|
||||
output [0:19] chany_top_out;
|
||||
output [0:19] chany_bottom_out;
|
||||
output [0:19] chanx_left_out;
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
|
||||
|
|
|
|||
|
|
@ -1,37 +1,36 @@
|
|||
|
||||
|
||||
module sb_2__2_
|
||||
(
|
||||
input [0:0] prog_clk,
|
||||
input [0:19] chany_bottom_in,
|
||||
input [0:0] bottom_right_grid_pin_1_,
|
||||
input [0:0] bottom_left_grid_pin_42_,
|
||||
input [0:0] bottom_left_grid_pin_43_,
|
||||
input [0:0] bottom_left_grid_pin_44_,
|
||||
input [0:0] bottom_left_grid_pin_45_,
|
||||
input [0:0] bottom_left_grid_pin_46_,
|
||||
input [0:0] bottom_left_grid_pin_47_,
|
||||
input [0:0] bottom_left_grid_pin_48_,
|
||||
input [0:0] bottom_left_grid_pin_49_,
|
||||
input [0:19] chanx_left_in,
|
||||
input [0:0] left_top_grid_pin_1_,
|
||||
input [0:0] left_bottom_grid_pin_34_,
|
||||
input [0:0] left_bottom_grid_pin_35_,
|
||||
input [0:0] left_bottom_grid_pin_36_,
|
||||
input [0:0] left_bottom_grid_pin_37_,
|
||||
input [0:0] left_bottom_grid_pin_38_,
|
||||
input [0:0] left_bottom_grid_pin_39_,
|
||||
input [0:0] left_bottom_grid_pin_40_,
|
||||
input [0:0] left_bottom_grid_pin_41_,
|
||||
input [0:0] ccff_head,
|
||||
output [0:19] chany_bottom_out,
|
||||
output [0:19] chanx_left_out,
|
||||
output [0:0] ccff_tail,
|
||||
input SC_IN_TOP,
|
||||
input SC_IN_BOT,
|
||||
output SC_OUT_TOP,
|
||||
output SC_OUT_BOT
|
||||
);
|
||||
( prog_clk, chany_bottom_in, bottom_right_grid_pin_1_, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_top_grid_pin_1_, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_bottom_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
|
||||
input [0:0] prog_clk;
|
||||
input [0:19] chany_bottom_in;
|
||||
input [0:0] bottom_right_grid_pin_1_;
|
||||
input [0:0] bottom_left_grid_pin_42_;
|
||||
input [0:0] bottom_left_grid_pin_43_;
|
||||
input [0:0] bottom_left_grid_pin_44_;
|
||||
input [0:0] bottom_left_grid_pin_45_;
|
||||
input [0:0] bottom_left_grid_pin_46_;
|
||||
input [0:0] bottom_left_grid_pin_47_;
|
||||
input [0:0] bottom_left_grid_pin_48_;
|
||||
input [0:0] bottom_left_grid_pin_49_;
|
||||
input [0:19] chanx_left_in;
|
||||
input [0:0] left_top_grid_pin_1_;
|
||||
input [0:0] left_bottom_grid_pin_34_;
|
||||
input [0:0] left_bottom_grid_pin_35_;
|
||||
input [0:0] left_bottom_grid_pin_36_;
|
||||
input [0:0] left_bottom_grid_pin_37_;
|
||||
input [0:0] left_bottom_grid_pin_38_;
|
||||
input [0:0] left_bottom_grid_pin_39_;
|
||||
input [0:0] left_bottom_grid_pin_40_;
|
||||
input [0:0] left_bottom_grid_pin_41_;
|
||||
input [0:0] ccff_head;
|
||||
output [0:19] chany_bottom_out;
|
||||
output [0:19] chanx_left_out;
|
||||
output [0:0] ccff_tail;
|
||||
input SC_IN_TOP;
|
||||
input SC_IN_BOT;
|
||||
output SC_OUT_TOP;
|
||||
output SC_OUT_BOT;
|
||||
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
- Fabric bitstream
|
||||
- Author: Xifan TANG
|
||||
- Organization: University of Utah
|
||||
- Date: Fri Nov 6 14:45:09 2020
|
||||
- Date: Sat Nov 7 21:20:25 2020
|
||||
-->
|
||||
|
||||
<fabric_bitstream>
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
- Architecture independent bitstream
|
||||
- Author: Xifan TANG
|
||||
- Organization: University of Utah
|
||||
- Date: Fri Nov 6 14:45:09 2020
|
||||
- Date: Sat Nov 7 21:20:25 2020
|
||||
-->
|
||||
|
||||
<bitstream_block name="fpga_top" hierarchy_level="0">
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock
|
|||
Warning 3: Model 'frac_lut4' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
|
||||
Warning 4: Model 'frac_lut4' output port 'lut4_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
|
||||
Warning 5: Model 'frac_lut4' output port 'lut3_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
|
||||
# Loading Architecture Description took 0.00 seconds (max_rss 9.0 MiB, delta_rss +0.6 MiB)
|
||||
# Loading Architecture Description took 0.01 seconds (max_rss 9.0 MiB, delta_rss +0.6 MiB)
|
||||
# Building complex block graph
|
||||
Warning 6: [LINE 582] false logically-equivalent pin clb[0].I0[1].
|
||||
Warning 7: [LINE 582] false logically-equivalent pin clb[0].I0[2].
|
||||
|
|
@ -255,9 +255,9 @@ Netlist conversion complete.
|
|||
Begin loading packed FPGA netlist file.
|
||||
Netlist generated from file 'top.net'.
|
||||
Detected 0 constant generators (to see names run with higher pack verbosity)
|
||||
Finished loading packed FPGA netlist file (took 0.01 seconds).
|
||||
Finished loading packed FPGA netlist file (took 0.02 seconds).
|
||||
Warning 34: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity).
|
||||
# Load Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.1 MiB)
|
||||
# Load Packing took 0.02 seconds (max_rss 10.6 MiB, delta_rss +0.1 MiB)
|
||||
Warning 35: Netlist contains 0 global net to non-global architecture pin connections
|
||||
|
||||
Netlist num_nets: 3
|
||||
|
|
@ -326,7 +326,7 @@ Warning 47: in check_rr_node: RR node: 328 type: OPIN location: (2,1) pin: 51 pi
|
|||
RR Graph Edges: 2428
|
||||
### Computing delta delays
|
||||
### Computing delta delays took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.0 MiB)
|
||||
## Computing placement delta delay look-up took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.3 MiB)
|
||||
## Computing placement delta delay look-up took 0.01 seconds (max_rss 11.5 MiB, delta_rss +0.3 MiB)
|
||||
|
||||
There are 3 point to point connections in this circuit.
|
||||
|
||||
|
|
@ -562,9 +562,9 @@ Setup slack histogram:
|
|||
[ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
|
||||
[ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
|
||||
|
||||
Timing analysis took 0.000428495 seconds (0.000379131 STA, 4.9364e-05 slack) (54 full updates: 51 setup, 0 hold, 3 combined).
|
||||
Timing analysis took 0.000465 seconds (0.000410914 STA, 5.4086e-05 slack) (54 full updates: 51 setup, 0 hold, 3 combined).
|
||||
VPR suceeded
|
||||
The entire flow of VPR took 0.09 seconds (max_rss 11.9 MiB)
|
||||
The entire flow of VPR took 0.10 seconds (max_rss 11.9 MiB)
|
||||
|
||||
Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml
|
||||
|
||||
|
|
@ -729,13 +729,13 @@ Command line to execute: repack
|
|||
Confirm selected options when call command 'repack':
|
||||
--verbose: off
|
||||
Build routing resource graph for the physical implementation of logical tile
|
||||
Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.3 MiB)
|
||||
Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.5 MiB, delta_rss +0.3 MiB)
|
||||
Repack clustered blocks to physical implementation of logical tile
|
||||
Repack clustered block 'c'...Done
|
||||
Repack clustered block 'out:c'...Done
|
||||
Repack clustered block 'a'...Done
|
||||
Repack clustered block 'b'...Done
|
||||
Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB)
|
||||
Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.5 MiB, delta_rss +0.0 MiB)
|
||||
Build truth tables for physical LUTs
|
||||
Build truth tables for physical LUTs took 0.00 seconds (max_rss 17.8 MiB, delta_rss +0.3 MiB)
|
||||
|
||||
|
|
@ -777,7 +777,7 @@ Confirm selected options when call command 'write_fabric_bitstream':
|
|||
--verbose: off
|
||||
Warning 57: Directory path is empty and nothing will be created.
|
||||
Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit'
|
||||
Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.00 seconds (max_rss 18.1 MiB, delta_rss +0.0 MiB)
|
||||
Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.01 seconds (max_rss 18.1 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml
|
||||
|
||||
|
|
@ -849,7 +849,7 @@ Building physical tiles...Done
|
|||
Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done
|
||||
Written 73 Verilog modules in total
|
||||
Write Verilog netlists for FPGA fabric
|
||||
took 0.16 seconds (max_rss 18.3 MiB, delta_rss +0.2 MiB)
|
||||
took 0.19 seconds (max_rss 18.3 MiB, delta_rss +0.2 MiB)
|
||||
|
||||
Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
|
||||
|
||||
|
|
@ -869,7 +869,7 @@ Write Verilog testbenches for FPGA fabric
|
|||
|
||||
Warning 60: Directory './SRC' already exists. Will overwrite contents
|
||||
# Write pre-configured FPGA top-level Verilog netlist for design 'top'
|
||||
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.01 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
|
||||
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.02 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
|
||||
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top'
|
||||
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
|
||||
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top'
|
||||
|
|
@ -879,7 +879,7 @@ Succeed to create directory './SimulationDeck'
|
|||
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini'
|
||||
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
|
||||
Write Verilog testbenches for FPGA fabric
|
||||
took 0.04 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
|
||||
took 0.05 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: exit
|
||||
|
||||
|
|
@ -887,6 +887,6 @@ Confirm selected options when call command 'exit':
|
|||
|
||||
Finish execution with 0 errors
|
||||
|
||||
The entire OpenFPGA flow took 0.25 seconds
|
||||
The entire OpenFPGA flow took 0.29 seconds
|
||||
|
||||
Thank you for using OpenFPGA!
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
set DIE_HEIGHT 1000
|
||||
set DIE_WIDTH 1000
|
||||
set DIE_HEIGHT 700
|
||||
set DIE_WIDTH 700
|
||||
set DESIGN_NAME fpga_core
|
||||
set TASK_NAME FPGA22_HIER_SKY_task
|
||||
set VERILOG_PROJ_DIR FPGA22_HIER_SKY_Verilog
|
||||
|
|
@ -7,6 +7,7 @@ set FPGA_ROW 2
|
|||
set FPGA_COL 2
|
||||
set INIT_DESIGN_INPUT DP_RM_NDM
|
||||
set TECHNOLOGY skywater
|
||||
set DP_BLOCK_REFS [list sb_0__0_ sb_0__1_ sb_0__2_ sb_1__0_ sb_1__1_ sb_1__2_ sb_2__0_ sb_2__1_ sb_2__2_ cbx_1__0_ cbx_1__1_ cbx_1__2_ cby_0__1_ cby_1__1_ grid_clb grid_io_bottom grid_io_left grid_io_right grid_io_top];
|
||||
set DP_BLOCK_REFS [list sb_0__0_ sb_0__1_ sb_0__2_ sb_1__0_ sb_1__1_ sb_1__2_ sb_2__0_ sb_2__1_ sb_2__2_ cbx_1__0_ cbx_1__1_ cbx_1__2_ cby_0__1_ cby_1__1_ cby_2__1_ grid_clb];
|
||||
set DP_FLOW "hier";
|
||||
set DESIGN_STYLE "hier";
|
||||
set STANDARD_CELLS sc_hd;
|
||||
|
|
|
|||
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BIN
FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds (Stored with Git LFS)
BIN
FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds (Stored with Git LFS)
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BIN
FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef (Stored with Git LFS)
BIN
FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef (Stored with Git LFS)
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|
|
@ -1,18 +1,18 @@
|
|||
| Module | Util| Area| Sites| Insts| Std_Cells
|
||||
|--------------------|----------|-----------------|-------|-------|-------
|
||||
| sb_0__0_ | 37.06 | 6606.336000 | 5280 | 1 | 85
|
||||
| sb_0__1_ | 61.64 | 7687.372800 | 6144 | 1 | 116
|
||||
| sb_0__2_ | 42.08 | 6606.336000 | 5280 | 1 | 85
|
||||
| sb_1__0_ | 64.92 | 7807.488000 | 6240 | 1 | 125
|
||||
| sb_1__1_ | 81.63 | 8888.524800 | 7104 | 1 | 117
|
||||
| sb_1__2_ | 69.36 | 7807.488000 | 6240 | 1 | 136
|
||||
| sb_2__0_ | 50.93 | 6606.336000 | 5280 | 1 | 94
|
||||
| sb_2__1_ | 73.86 | 7687.372800 | 6144 | 1 | 123
|
||||
| sb_2__2_ | 58.11 | 6606.336000 | 5280 | 1 | 95
|
||||
| cbx_1__0_ | 60.07 | 5044.838400 | 4032 | 2 | 130
|
||||
| cbx_1__1_ | 79.61 | 5044.838400 | 4032 | 2 | 86
|
||||
| cbx_1__2_ | 81.82 | 5044.838400 | 4032 | 2 | 82
|
||||
| cby_0__1_ | 30.11 | 5044.838400 | 4032 | 2 | 109
|
||||
| cby_1__1_ | 80.46 | 5044.838400 | 4032 | 2 | 88
|
||||
| cby_2__1_ | 67.51 | 5044.838400 | 4032 | 2 | 38
|
||||
| grid_clb_1__1_ | 75.03 | 12411.904000 | 9920 | 4 | 56
|
||||
| sb_0__0_ | 39.51 | 6426.163200 | 5136 | 1 | 93
|
||||
| sb_0__1_ | 67.8 | 7086.796800 | 5664 | 1 | 119
|
||||
| sb_0__2_ | 41.69 | 6426.163200 | 5136 | 1 | 83
|
||||
| sb_1__0_ | 61.56 | 8227.891200 | 6576 | 1 | 132
|
||||
| sb_1__1_ | 81.35 | 8888.524800 | 7104 | 1 | 116
|
||||
| sb_1__2_ | 65.88 | 8227.891200 | 6576 | 1 | 133
|
||||
| sb_2__0_ | 56.8 | 6426.163200 | 5136 | 1 | 103
|
||||
| sb_2__1_ | 76.61 | 7086.796800 | 5664 | 1 | 109
|
||||
| sb_2__2_ | 59.11 | 6426.163200 | 5136 | 1 | 89
|
||||
| cbx_1__0_ | 65.82 | 4444.262400 | 3552 | 2 | 115
|
||||
| cbx_1__1_ | 70.58 | 4444.262400 | 3552 | 2 | 36
|
||||
| cbx_1__2_ | 75.73 | 4444.262400 | 3552 | 2 | 38
|
||||
| cby_0__1_ | 31.85 | 4624.435200 | 3696 | 2 | 100
|
||||
| cby_1__1_ | 66.96 | 4624.435200 | 3696 | 2 | 34
|
||||
| cby_2__1_ | 72.89 | 4624.435200 | 3696 | 2 | 38
|
||||
| grid_clb_1__1_ | 76.09 | 12071.577600 | 9648 | 4 | 63
|
||||
|
|
|
|||
|
|
|
@ -0,0 +1,27 @@
|
|||
Ref Name Total Area Utilization_% Instance Count
|
||||
------------------------------------------------------------------------------------
|
||||
sky130_fd_sc_hd__mux2_1 32250.931200 6.62 2864
|
||||
sky130_fd_sc_hd__dfxbp_1 19755.196800 4.06 831
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 4604.416000 0.95 368
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 4579.392000 0.94 366
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 3275.641600 0.67 374
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 2682.572800 0.55 268
|
||||
sky130_fd_sc_hd__buf_4 2169.580800 0.45 289
|
||||
sky130_fd_sc_hd__sdfxtp_1 1051.008000 0.22 40
|
||||
sky130_fd_sc_hd__buf_6 1035.993600 0.21 92
|
||||
sky130_fd_sc_hd__buf_2 410.393600 0.08 82
|
||||
sky130_fd_sc_hd__dlygate4sd1_1 385.369600 0.08 44
|
||||
sky130_fd_sc_hd__inv_1 360.345600 0.07 96
|
||||
sky130_fd_sc_hd__mux2_8 289.027200 0.06 11
|
||||
sky130_fd_sc_hd__or2_0 200.192000 0.04 32
|
||||
sky130_fd_sc_hd__clkbuf_8 192.684800 0.04 14
|
||||
sky130_fd_sc_hd__conb_1 187.680000 0.04 50
|
||||
sky130_fd_sc_hd__clkinvlp_2 65.062400 0.01 13
|
||||
sky130_fd_sc_hd__bufinv_8 35.033600 0.01 2
|
||||
sky130_fd_sc_hd__bufinv_16 30.028800 0.01 1
|
||||
sky130_fd_sc_hd__clkinv_16 30.028800 0.01 1
|
||||
sky130_fd_sc_hd__mux2_4 30.028800 0.01 2
|
||||
sky130_fd_sc_hd__clkbuf_1 7.507200 0.00 2
|
||||
FPGA_BBOX_AREA 189421.6704
|
||||
CORE_BBOX_AREA 486866.944
|
||||
FPGA_BBOX_UTIL 38.90625
|
||||
|
Can't render this file because it has a wrong number of fields in line 2.
|
|
|
@ -6,7 +6,7 @@ Report : clock timing
|
|||
-setup
|
||||
Design : fpga_core
|
||||
Version: P-2019.03-SP4
|
||||
Date : Fri Nov 6 22:19:36 2020
|
||||
Date : Sat Nov 7 23:46:49 2020
|
||||
****************************************
|
||||
Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050)
|
||||
|
||||
|
|
@ -16,7 +16,7 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
|
|||
--- Latency ---
|
||||
Clock Pin Trans Source Offset Network Total Corner
|
||||
---------------------------------------------------------------------------------------------------
|
||||
grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.061 0.000 -- 0.039 0.039 rp-+ nominal
|
||||
grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.080 0.000 -- 0.051 0.051 rp-+ nominal
|
||||
---------------------------------------------------------------------------------------------------
|
||||
|
||||
Mode: full_chip
|
||||
|
|
@ -25,7 +25,7 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
|
|||
--- Latency ---
|
||||
Clock Pin Trans Source Offset Network Total Corner
|
||||
---------------------------------------------------------------------------------------------------
|
||||
grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 3.187 0.000 -- 5.545 5.545 rp-+ nominal
|
||||
grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxbp_1_0_/CLK 2.855 0.000 -- 6.358 6.358 rp-+ nominal
|
||||
---------------------------------------------------------------------------------------------------
|
||||
****************************************
|
||||
Report : clock timing
|
||||
|
|
@ -34,7 +34,7 @@ Report : clock timing
|
|||
-setup
|
||||
Design : fpga_core
|
||||
Version: P-2019.03-SP4
|
||||
Date : Fri Nov 6 22:19:36 2020
|
||||
Date : Sat Nov 7 23:46:49 2020
|
||||
****************************************
|
||||
Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050)
|
||||
|
||||
|
|
@ -43,8 +43,8 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
|
|||
|
||||
Clock Pin Latency CRP Skew Corner
|
||||
---------------------------------------------------------------------------------------------------
|
||||
grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.032 rp-+ nominal
|
||||
grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.020 0.000 0.011 rp-+ nominal
|
||||
grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.051 rp-+ nominal
|
||||
grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.026 0.000 0.024 rp-+ nominal
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
|
||||
|
|
@ -53,8 +53,8 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
|
|||
|
||||
Clock Pin Latency CRP Skew Corner
|
||||
---------------------------------------------------------------------------------------------------
|
||||
sb_1__2_/mem_left_track_33/sky130_fd_sc_hd__dfxbp_1_2_/CLK 5.061 rp-+ nominal
|
||||
cbx_1__2_/mem_bottom_ipin_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 3.276 0.000 1.785 rp-+ nominal
|
||||
grid_clb_1__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxbp_1_1_/CLK 5.290 rp-+ nominal
|
||||
cby_1__2_/mem_right_ipin_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 3.099 0.000 2.191 rp-+ nominal
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050)
|
||||
|
|
@ -63,7 +63,7 @@ Report : global timing
|
|||
-format { narrow }
|
||||
Design : fpga_core
|
||||
Version: P-2019.03-SP4
|
||||
Date : Fri Nov 6 22:19:36 2020
|
||||
Date : Sat Nov 7 23:46:49 2020
|
||||
****************************************
|
||||
|
||||
No setup violations found.
|
||||
|
|
@ -73,8 +73,8 @@ Hold violations
|
|||
--------------------------------------------------------------
|
||||
Total reg->reg in->reg reg->out in->out
|
||||
--------------------------------------------------------------
|
||||
WNS -0.632 -0.632 0.000 0.000 0.000
|
||||
TNS -0.750 -0.750 0.000 0.000 0.000
|
||||
WNS -2.785 -2.785 0.000 0.000 0.000
|
||||
TNS -3.014 -3.014 0.000 0.000 0.000
|
||||
NUM 2 2 0 0 0
|
||||
--------------------------------------------------------------
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue