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[HDL] Bug fix in custom cell code generator

This commit is contained in:
tangxifan 2020-12-06 11:28:37 -07:00
parent da08e505b5
commit 21a4928002
1 changed files with 16 additions and 6 deletions
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22
HDL/common/custom_cell_mux_primitive_generator.py
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@ -94,6 +94,20 @@ def generate_verilog_codes_custom_cell_mux2(first_input_index, instance_index):
return lines return lines
#######################################################################
# A function to generate Verilog codes for a MUX2 standard cell
# Given an input index
def generate_verilog_codes_standard_cell_mux2(first_input_index, instance_index):
lines = []
lines.append("\tsky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_" + str(instance_index) + "(")
lines.append("\t .A1(in[" + str(first_input_index) + "]),")
lines.append("\t .A0(in[" + str(first_input_index + 1) + "]),")
lines.append("\t .S(mem[" + str(first_input_index) + "]),")
lines.append("\t .X(out[0])")
lines.append("\t );")
return lines
####################################################################### #######################################################################
# A function to output custom cells of multiplexing structure to a file # A function to output custom cells of multiplexing structure to a file
@ -107,12 +121,8 @@ def write_custom_mux_cells_to_file(custom_nlist, input_size, mem_size):
if (1 == mem_size): if (1 == mem_size):
assert(2 == input_size) assert(2 == input_size)
# Output a standard cell, currently we support HD cell MUX2 # Output a standard cell, currently we support HD cell MUX2
lines.append("\tsky130_fd_sc_hd_mux2_1 sky130_fd_sc_hd_mux2_1_0(") for line in generate_verilog_codes_standard_cell_mux2(0, 0):
lines.append("\t .A1(in[0]),") lines.append(line)
lines.append("\t .A0(in[1]),")
lines.append("\t .S(mem[0]),")
lines.append("\t .X(out[0])")
lines.append("\t );")
else: else:
assert(1 < mem_size) assert(1 < mem_size)
assert(mem_size == input_size) assert(mem_size == input_size)