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diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef
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index 0000000..4418009
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef
@@ -0,0 +1,1787 @@
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+
+UNITS
+  DATABASE MICRONS 1000 ;
+END UNITS
+
+MANUFACTURINGGRID 0.005 ;
+
+LAYER li1
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.17 ;
+END li1
+
+LAYER mcon
+  TYPE CUT ;
+END mcon
+
+LAYER met1
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.34 ;
+  WIDTH 0.14 ;
+END met1
+
+LAYER via
+  TYPE CUT ;
+END via
+
+LAYER met2
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.14 ;
+END met2
+
+LAYER via2
+  TYPE CUT ;
+END via2
+
+LAYER met3
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.68 ;
+  WIDTH 0.3 ;
+END met3
+
+LAYER via3
+  TYPE CUT ;
+END via3
+
+LAYER met4
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.92 ;
+  WIDTH 0.3 ;
+END met4
+
+LAYER via4
+  TYPE CUT ;
+END via4
+
+LAYER met5
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 3.4 ;
+  WIDTH 1.6 ;
+END met5
+
+LAYER nwell
+  TYPE MASTERSLICE ;
+END nwell
+
+LAYER pwell
+  TYPE MASTERSLICE ;
+END pwell
+
+LAYER OVERLAP
+  TYPE OVERLAP ;
+END OVERLAP
+
+VIA L1M1_PR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR
+
+VIA L1M1_PR_R
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_R
+
+VIA L1M1_PR_M
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_M
+
+VIA L1M1_PR_MR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR_MR
+
+VIA L1M1_PR_C
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.145 0.145 0.145 ;
+END L1M1_PR_C
+
+VIA M1M2_PR
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR
+
+VIA M1M2_PR_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_Enc
+
+VIA M1M2_PR_R
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_R
+
+VIA M1M2_PR_R_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_R_Enc
+
+VIA M1M2_PR_M
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIA M1M2_PR_M_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_M_Enc
+
+VIA M1M2_PR_MR
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIA M1M2_PR_MR_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_MR_Enc
+
+VIA M1M2_PR_C
+  LAYER met1 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIA M2M3_PR
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIA M2M3_PR_R
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIA M2M3_PR_M
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIA M2M3_PR_MR
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIA M2M3_PR_C
+  LAYER met2 ;
+    RECT -0.185 -0.185 0.185 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIA M3M4_PR
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIA M3M4_PR_R
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIA M3M4_PR_M
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIA M3M4_PR_MR
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIA M3M4_PR_C
+  LAYER met3 ;
+    RECT -0.19 -0.19 0.19 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIA M4M5_PR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIA M4M5_PR_R
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIA M4M5_PR_M
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIA M4M5_PR_MR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIA M4M5_PR_C
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+  CLASS CORE ;
+  SYMMETRY Y ;
+  SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+  CLASS CORE ;
+  SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+MACRO cbx_1__0_
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 66.24 BY 87.04 ;
+  SYMMETRY X Y ;
+  PIN chanx_left_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 69.55 0.8 69.85 ;
+    END
+  END chanx_left_in[0]
+  PIN chanx_left_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 52.55 0.8 52.85 ;
+    END
+  END chanx_left_in[1]
+  PIN chanx_left_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 47.11 0.8 47.41 ;
+    END
+  END chanx_left_in[2]
+  PIN chanx_left_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 65.47 0.8 65.77 ;
+    END
+  END chanx_left_in[3]
+  PIN chanx_left_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 36.91 0.8 37.21 ;
+    END
+  END chanx_left_in[4]
+  PIN chanx_left_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 15.83 0.8 16.13 ;
+    END
+  END chanx_left_in[5]
+  PIN chanx_left_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 68.19 0.8 68.49 ;
+    END
+  END chanx_left_in[6]
+  PIN chanx_left_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 62.07 0.8 62.37 ;
+    END
+  END chanx_left_in[7]
+  PIN chanx_left_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 55.27 0.8 55.57 ;
+    END
+  END chanx_left_in[8]
+  PIN chanx_left_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 74.31 0.8 74.61 ;
+    END
+  END chanx_left_in[9]
+  PIN chanx_left_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 31.47 0.8 31.77 ;
+    END
+  END chanx_left_in[10]
+  PIN chanx_left_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 23.99 0.8 24.29 ;
+    END
+  END chanx_left_in[11]
+  PIN chanx_left_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 64.11 0.8 64.41 ;
+    END
+  END chanx_left_in[12]
+  PIN chanx_left_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 81.79 0.8 82.09 ;
+    END
+  END chanx_left_in[13]
+  PIN chanx_left_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 80.43 0.8 80.73 ;
+    END
+  END chanx_left_in[14]
+  PIN chanx_left_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 83.15 0.8 83.45 ;
+    END
+  END chanx_left_in[15]
+  PIN chanx_left_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 35.55 0.8 35.85 ;
+    END
+  END chanx_left_in[16]
+  PIN chanx_left_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 45.75 0.8 46.05 ;
+    END
+  END chanx_left_in[17]
+  PIN chanx_left_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 38.27 0.8 38.57 ;
+    END
+  END chanx_left_in[18]
+  PIN chanx_left_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 34.19 0.8 34.49 ;
+    END
+  END chanx_left_in[19]
+  PIN chanx_right_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 53.23 66.24 53.53 ;
+    END
+  END chanx_right_in[0]
+  PIN chanx_right_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 74.99 66.24 75.29 ;
+    END
+  END chanx_right_in[1]
+  PIN chanx_right_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 54.59 66.24 54.89 ;
+    END
+  END chanx_right_in[2]
+  PIN chanx_right_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 44.39 66.24 44.69 ;
+    END
+  END chanx_right_in[3]
+  PIN chanx_right_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 77.03 66.24 77.33 ;
+    END
+  END chanx_right_in[4]
+  PIN chanx_right_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 31.47 66.24 31.77 ;
+    END
+  END chanx_right_in[5]
+  PIN chanx_right_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 69.55 66.24 69.85 ;
+    END
+  END chanx_right_in[6]
+  PIN chanx_right_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 18.55 66.24 18.85 ;
+    END
+  END chanx_right_in[7]
+  PIN chanx_right_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 34.19 66.24 34.49 ;
+    END
+  END chanx_right_in[8]
+  PIN chanx_right_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 66.83 66.24 67.13 ;
+    END
+  END chanx_right_in[9]
+  PIN chanx_right_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 43.03 66.24 43.33 ;
+    END
+  END chanx_right_in[10]
+  PIN chanx_right_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 39.63 66.24 39.93 ;
+    END
+  END chanx_right_in[11]
+  PIN chanx_right_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 35.55 66.24 35.85 ;
+    END
+  END chanx_right_in[12]
+  PIN chanx_right_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 72.27 66.24 72.57 ;
+    END
+  END chanx_right_in[13]
+  PIN chanx_right_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 79.75 66.24 80.05 ;
+    END
+  END chanx_right_in[14]
+  PIN chanx_right_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 83.15 66.24 83.45 ;
+    END
+  END chanx_right_in[15]
+  PIN chanx_right_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 17.19 66.24 17.49 ;
+    END
+  END chanx_right_in[16]
+  PIN chanx_right_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 28.07 66.24 28.37 ;
+    END
+  END chanx_right_in[17]
+  PIN chanx_right_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 41.67 66.24 41.97 ;
+    END
+  END chanx_right_in[18]
+  PIN chanx_right_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 70.91 66.24 71.21 ;
+    END
+  END chanx_right_in[19]
+  PIN ccff_head[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 81.11 66.24 81.41 ;
+    END
+  END ccff_head[0]
+  PIN chanx_left_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 66.83 0.8 67.13 ;
+    END
+  END chanx_left_out[0]
+  PIN chanx_left_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 77.71 0.8 78.01 ;
+    END
+  END chanx_left_out[1]
+  PIN chanx_left_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 75.67 0.8 75.97 ;
+    END
+  END chanx_left_out[2]
+  PIN chanx_left_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 59.35 0.8 59.65 ;
+    END
+  END chanx_left_out[3]
+  PIN chanx_left_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 57.99 0.8 58.29 ;
+    END
+  END chanx_left_out[4]
+  PIN chanx_left_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 79.07 0.8 79.37 ;
+    END
+  END chanx_left_out[5]
+  PIN chanx_left_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 48.47 0.8 48.77 ;
+    END
+  END chanx_left_out[6]
+  PIN chanx_left_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 60.71 0.8 61.01 ;
+    END
+  END chanx_left_out[7]
+  PIN chanx_left_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 25.35 0.8 25.65 ;
+    END
+  END chanx_left_out[8]
+  PIN chanx_left_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 22.63 0.8 22.93 ;
+    END
+  END chanx_left_out[9]
+  PIN chanx_left_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 43.03 0.8 43.33 ;
+    END
+  END chanx_left_out[10]
+  PIN chanx_left_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 39.63 0.8 39.93 ;
+    END
+  END chanx_left_out[11]
+  PIN chanx_left_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 29.43 0.8 29.73 ;
+    END
+  END chanx_left_out[12]
+  PIN chanx_left_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 44.39 0.8 44.69 ;
+    END
+  END chanx_left_out[13]
+  PIN chanx_left_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 26.71 0.8 27.01 ;
+    END
+  END chanx_left_out[14]
+  PIN chanx_left_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 49.83 0.8 50.13 ;
+    END
+  END chanx_left_out[15]
+  PIN chanx_left_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 28.07 0.8 28.37 ;
+    END
+  END chanx_left_out[16]
+  PIN chanx_left_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 13.11 0.8 13.41 ;
+    END
+  END chanx_left_out[17]
+  PIN chanx_left_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 41.67 0.8 41.97 ;
+    END
+  END chanx_left_out[18]
+  PIN chanx_left_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 14.47 0.8 14.77 ;
+    END
+  END chanx_left_out[19]
+  PIN chanx_right_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 36.91 66.24 37.21 ;
+    END
+  END chanx_right_out[0]
+  PIN chanx_right_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 21.27 66.24 21.57 ;
+    END
+  END chanx_right_out[1]
+  PIN chanx_right_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 63.43 66.24 63.73 ;
+    END
+  END chanx_right_out[2]
+  PIN chanx_right_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 47.11 66.24 47.41 ;
+    END
+  END chanx_right_out[3]
+  PIN chanx_right_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 45.75 66.24 46.05 ;
+    END
+  END chanx_right_out[4]
+  PIN chanx_right_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 49.83 66.24 50.13 ;
+    END
+  END chanx_right_out[5]
+  PIN chanx_right_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 60.71 66.24 61.01 ;
+    END
+  END chanx_right_out[6]
+  PIN chanx_right_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 55.95 66.24 56.25 ;
+    END
+  END chanx_right_out[7]
+  PIN chanx_right_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 64.79 66.24 65.09 ;
+    END
+  END chanx_right_out[8]
+  PIN chanx_right_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 51.19 66.24 51.49 ;
+    END
+  END chanx_right_out[9]
+  PIN chanx_right_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 29.43 66.24 29.73 ;
+    END
+  END chanx_right_out[10]
+  PIN chanx_right_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 15.83 66.24 16.13 ;
+    END
+  END chanx_right_out[11]
+  PIN chanx_right_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 68.19 66.24 68.49 ;
+    END
+  END chanx_right_out[12]
+  PIN chanx_right_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 48.47 66.24 48.77 ;
+    END
+  END chanx_right_out[13]
+  PIN chanx_right_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 38.27 66.24 38.57 ;
+    END
+  END chanx_right_out[14]
+  PIN chanx_right_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 57.31 66.24 57.61 ;
+    END
+  END chanx_right_out[15]
+  PIN chanx_right_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 62.07 66.24 62.37 ;
+    END
+  END chanx_right_out[16]
+  PIN chanx_right_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 73.63 66.24 73.93 ;
+    END
+  END chanx_right_out[17]
+  PIN chanx_right_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 59.35 66.24 59.65 ;
+    END
+  END chanx_right_out[18]
+  PIN chanx_right_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 78.39 66.24 78.69 ;
+    END
+  END chanx_right_out[19]
+  PIN bottom_grid_pin_0_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 9.03 66.24 9.33 ;
+    END
+  END bottom_grid_pin_0_[0]
+  PIN bottom_grid_pin_2_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 38.34 0 38.48 0.485 ;
+    END
+  END bottom_grid_pin_2_[0]
+  PIN bottom_grid_pin_4_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 8.59 0 8.89 0.8 ;
+    END
+  END bottom_grid_pin_4_[0]
+  PIN bottom_grid_pin_6_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 6.75 0 7.05 0.8 ;
+    END
+  END bottom_grid_pin_6_[0]
+  PIN bottom_grid_pin_8_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 36.04 0 36.18 0.485 ;
+    END
+  END bottom_grid_pin_8_[0]
+  PIN bottom_grid_pin_10_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 4.91 0 5.21 0.8 ;
+    END
+  END bottom_grid_pin_10_[0]
+  PIN bottom_grid_pin_12_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 32.82 0 32.96 0.485 ;
+    END
+  END bottom_grid_pin_12_[0]
+  PIN bottom_grid_pin_14_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 9.82 0 9.96 0.485 ;
+    END
+  END bottom_grid_pin_14_[0]
+  PIN bottom_grid_pin_16_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 3.59 0.8 3.89 ;
+    END
+  END bottom_grid_pin_16_[0]
+  PIN ccff_tail[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 51.19 0.8 51.49 ;
+    END
+  END ccff_tail[0]
+  PIN IO_ISOL_N[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 3.38 86.555 3.52 87.04 ;
+    END
+  END IO_ISOL_N[0]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 14.42 0 14.56 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 15.34 0 15.48 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 29.14 0 29.28 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 30.98 0 31.12 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 16.26 0 16.4 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 10.74 0 10.88 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 6.6 0 6.74 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 5.68 0 5.82 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 12.12 0 12.26 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 23.16 0 23.3 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 26.38 0 26.52 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 35.12 0 35.26 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 30.06 0 30.2 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 28.22 0 28.36 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 19.48 0 19.62 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 18.56 0 18.7 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 3.84 0 3.98 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.98 0 8.12 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 17.18 0 17.32 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 21.78 0 21.92 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 27.3 0 27.44 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 24.54 0 24.68 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 20.86 0 21 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.5 0 13.64 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 8.9 0 9.04 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 2.46 0 2.6 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 4.76 0 4.9 0.485 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8]
+  PIN top_width_0_height_0__pin_0_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 10.39 66.24 10.69 ;
+    END
+  END top_width_0_height_0__pin_0_[0]
+  PIN top_width_0_height_0__pin_2_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 39.26 0 39.4 0.485 ;
+    END
+  END top_width_0_height_0__pin_2_[0]
+  PIN top_width_0_height_0__pin_4_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 4.95 0.8 5.25 ;
+    END
+  END top_width_0_height_0__pin_4_[0]
+  PIN top_width_0_height_0__pin_6_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 6.31 0.8 6.61 ;
+    END
+  END top_width_0_height_0__pin_6_[0]
+  PIN top_width_0_height_0__pin_8_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 34.2 0 34.34 0.485 ;
+    END
+  END top_width_0_height_0__pin_8_[0]
+  PIN top_width_0_height_0__pin_10_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 9.03 0.8 9.33 ;
+    END
+  END top_width_0_height_0__pin_10_[0]
+  PIN top_width_0_height_0__pin_12_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 31.9 0 32.04 0.485 ;
+    END
+  END top_width_0_height_0__pin_12_[0]
+  PIN top_width_0_height_0__pin_14_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 10.39 0.8 10.69 ;
+    END
+  END top_width_0_height_0__pin_14_[0]
+  PIN top_width_0_height_0__pin_16_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 11.75 0.8 12.05 ;
+    END
+  END top_width_0_height_0__pin_16_[0]
+  PIN top_width_0_height_0__pin_1_upper[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 53.91 0.8 54.21 ;
+    END
+  END top_width_0_height_0__pin_1_upper[0]
+  PIN top_width_0_height_0__pin_1_lower[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 26.71 66.24 27.01 ;
+    END
+  END top_width_0_height_0__pin_1_lower[0]
+  PIN top_width_0_height_0__pin_3_upper[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 72.95 0.8 73.25 ;
+    END
+  END top_width_0_height_0__pin_3_upper[0]
+  PIN top_width_0_height_0__pin_3_lower[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 25.35 66.24 25.65 ;
+    END
+  END top_width_0_height_0__pin_3_lower[0]
+  PIN top_width_0_height_0__pin_5_upper[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 70.91 0.8 71.21 ;
+    END
+  END top_width_0_height_0__pin_5_upper[0]
+  PIN top_width_0_height_0__pin_5_lower[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 14.47 66.24 14.77 ;
+    END
+  END top_width_0_height_0__pin_5_lower[0]
+  PIN top_width_0_height_0__pin_7_upper[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 32.83 0.8 33.13 ;
+    END
+  END top_width_0_height_0__pin_7_upper[0]
+  PIN top_width_0_height_0__pin_7_lower[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 32.83 66.24 33.13 ;
+    END
+  END top_width_0_height_0__pin_7_lower[0]
+  PIN top_width_0_height_0__pin_9_upper[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 18.55 0.8 18.85 ;
+    END
+  END top_width_0_height_0__pin_9_upper[0]
+  PIN top_width_0_height_0__pin_9_lower[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 13.11 66.24 13.41 ;
+    END
+  END top_width_0_height_0__pin_9_lower[0]
+  PIN top_width_0_height_0__pin_11_upper[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 56.63 0.8 56.93 ;
+    END
+  END top_width_0_height_0__pin_11_upper[0]
+  PIN top_width_0_height_0__pin_11_lower[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 23.99 66.24 24.29 ;
+    END
+  END top_width_0_height_0__pin_11_lower[0]
+  PIN top_width_0_height_0__pin_13_upper[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 19.91 0.8 20.21 ;
+    END
+  END top_width_0_height_0__pin_13_upper[0]
+  PIN top_width_0_height_0__pin_13_lower[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 22.63 66.24 22.93 ;
+    END
+  END top_width_0_height_0__pin_13_lower[0]
+  PIN top_width_0_height_0__pin_15_upper[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 17.19 0.8 17.49 ;
+    END
+  END top_width_0_height_0__pin_15_upper[0]
+  PIN top_width_0_height_0__pin_15_lower[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 11.75 66.24 12.05 ;
+    END
+  END top_width_0_height_0__pin_15_lower[0]
+  PIN top_width_0_height_0__pin_17_upper[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 21.27 0.8 21.57 ;
+    END
+  END top_width_0_height_0__pin_17_upper[0]
+  PIN top_width_0_height_0__pin_17_lower[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 19.91 66.24 20.21 ;
+    END
+  END top_width_0_height_0__pin_17_lower[0]
+  PIN SC_IN_TOP
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.8 86.555 61.94 87.04 ;
+    END
+  END SC_IN_TOP
+  PIN SC_OUT_BOT
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.64 86.555 63.78 87.04 ;
+    END
+  END SC_OUT_BOT
+  PIN SC_IN_BOT
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 2.46 86.555 2.6 87.04 ;
+    END
+  END SC_IN_BOT
+  PIN SC_OUT_TOP
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 16.26 86.555 16.4 87.04 ;
+    END
+  END SC_OUT_TOP
+  PIN prog_clk_0_N_in
+    DIRECTION INPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met2 ;
+        RECT 24.54 86.555 24.68 87.04 ;
+    END
+  END prog_clk_0_N_in
+  PIN prog_clk_0_W_out
+    DIRECTION OUTPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met3 ;
+        RECT 0 7.67 0.8 7.97 ;
+    END
+  END prog_clk_0_W_out
+  PIN VDD
+    DIRECTION INPUT ;
+    USE POWER ;
+    PORT
+      LAYER met1 ;
+        RECT 0 2.48 0.48 2.96 ;
+        RECT 65.76 2.48 66.24 2.96 ;
+        RECT 0 7.92 0.48 8.4 ;
+        RECT 65.76 7.92 66.24 8.4 ;
+        RECT 0 13.36 0.48 13.84 ;
+        RECT 65.76 13.36 66.24 13.84 ;
+        RECT 0 18.8 0.48 19.28 ;
+        RECT 65.76 18.8 66.24 19.28 ;
+        RECT 0 24.24 0.48 24.72 ;
+        RECT 65.76 24.24 66.24 24.72 ;
+        RECT 0 29.68 0.48 30.16 ;
+        RECT 65.76 29.68 66.24 30.16 ;
+        RECT 0 35.12 0.48 35.6 ;
+        RECT 65.76 35.12 66.24 35.6 ;
+        RECT 0 40.56 0.48 41.04 ;
+        RECT 65.76 40.56 66.24 41.04 ;
+        RECT 0 46 0.48 46.48 ;
+        RECT 65.76 46 66.24 46.48 ;
+        RECT 0 51.44 0.48 51.92 ;
+        RECT 65.76 51.44 66.24 51.92 ;
+        RECT 0 56.88 0.48 57.36 ;
+        RECT 65.76 56.88 66.24 57.36 ;
+        RECT 0 62.32 0.48 62.8 ;
+        RECT 65.76 62.32 66.24 62.8 ;
+        RECT 0 67.76 0.48 68.24 ;
+        RECT 65.76 67.76 66.24 68.24 ;
+        RECT 0 73.2 0.48 73.68 ;
+        RECT 65.76 73.2 66.24 73.68 ;
+        RECT 0 78.64 0.48 79.12 ;
+        RECT 65.76 78.64 66.24 79.12 ;
+        RECT 0 84.08 0.48 84.56 ;
+        RECT 65.76 84.08 66.24 84.56 ;
+      LAYER met4 ;
+        RECT 10.74 0 11.34 0.6 ;
+        RECT 40.18 0 40.78 0.6 ;
+        RECT 10.74 86.44 11.34 87.04 ;
+        RECT 40.18 86.44 40.78 87.04 ;
+      LAYER met5 ;
+        RECT 0 11.32 3.2 14.52 ;
+        RECT 63.04 11.32 66.24 14.52 ;
+        RECT 0 52.12 3.2 55.32 ;
+        RECT 63.04 52.12 66.24 55.32 ;
+    END
+  END VDD
+  PIN VSS
+    DIRECTION INPUT ;
+    USE GROUND ;
+    PORT
+      LAYER met1 ;
+        RECT 0 0 45.4 0.24 ;
+        RECT 46.6 0 66.24 0.24 ;
+        RECT 0 5.2 0.48 5.68 ;
+        RECT 65.76 5.2 66.24 5.68 ;
+        RECT 0 10.64 0.48 11.12 ;
+        RECT 65.76 10.64 66.24 11.12 ;
+        RECT 0 16.08 0.48 16.56 ;
+        RECT 65.76 16.08 66.24 16.56 ;
+        RECT 0 21.52 0.48 22 ;
+        RECT 65.76 21.52 66.24 22 ;
+        RECT 0 26.96 0.48 27.44 ;
+        RECT 65.76 26.96 66.24 27.44 ;
+        RECT 0 32.4 0.48 32.88 ;
+        RECT 65.76 32.4 66.24 32.88 ;
+        RECT 0 37.84 0.48 38.32 ;
+        RECT 65.76 37.84 66.24 38.32 ;
+        RECT 0 43.28 0.48 43.76 ;
+        RECT 65.76 43.28 66.24 43.76 ;
+        RECT 0 48.72 0.48 49.2 ;
+        RECT 65.76 48.72 66.24 49.2 ;
+        RECT 0 54.16 0.48 54.64 ;
+        RECT 65.76 54.16 66.24 54.64 ;
+        RECT 0 59.6 0.48 60.08 ;
+        RECT 65.76 59.6 66.24 60.08 ;
+        RECT 0 65.04 0.48 65.52 ;
+        RECT 65.76 65.04 66.24 65.52 ;
+        RECT 0 70.48 0.48 70.96 ;
+        RECT 65.76 70.48 66.24 70.96 ;
+        RECT 0 75.92 0.48 76.4 ;
+        RECT 65.76 75.92 66.24 76.4 ;
+        RECT 0 81.36 0.48 81.84 ;
+        RECT 65.76 81.36 66.24 81.84 ;
+        RECT 0 86.8 45.4 87.04 ;
+        RECT 46.6 86.8 66.24 87.04 ;
+      LAYER met4 ;
+        RECT 25.46 0 26.06 0.6 ;
+        RECT 54.9 0 55.5 0.6 ;
+        RECT 25.46 86.44 26.06 87.04 ;
+        RECT 54.9 86.44 55.5 87.04 ;
+      LAYER met5 ;
+        RECT 0 31.72 3.2 34.92 ;
+        RECT 63.04 31.72 66.24 34.92 ;
+        RECT 0 72.52 3.2 75.72 ;
+        RECT 63.04 72.52 66.24 75.72 ;
+    END
+  END VSS
+  OBS
+    LAYER met3 ;
+      POLYGON 55.365 87.205 55.365 87.2 55.58 87.2 55.58 86.88 55.365 86.88 55.365 86.875 55.035 86.875 55.035 86.88 54.82 86.88 54.82 87.2 55.035 87.2 55.035 87.205 ;
+      POLYGON 25.925 87.205 25.925 87.2 26.14 87.2 26.14 86.88 25.925 86.88 25.925 86.875 25.595 86.875 25.595 86.88 25.38 86.88 25.38 87.2 25.595 87.2 25.595 87.205 ;
+      POLYGON 11.88 18.17 11.88 17.87 0.65 17.87 0.65 18.15 1.2 18.15 1.2 18.17 ;
+      POLYGON 65.04 15.45 65.04 15.43 65.59 15.43 65.59 15.15 56.2 15.15 56.2 15.45 ;
+      POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ;
+      POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ;
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diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef
new file mode 100644
index 0000000..675ca4a
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef
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+END nwell
+
+LAYER pwell
+  TYPE MASTERSLICE ;
+END pwell
+
+LAYER OVERLAP
+  TYPE OVERLAP ;
+END OVERLAP
+
+VIA L1M1_PR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR
+
+VIA L1M1_PR_R
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_R
+
+VIA L1M1_PR_M
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_M
+
+VIA L1M1_PR_MR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR_MR
+
+VIA L1M1_PR_C
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.145 0.145 0.145 ;
+END L1M1_PR_C
+
+VIA M1M2_PR
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR
+
+VIA M1M2_PR_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_Enc
+
+VIA M1M2_PR_R
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_R
+
+VIA M1M2_PR_R_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_R_Enc
+
+VIA M1M2_PR_M
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIA M1M2_PR_M_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_M_Enc
+
+VIA M1M2_PR_MR
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIA M1M2_PR_MR_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_MR_Enc
+
+VIA M1M2_PR_C
+  LAYER met1 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIA M2M3_PR
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIA M2M3_PR_R
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIA M2M3_PR_M
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIA M2M3_PR_MR
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIA M2M3_PR_C
+  LAYER met2 ;
+    RECT -0.185 -0.185 0.185 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIA M3M4_PR
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIA M3M4_PR_R
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIA M3M4_PR_M
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIA M3M4_PR_MR
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIA M3M4_PR_C
+  LAYER met3 ;
+    RECT -0.19 -0.19 0.19 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIA M4M5_PR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIA M4M5_PR_R
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIA M4M5_PR_M
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIA M4M5_PR_MR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIA M4M5_PR_C
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+  CLASS CORE ;
+  SYMMETRY Y ;
+  SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+  CLASS CORE ;
+  SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+MACRO cbx_1__1_
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 66.24 BY 87.04 ;
+  SYMMETRY X Y ;
+  PIN chanx_left_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 59.35 0.8 59.65 ;
+    END
+  END chanx_left_in[0]
+  PIN chanx_left_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 62.07 0.8 62.37 ;
+    END
+  END chanx_left_in[1]
+  PIN chanx_left_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 14.47 0.8 14.77 ;
+    END
+  END chanx_left_in[2]
+  PIN chanx_left_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 38.95 0.8 39.25 ;
+    END
+  END chanx_left_in[3]
+  PIN chanx_left_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 45.75 0.8 46.05 ;
+    END
+  END chanx_left_in[4]
+  PIN chanx_left_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 43.03 0.8 43.33 ;
+    END
+  END chanx_left_in[5]
+  PIN chanx_left_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 74.31 0.8 74.61 ;
+    END
+  END chanx_left_in[6]
+  PIN chanx_left_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 22.63 0.8 22.93 ;
+    END
+  END chanx_left_in[7]
+  PIN chanx_left_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 21.27 0.8 21.57 ;
+    END
+  END chanx_left_in[8]
+  PIN chanx_left_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 44.39 0.8 44.69 ;
+    END
+  END chanx_left_in[9]
+  PIN chanx_left_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 15.83 0.8 16.13 ;
+    END
+  END chanx_left_in[10]
+  PIN chanx_left_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 41.67 0.8 41.97 ;
+    END
+  END chanx_left_in[11]
+  PIN chanx_left_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 4.95 0.8 5.25 ;
+    END
+  END chanx_left_in[12]
+  PIN chanx_left_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 36.23 0.8 36.53 ;
+    END
+  END chanx_left_in[13]
+  PIN chanx_left_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 19.91 0.8 20.21 ;
+    END
+  END chanx_left_in[14]
+  PIN chanx_left_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 57.99 0.8 58.29 ;
+    END
+  END chanx_left_in[15]
+  PIN chanx_left_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 3.59 0.8 3.89 ;
+    END
+  END chanx_left_in[16]
+  PIN chanx_left_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 48.47 0.8 48.77 ;
+    END
+  END chanx_left_in[17]
+  PIN chanx_left_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 17.19 0.8 17.49 ;
+    END
+  END chanx_left_in[18]
+  PIN chanx_left_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 78.39 0.8 78.69 ;
+    END
+  END chanx_left_in[19]
+  PIN chanx_right_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 13.11 66.24 13.41 ;
+    END
+  END chanx_right_in[0]
+  PIN chanx_right_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 53.91 66.24 54.21 ;
+    END
+  END chanx_right_in[1]
+  PIN chanx_right_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 23.99 66.24 24.29 ;
+    END
+  END chanx_right_in[2]
+  PIN chanx_right_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 44.39 66.24 44.69 ;
+    END
+  END chanx_right_in[3]
+  PIN chanx_right_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 4.95 66.24 5.25 ;
+    END
+  END chanx_right_in[4]
+  PIN chanx_right_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 33.51 66.24 33.81 ;
+    END
+  END chanx_right_in[5]
+  PIN chanx_right_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 22.63 66.24 22.93 ;
+    END
+  END chanx_right_in[6]
+  PIN chanx_right_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 14.47 66.24 14.77 ;
+    END
+  END chanx_right_in[7]
+  PIN chanx_right_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 19.91 66.24 20.21 ;
+    END
+  END chanx_right_in[8]
+  PIN chanx_right_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 38.95 66.24 39.25 ;
+    END
+  END chanx_right_in[9]
+  PIN chanx_right_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 25.35 66.24 25.65 ;
+    END
+  END chanx_right_in[10]
+  PIN chanx_right_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 41.67 66.24 41.97 ;
+    END
+  END chanx_right_in[11]
+  PIN chanx_right_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 6.31 66.24 6.61 ;
+    END
+  END chanx_right_in[12]
+  PIN chanx_right_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 75.67 66.24 75.97 ;
+    END
+  END chanx_right_in[13]
+  PIN chanx_right_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 26.71 66.24 27.01 ;
+    END
+  END chanx_right_in[14]
+  PIN chanx_right_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 17.19 66.24 17.49 ;
+    END
+  END chanx_right_in[15]
+  PIN chanx_right_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 3.59 66.24 3.89 ;
+    END
+  END chanx_right_in[16]
+  PIN chanx_right_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 40.31 66.24 40.61 ;
+    END
+  END chanx_right_in[17]
+  PIN chanx_right_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 21.27 66.24 21.57 ;
+    END
+  END chanx_right_in[18]
+  PIN chanx_right_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 15.83 66.24 16.13 ;
+    END
+  END chanx_right_in[19]
+  PIN ccff_head[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 18.55 66.24 18.85 ;
+    END
+  END ccff_head[0]
+  PIN chanx_left_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 55.27 0.8 55.57 ;
+    END
+  END chanx_left_out[0]
+  PIN chanx_left_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 77.03 0.8 77.33 ;
+    END
+  END chanx_left_out[1]
+  PIN chanx_left_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 25.35 0.8 25.65 ;
+    END
+  END chanx_left_out[2]
+  PIN chanx_left_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 37.59 0.8 37.89 ;
+    END
+  END chanx_left_out[3]
+  PIN chanx_left_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 60.71 0.8 61.01 ;
+    END
+  END chanx_left_out[4]
+  PIN chanx_left_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 75.67 0.8 75.97 ;
+    END
+  END chanx_left_out[5]
+  PIN chanx_left_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 51.19 0.8 51.49 ;
+    END
+  END chanx_left_out[6]
+  PIN chanx_left_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 11.75 0.8 12.05 ;
+    END
+  END chanx_left_out[7]
+  PIN chanx_left_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 23.99 0.8 24.29 ;
+    END
+  END chanx_left_out[8]
+  PIN chanx_left_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 30.79 0.8 31.09 ;
+    END
+  END chanx_left_out[9]
+  PIN chanx_left_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 53.91 0.8 54.21 ;
+    END
+  END chanx_left_out[10]
+  PIN chanx_left_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 40.31 0.8 40.61 ;
+    END
+  END chanx_left_out[11]
+  PIN chanx_left_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 13.11 0.8 13.41 ;
+    END
+  END chanx_left_out[12]
+  PIN chanx_left_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 33.51 0.8 33.81 ;
+    END
+  END chanx_left_out[13]
+  PIN chanx_left_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 49.83 0.8 50.13 ;
+    END
+  END chanx_left_out[14]
+  PIN chanx_left_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 47.11 0.8 47.41 ;
+    END
+  END chanx_left_out[15]
+  PIN chanx_left_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 56.63 0.8 56.93 ;
+    END
+  END chanx_left_out[16]
+  PIN chanx_left_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 34.87 0.8 35.17 ;
+    END
+  END chanx_left_out[17]
+  PIN chanx_left_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 52.55 0.8 52.85 ;
+    END
+  END chanx_left_out[18]
+  PIN chanx_left_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 32.15 0.8 32.45 ;
+    END
+  END chanx_left_out[19]
+  PIN chanx_right_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 48.47 66.24 48.77 ;
+    END
+  END chanx_right_out[0]
+  PIN chanx_right_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 43.03 66.24 43.33 ;
+    END
+  END chanx_right_out[1]
+  PIN chanx_right_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 51.19 66.24 51.49 ;
+    END
+  END chanx_right_out[2]
+  PIN chanx_right_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 45.75 66.24 46.05 ;
+    END
+  END chanx_right_out[3]
+  PIN chanx_right_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 11.75 66.24 12.05 ;
+    END
+  END chanx_right_out[4]
+  PIN chanx_right_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 36.23 66.24 36.53 ;
+    END
+  END chanx_right_out[5]
+  PIN chanx_right_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 32.15 66.24 32.45 ;
+    END
+  END chanx_right_out[6]
+  PIN chanx_right_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 37.59 66.24 37.89 ;
+    END
+  END chanx_right_out[7]
+  PIN chanx_right_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 55.95 66.24 56.25 ;
+    END
+  END chanx_right_out[8]
+  PIN chanx_right_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 61.39 66.24 61.69 ;
+    END
+  END chanx_right_out[9]
+  PIN chanx_right_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 30.79 66.24 31.09 ;
+    END
+  END chanx_right_out[10]
+  PIN chanx_right_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 47.11 66.24 47.41 ;
+    END
+  END chanx_right_out[11]
+  PIN chanx_right_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 49.83 66.24 50.13 ;
+    END
+  END chanx_right_out[12]
+  PIN chanx_right_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 77.03 66.24 77.33 ;
+    END
+  END chanx_right_out[13]
+  PIN chanx_right_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 34.87 66.24 35.17 ;
+    END
+  END chanx_right_out[14]
+  PIN chanx_right_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 58.67 66.24 58.97 ;
+    END
+  END chanx_right_out[15]
+  PIN chanx_right_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 52.55 66.24 52.85 ;
+    END
+  END chanx_right_out[16]
+  PIN chanx_right_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 60.03 66.24 60.33 ;
+    END
+  END chanx_right_out[17]
+  PIN chanx_right_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 74.31 66.24 74.61 ;
+    END
+  END chanx_right_out[18]
+  PIN chanx_right_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 57.31 66.24 57.61 ;
+    END
+  END chanx_right_out[19]
+  PIN bottom_grid_pin_0_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 18.1 0 18.24 0.485 ;
+    END
+  END bottom_grid_pin_0_[0]
+  PIN bottom_grid_pin_1_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 12.12 0 12.26 0.485 ;
+    END
+  END bottom_grid_pin_1_[0]
+  PIN bottom_grid_pin_2_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 11.2 0 11.34 0.485 ;
+    END
+  END bottom_grid_pin_2_[0]
+  PIN bottom_grid_pin_3_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 5.68 0 5.82 0.485 ;
+    END
+  END bottom_grid_pin_3_[0]
+  PIN bottom_grid_pin_4_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.06 0 7.2 0.485 ;
+    END
+  END bottom_grid_pin_4_[0]
+  PIN bottom_grid_pin_5_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.98 0 8.12 0.485 ;
+    END
+  END bottom_grid_pin_5_[0]
+  PIN bottom_grid_pin_6_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 3.38 0 3.52 0.485 ;
+    END
+  END bottom_grid_pin_6_[0]
+  PIN bottom_grid_pin_7_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 10.28 0 10.42 0.485 ;
+    END
+  END bottom_grid_pin_7_[0]
+  PIN bottom_grid_pin_8_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 25 0 25.14 0.485 ;
+    END
+  END bottom_grid_pin_8_[0]
+  PIN bottom_grid_pin_9_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 26.38 0 26.52 0.485 ;
+    END
+  END bottom_grid_pin_9_[0]
+  PIN bottom_grid_pin_10_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 24.08 0 24.22 0.485 ;
+    END
+  END bottom_grid_pin_10_[0]
+  PIN bottom_grid_pin_11_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 23.16 0 23.3 0.485 ;
+    END
+  END bottom_grid_pin_11_[0]
+  PIN bottom_grid_pin_12_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.5 0 59.64 0.485 ;
+    END
+  END bottom_grid_pin_12_[0]
+  PIN bottom_grid_pin_13_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.8 0 61.94 0.485 ;
+    END
+  END bottom_grid_pin_13_[0]
+  PIN bottom_grid_pin_14_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.12 0 58.26 0.485 ;
+    END
+  END bottom_grid_pin_14_[0]
+  PIN bottom_grid_pin_15_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 40.18 0 40.32 0.485 ;
+    END
+  END bottom_grid_pin_15_[0]
+  PIN ccff_tail[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 18.55 0.8 18.85 ;
+    END
+  END ccff_tail[0]
+  PIN SC_IN_TOP
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.8 86.555 61.94 87.04 ;
+    END
+  END SC_IN_TOP
+  PIN SC_OUT_BOT
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 4.76 0 4.9 0.485 ;
+    END
+  END SC_OUT_BOT
+  PIN SC_IN_BOT
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 60.42 0 60.56 0.485 ;
+    END
+  END SC_IN_BOT
+  PIN SC_OUT_TOP
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 16.26 86.555 16.4 87.04 ;
+    END
+  END SC_OUT_TOP
+  PIN REGIN_FEEDTHROUGH
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 57.66 86.555 57.8 87.04 ;
+    END
+  END REGIN_FEEDTHROUGH
+  PIN REGOUT_FEEDTHROUGH
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 9.36 0 9.5 0.485 ;
+    END
+  END REGOUT_FEEDTHROUGH
+  PIN prog_clk_0_N_in
+    DIRECTION INPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met2 ;
+        RECT 24.54 86.555 24.68 87.04 ;
+    END
+  END prog_clk_0_N_in
+  PIN prog_clk_0_W_out
+    DIRECTION OUTPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met3 ;
+        RECT 0 29.43 0.8 29.73 ;
+    END
+  END prog_clk_0_W_out
+  PIN prog_clk_1_W_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 26.71 0.8 27.01 ;
+    END
+  END prog_clk_1_W_in
+  PIN prog_clk_1_E_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 29.43 66.24 29.73 ;
+    END
+  END prog_clk_1_E_in
+  PIN prog_clk_1_N_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 30.06 86.555 30.2 87.04 ;
+    END
+  END prog_clk_1_N_out
+  PIN prog_clk_1_S_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 30.06 0 30.2 0.485 ;
+    END
+  END prog_clk_1_S_out
+  PIN prog_clk_2_E_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 62.75 66.24 63.05 ;
+    END
+  END prog_clk_2_E_in
+  PIN prog_clk_2_W_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 63.43 0.8 63.73 ;
+    END
+  END prog_clk_2_W_in
+  PIN prog_clk_2_W_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 71.59 0.8 71.89 ;
+    END
+  END prog_clk_2_W_out
+  PIN prog_clk_2_E_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 64.11 66.24 64.41 ;
+    END
+  END prog_clk_2_E_out
+  PIN prog_clk_3_W_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 70.23 0.8 70.53 ;
+    END
+  END prog_clk_3_W_in
+  PIN prog_clk_3_E_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 70.91 66.24 71.21 ;
+    END
+  END prog_clk_3_E_in
+  PIN prog_clk_3_E_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 65.47 66.24 65.77 ;
+    END
+  END prog_clk_3_E_out
+  PIN prog_clk_3_W_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 66.15 0.8 66.45 ;
+    END
+  END prog_clk_3_W_out
+  PIN clk_1_W_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 28.07 0.8 28.37 ;
+    END
+  END clk_1_W_in
+  PIN clk_1_E_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 28.07 66.24 28.37 ;
+    END
+  END clk_1_E_in
+  PIN clk_1_N_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.04 86.555 13.18 87.04 ;
+    END
+  END clk_1_N_out
+  PIN clk_1_S_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.04 0 13.18 0.485 ;
+    END
+  END clk_1_S_out
+  PIN clk_2_E_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 72.95 66.24 73.25 ;
+    END
+  END clk_2_E_in
+  PIN clk_2_W_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 64.79 0.8 65.09 ;
+    END
+  END clk_2_W_in
+  PIN clk_2_W_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 72.95 0.8 73.25 ;
+    END
+  END clk_2_W_out
+  PIN clk_2_E_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 66.83 66.24 67.13 ;
+    END
+  END clk_2_E_out
+  PIN clk_3_W_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 67.51 0.8 67.81 ;
+    END
+  END clk_3_W_in
+  PIN clk_3_E_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 69.55 66.24 69.85 ;
+    END
+  END clk_3_E_in
+  PIN clk_3_E_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 68.19 66.24 68.49 ;
+    END
+  END clk_3_E_out
+  PIN clk_3_W_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 68.87 0.8 69.17 ;
+    END
+  END clk_3_W_out
+  PIN VDD
+    DIRECTION INPUT ;
+    USE POWER ;
+    PORT
+      LAYER met1 ;
+        RECT 0 2.48 0.48 2.96 ;
+        RECT 65.76 2.48 66.24 2.96 ;
+        RECT 0 7.92 0.48 8.4 ;
+        RECT 65.76 7.92 66.24 8.4 ;
+        RECT 0 13.36 0.48 13.84 ;
+        RECT 65.76 13.36 66.24 13.84 ;
+        RECT 0 18.8 0.48 19.28 ;
+        RECT 65.76 18.8 66.24 19.28 ;
+        RECT 0 24.24 0.48 24.72 ;
+        RECT 65.76 24.24 66.24 24.72 ;
+        RECT 0 29.68 0.48 30.16 ;
+        RECT 65.76 29.68 66.24 30.16 ;
+        RECT 0 35.12 0.48 35.6 ;
+        RECT 65.76 35.12 66.24 35.6 ;
+        RECT 0 40.56 0.48 41.04 ;
+        RECT 65.76 40.56 66.24 41.04 ;
+        RECT 0 46 0.48 46.48 ;
+        RECT 65.76 46 66.24 46.48 ;
+        RECT 0 51.44 0.48 51.92 ;
+        RECT 65.76 51.44 66.24 51.92 ;
+        RECT 0 56.88 0.48 57.36 ;
+        RECT 65.76 56.88 66.24 57.36 ;
+        RECT 0 62.32 0.48 62.8 ;
+        RECT 65.76 62.32 66.24 62.8 ;
+        RECT 0 67.76 0.48 68.24 ;
+        RECT 65.76 67.76 66.24 68.24 ;
+        RECT 0 73.2 0.48 73.68 ;
+        RECT 65.76 73.2 66.24 73.68 ;
+        RECT 0 78.64 0.48 79.12 ;
+        RECT 65.76 78.64 66.24 79.12 ;
+        RECT 0 84.08 0.48 84.56 ;
+        RECT 65.76 84.08 66.24 84.56 ;
+      LAYER met5 ;
+        RECT 0 11.32 3.2 14.52 ;
+        RECT 63.04 11.32 66.24 14.52 ;
+        RECT 0 52.12 3.2 55.32 ;
+        RECT 63.04 52.12 66.24 55.32 ;
+      LAYER met4 ;
+        RECT 10.74 0 11.34 0.6 ;
+        RECT 40.18 0 40.78 0.6 ;
+        RECT 10.74 86.44 11.34 87.04 ;
+        RECT 40.18 86.44 40.78 87.04 ;
+    END
+  END VDD
+  PIN VSS
+    DIRECTION INPUT ;
+    USE GROUND ;
+    PORT
+      LAYER met1 ;
+        RECT 0 0 45.4 0.24 ;
+        RECT 46.6 0 66.24 0.24 ;
+        RECT 0 5.2 0.48 5.68 ;
+        RECT 65.76 5.2 66.24 5.68 ;
+        RECT 0 10.64 0.48 11.12 ;
+        RECT 65.76 10.64 66.24 11.12 ;
+        RECT 0 16.08 0.48 16.56 ;
+        RECT 65.76 16.08 66.24 16.56 ;
+        RECT 0 21.52 0.48 22 ;
+        RECT 65.76 21.52 66.24 22 ;
+        RECT 0 26.96 0.48 27.44 ;
+        RECT 65.76 26.96 66.24 27.44 ;
+        RECT 0 32.4 0.48 32.88 ;
+        RECT 65.76 32.4 66.24 32.88 ;
+        RECT 0 37.84 0.48 38.32 ;
+        RECT 65.76 37.84 66.24 38.32 ;
+        RECT 0 43.28 0.48 43.76 ;
+        RECT 65.76 43.28 66.24 43.76 ;
+        RECT 0 48.72 0.48 49.2 ;
+        RECT 65.76 48.72 66.24 49.2 ;
+        RECT 0 54.16 0.48 54.64 ;
+        RECT 65.76 54.16 66.24 54.64 ;
+        RECT 0 59.6 0.48 60.08 ;
+        RECT 65.76 59.6 66.24 60.08 ;
+        RECT 0 65.04 0.48 65.52 ;
+        RECT 65.76 65.04 66.24 65.52 ;
+        RECT 0 70.48 0.48 70.96 ;
+        RECT 65.76 70.48 66.24 70.96 ;
+        RECT 0 75.92 0.48 76.4 ;
+        RECT 65.76 75.92 66.24 76.4 ;
+        RECT 0 81.36 0.48 81.84 ;
+        RECT 65.76 81.36 66.24 81.84 ;
+        RECT 0 86.8 45.4 87.04 ;
+        RECT 46.6 86.8 66.24 87.04 ;
+      LAYER met5 ;
+        RECT 0 31.72 3.2 34.92 ;
+        RECT 63.04 31.72 66.24 34.92 ;
+        RECT 0 72.52 3.2 75.72 ;
+        RECT 63.04 72.52 66.24 75.72 ;
+      LAYER met4 ;
+        RECT 25.46 0 26.06 0.6 ;
+        RECT 54.9 0 55.5 0.6 ;
+        RECT 25.46 86.44 26.06 87.04 ;
+        RECT 54.9 86.44 55.5 87.04 ;
+    END
+  END VSS
+  OBS
+    LAYER met3 ;
+      POLYGON 55.365 87.205 55.365 87.2 55.58 87.2 55.58 86.88 55.365 86.88 55.365 86.875 55.035 86.875 55.035 86.88 54.82 86.88 54.82 87.2 55.035 87.2 55.035 87.205 ;
+      POLYGON 25.925 87.205 25.925 87.2 26.14 87.2 26.14 86.88 25.925 86.88 25.925 86.875 25.595 86.875 25.595 86.88 25.38 86.88 25.38 87.2 25.595 87.2 25.595 87.205 ;
+      POLYGON 1.315 38.585 1.315 38.57 10.5 38.57 10.5 38.27 1.315 38.27 1.315 38.255 0.985 38.255 0.985 38.585 ;
+      POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ;
+      POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ;
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diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef
new file mode 100644
index 0000000..2aa7bd7
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef
@@ -0,0 +1,1466 @@
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+END L1M1_PR_MR
+
+VIA L1M1_PR_C
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.145 0.145 0.145 ;
+END L1M1_PR_C
+
+VIA M1M2_PR
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR
+
+VIA M1M2_PR_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_Enc
+
+VIA M1M2_PR_R
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_R
+
+VIA M1M2_PR_R_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_R_Enc
+
+VIA M1M2_PR_M
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIA M1M2_PR_M_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_M_Enc
+
+VIA M1M2_PR_MR
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIA M1M2_PR_MR_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_MR_Enc
+
+VIA M1M2_PR_C
+  LAYER met1 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIA M2M3_PR
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIA M2M3_PR_R
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIA M2M3_PR_M
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIA M2M3_PR_MR
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIA M2M3_PR_C
+  LAYER met2 ;
+    RECT -0.185 -0.185 0.185 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIA M3M4_PR
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIA M3M4_PR_R
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIA M3M4_PR_M
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIA M3M4_PR_MR
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIA M3M4_PR_C
+  LAYER met3 ;
+    RECT -0.19 -0.19 0.19 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIA M4M5_PR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIA M4M5_PR_R
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIA M4M5_PR_M
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIA M4M5_PR_MR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIA M4M5_PR_C
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+  CLASS CORE ;
+  SYMMETRY Y ;
+  SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+  CLASS CORE ;
+  SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+MACRO cbx_1__2_
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 66.24 BY 87.04 ;
+  SYMMETRY X Y ;
+  PIN chanx_left_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 6.99 0.8 7.29 ;
+    END
+  END chanx_left_in[0]
+  PIN chanx_left_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 35.55 0.8 35.85 ;
+    END
+  END chanx_left_in[1]
+  PIN chanx_left_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 28.75 0.8 29.05 ;
+    END
+  END chanx_left_in[2]
+  PIN chanx_left_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 14.47 0.8 14.77 ;
+    END
+  END chanx_left_in[3]
+  PIN chanx_left_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 36.91 0.8 37.21 ;
+    END
+  END chanx_left_in[4]
+  PIN chanx_left_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 17.19 0.8 17.49 ;
+    END
+  END chanx_left_in[5]
+  PIN chanx_left_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 47.79 0.8 48.09 ;
+    END
+  END chanx_left_in[6]
+  PIN chanx_left_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 13.11 0.8 13.41 ;
+    END
+  END chanx_left_in[7]
+  PIN chanx_left_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 31.47 0.8 31.77 ;
+    END
+  END chanx_left_in[8]
+  PIN chanx_left_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 19.91 0.8 20.21 ;
+    END
+  END chanx_left_in[9]
+  PIN chanx_left_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 42.35 0.8 42.65 ;
+    END
+  END chanx_left_in[10]
+  PIN chanx_left_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 15.83 0.8 16.13 ;
+    END
+  END chanx_left_in[11]
+  PIN chanx_left_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 61.39 0.8 61.69 ;
+    END
+  END chanx_left_in[12]
+  PIN chanx_left_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 9.71 0.8 10.01 ;
+    END
+  END chanx_left_in[13]
+  PIN chanx_left_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 45.07 0.8 45.37 ;
+    END
+  END chanx_left_in[14]
+  PIN chanx_left_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 22.63 0.8 22.93 ;
+    END
+  END chanx_left_in[15]
+  PIN chanx_left_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 55.95 0.8 56.25 ;
+    END
+  END chanx_left_in[16]
+  PIN chanx_left_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 27.39 0.8 27.69 ;
+    END
+  END chanx_left_in[17]
+  PIN chanx_left_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 43.71 0.8 44.01 ;
+    END
+  END chanx_left_in[18]
+  PIN chanx_left_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 11.75 0.8 12.05 ;
+    END
+  END chanx_left_in[19]
+  PIN chanx_right_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 62.07 66.24 62.37 ;
+    END
+  END chanx_right_in[0]
+  PIN chanx_right_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 60.71 66.24 61.01 ;
+    END
+  END chanx_right_in[1]
+  PIN chanx_right_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 79.75 66.24 80.05 ;
+    END
+  END chanx_right_in[2]
+  PIN chanx_right_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 58.67 66.24 58.97 ;
+    END
+  END chanx_right_in[3]
+  PIN chanx_right_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 30.79 66.24 31.09 ;
+    END
+  END chanx_right_in[4]
+  PIN chanx_right_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 18.55 66.24 18.85 ;
+    END
+  END chanx_right_in[5]
+  PIN chanx_right_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 40.31 66.24 40.61 ;
+    END
+  END chanx_right_in[6]
+  PIN chanx_right_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 15.15 66.24 15.45 ;
+    END
+  END chanx_right_in[7]
+  PIN chanx_right_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 20.59 66.24 20.89 ;
+    END
+  END chanx_right_in[8]
+  PIN chanx_right_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 23.31 66.24 23.61 ;
+    END
+  END chanx_right_in[9]
+  PIN chanx_right_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 33.51 66.24 33.81 ;
+    END
+  END chanx_right_in[10]
+  PIN chanx_right_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 11.07 66.24 11.37 ;
+    END
+  END chanx_right_in[11]
+  PIN chanx_right_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 28.07 66.24 28.37 ;
+    END
+  END chanx_right_in[12]
+  PIN chanx_right_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 4.95 66.24 5.25 ;
+    END
+  END chanx_right_in[13]
+  PIN chanx_right_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 43.03 66.24 43.33 ;
+    END
+  END chanx_right_in[14]
+  PIN chanx_right_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 13.79 66.24 14.09 ;
+    END
+  END chanx_right_in[15]
+  PIN chanx_right_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 6.31 66.24 6.61 ;
+    END
+  END chanx_right_in[16]
+  PIN chanx_right_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 7.67 66.24 7.97 ;
+    END
+  END chanx_right_in[17]
+  PIN chanx_right_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 51.87 66.24 52.17 ;
+    END
+  END chanx_right_in[18]
+  PIN chanx_right_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 24.67 66.24 24.97 ;
+    END
+  END chanx_right_in[19]
+  PIN ccff_head[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 32.15 66.24 32.45 ;
+    END
+  END ccff_head[0]
+  PIN chanx_left_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 79.75 0.8 80.05 ;
+    END
+  END chanx_left_out[0]
+  PIN chanx_left_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 64.11 0.8 64.41 ;
+    END
+  END chanx_left_out[1]
+  PIN chanx_left_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 54.59 0.8 54.89 ;
+    END
+  END chanx_left_out[2]
+  PIN chanx_left_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 65.47 0.8 65.77 ;
+    END
+  END chanx_left_out[3]
+  PIN chanx_left_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 21.27 0.8 21.57 ;
+    END
+  END chanx_left_out[4]
+  PIN chanx_left_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 49.15 0.8 49.45 ;
+    END
+  END chanx_left_out[5]
+  PIN chanx_left_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 40.31 0.8 40.61 ;
+    END
+  END chanx_left_out[6]
+  PIN chanx_left_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 34.19 0.8 34.49 ;
+    END
+  END chanx_left_out[7]
+  PIN chanx_left_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 53.23 0.8 53.53 ;
+    END
+  END chanx_left_out[8]
+  PIN chanx_left_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 18.55 0.8 18.85 ;
+    END
+  END chanx_left_out[9]
+  PIN chanx_left_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 58.67 0.8 58.97 ;
+    END
+  END chanx_left_out[10]
+  PIN chanx_left_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 62.75 0.8 63.05 ;
+    END
+  END chanx_left_out[11]
+  PIN chanx_left_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 24.67 0.8 24.97 ;
+    END
+  END chanx_left_out[12]
+  PIN chanx_left_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 8.35 0.8 8.65 ;
+    END
+  END chanx_left_out[13]
+  PIN chanx_left_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 26.03 0.8 26.33 ;
+    END
+  END chanx_left_out[14]
+  PIN chanx_left_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 30.11 0.8 30.41 ;
+    END
+  END chanx_left_out[15]
+  PIN chanx_left_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 46.43 0.8 46.73 ;
+    END
+  END chanx_left_out[16]
+  PIN chanx_left_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 60.03 0.8 60.33 ;
+    END
+  END chanx_left_out[17]
+  PIN chanx_left_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 38.95 0.8 39.25 ;
+    END
+  END chanx_left_out[18]
+  PIN chanx_left_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 57.31 0.8 57.61 ;
+    END
+  END chanx_left_out[19]
+  PIN chanx_right_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 55.95 66.24 56.25 ;
+    END
+  END chanx_right_out[0]
+  PIN chanx_right_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 41.67 66.24 41.97 ;
+    END
+  END chanx_right_out[1]
+  PIN chanx_right_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 49.83 66.24 50.13 ;
+    END
+  END chanx_right_out[2]
+  PIN chanx_right_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 34.87 66.24 35.17 ;
+    END
+  END chanx_right_out[3]
+  PIN chanx_right_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 37.59 66.24 37.89 ;
+    END
+  END chanx_right_out[4]
+  PIN chanx_right_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 45.75 66.24 46.05 ;
+    END
+  END chanx_right_out[5]
+  PIN chanx_right_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 57.31 66.24 57.61 ;
+    END
+  END chanx_right_out[6]
+  PIN chanx_right_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 54.59 66.24 54.89 ;
+    END
+  END chanx_right_out[7]
+  PIN chanx_right_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 38.95 66.24 39.25 ;
+    END
+  END chanx_right_out[8]
+  PIN chanx_right_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 48.47 66.24 48.77 ;
+    END
+  END chanx_right_out[9]
+  PIN chanx_right_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 53.23 66.24 53.53 ;
+    END
+  END chanx_right_out[10]
+  PIN chanx_right_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 36.23 66.24 36.53 ;
+    END
+  END chanx_right_out[11]
+  PIN chanx_right_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 44.39 66.24 44.69 ;
+    END
+  END chanx_right_out[12]
+  PIN chanx_right_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 12.43 66.24 12.73 ;
+    END
+  END chanx_right_out[13]
+  PIN chanx_right_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 47.11 66.24 47.41 ;
+    END
+  END chanx_right_out[14]
+  PIN chanx_right_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 29.43 66.24 29.73 ;
+    END
+  END chanx_right_out[15]
+  PIN chanx_right_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 26.71 66.24 27.01 ;
+    END
+  END chanx_right_out[16]
+  PIN chanx_right_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 16.51 66.24 16.81 ;
+    END
+  END chanx_right_out[17]
+  PIN chanx_right_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 63.43 66.24 63.73 ;
+    END
+  END chanx_right_out[18]
+  PIN chanx_right_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 21.95 66.24 22.25 ;
+    END
+  END chanx_right_out[19]
+  PIN top_grid_pin_0_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 66.15 66.24 66.45 ;
+    END
+  END top_grid_pin_0_[0]
+  PIN bottom_grid_pin_0_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 18.1 0 18.24 0.485 ;
+    END
+  END bottom_grid_pin_0_[0]
+  PIN bottom_grid_pin_1_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 12.12 0 12.26 0.485 ;
+    END
+  END bottom_grid_pin_1_[0]
+  PIN bottom_grid_pin_2_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 11.2 0 11.34 0.485 ;
+    END
+  END bottom_grid_pin_2_[0]
+  PIN bottom_grid_pin_3_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 5.68 0 5.82 0.485 ;
+    END
+  END bottom_grid_pin_3_[0]
+  PIN bottom_grid_pin_4_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.06 0 7.2 0.485 ;
+    END
+  END bottom_grid_pin_4_[0]
+  PIN bottom_grid_pin_5_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.98 0 8.12 0.485 ;
+    END
+  END bottom_grid_pin_5_[0]
+  PIN bottom_grid_pin_6_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 3.38 0 3.52 0.485 ;
+    END
+  END bottom_grid_pin_6_[0]
+  PIN bottom_grid_pin_7_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 10.28 0 10.42 0.485 ;
+    END
+  END bottom_grid_pin_7_[0]
+  PIN bottom_grid_pin_8_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 25 0 25.14 0.485 ;
+    END
+  END bottom_grid_pin_8_[0]
+  PIN bottom_grid_pin_9_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 26.38 0 26.52 0.485 ;
+    END
+  END bottom_grid_pin_9_[0]
+  PIN bottom_grid_pin_10_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 24.08 0 24.22 0.485 ;
+    END
+  END bottom_grid_pin_10_[0]
+  PIN bottom_grid_pin_11_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 23.16 0 23.3 0.485 ;
+    END
+  END bottom_grid_pin_11_[0]
+  PIN bottom_grid_pin_12_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.5 0 59.64 0.485 ;
+    END
+  END bottom_grid_pin_12_[0]
+  PIN bottom_grid_pin_13_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.8 0 61.94 0.485 ;
+    END
+  END bottom_grid_pin_13_[0]
+  PIN bottom_grid_pin_14_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.12 0 58.26 0.485 ;
+    END
+  END bottom_grid_pin_14_[0]
+  PIN bottom_grid_pin_15_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 40.18 0 40.32 0.485 ;
+    END
+  END bottom_grid_pin_15_[0]
+  PIN ccff_tail[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 50.51 0.8 50.81 ;
+    END
+  END ccff_tail[0]
+  PIN IO_ISOL_N[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 4.95 0.8 5.25 ;
+    END
+  END IO_ISOL_N[0]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 28.68 86.555 28.82 87.04 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 25 86.555 25.14 87.04 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 19.48 86.555 19.62 87.04 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]
+  PIN bottom_width_0_height_0__pin_0_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 64.79 66.24 65.09 ;
+    END
+  END bottom_width_0_height_0__pin_0_[0]
+  PIN bottom_width_0_height_0__pin_1_upper[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 32.83 0.8 33.13 ;
+    END
+  END bottom_width_0_height_0__pin_1_upper[0]
+  PIN bottom_width_0_height_0__pin_1_lower[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 9.71 66.24 10.01 ;
+    END
+  END bottom_width_0_height_0__pin_1_lower[0]
+  PIN SC_IN_TOP
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 3.59 0.8 3.89 ;
+    END
+  END SC_IN_TOP
+  PIN SC_OUT_BOT
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 4.76 0 4.9 0.485 ;
+    END
+  END SC_OUT_BOT
+  PIN SC_IN_BOT
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 60.42 0 60.56 0.485 ;
+    END
+  END SC_IN_BOT
+  PIN SC_OUT_TOP
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 3.59 66.24 3.89 ;
+    END
+  END SC_OUT_TOP
+  PIN prog_clk_0_S_in
+    DIRECTION INPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met2 ;
+        RECT 2.46 0 2.6 0.485 ;
+    END
+  END prog_clk_0_S_in
+  PIN prog_clk_0_W_out
+    DIRECTION OUTPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met3 ;
+        RECT 0 51.87 0.8 52.17 ;
+    END
+  END prog_clk_0_W_out
+  PIN VDD
+    DIRECTION INPUT ;
+    USE POWER ;
+    PORT
+      LAYER met1 ;
+        RECT 0 2.48 0.48 2.96 ;
+        RECT 65.76 2.48 66.24 2.96 ;
+        RECT 0 7.92 0.48 8.4 ;
+        RECT 65.76 7.92 66.24 8.4 ;
+        RECT 0 13.36 0.48 13.84 ;
+        RECT 65.76 13.36 66.24 13.84 ;
+        RECT 0 18.8 0.48 19.28 ;
+        RECT 65.76 18.8 66.24 19.28 ;
+        RECT 0 24.24 0.48 24.72 ;
+        RECT 65.76 24.24 66.24 24.72 ;
+        RECT 0 29.68 0.48 30.16 ;
+        RECT 65.76 29.68 66.24 30.16 ;
+        RECT 0 35.12 0.48 35.6 ;
+        RECT 65.76 35.12 66.24 35.6 ;
+        RECT 0 40.56 0.48 41.04 ;
+        RECT 65.76 40.56 66.24 41.04 ;
+        RECT 0 46 0.48 46.48 ;
+        RECT 65.76 46 66.24 46.48 ;
+        RECT 0 51.44 0.48 51.92 ;
+        RECT 65.76 51.44 66.24 51.92 ;
+        RECT 0 56.88 0.48 57.36 ;
+        RECT 65.76 56.88 66.24 57.36 ;
+        RECT 0 62.32 0.48 62.8 ;
+        RECT 65.76 62.32 66.24 62.8 ;
+        RECT 0 67.76 0.48 68.24 ;
+        RECT 65.76 67.76 66.24 68.24 ;
+        RECT 0 73.2 0.48 73.68 ;
+        RECT 65.76 73.2 66.24 73.68 ;
+        RECT 0 78.64 0.48 79.12 ;
+        RECT 65.76 78.64 66.24 79.12 ;
+        RECT 0 84.08 0.48 84.56 ;
+        RECT 65.76 84.08 66.24 84.56 ;
+      LAYER met5 ;
+        RECT 0 11.32 3.2 14.52 ;
+        RECT 63.04 11.32 66.24 14.52 ;
+        RECT 0 52.12 3.2 55.32 ;
+        RECT 63.04 52.12 66.24 55.32 ;
+      LAYER met4 ;
+        RECT 10.74 0 11.34 0.6 ;
+        RECT 40.18 0 40.78 0.6 ;
+        RECT 10.74 86.44 11.34 87.04 ;
+        RECT 40.18 86.44 40.78 87.04 ;
+    END
+  END VDD
+  PIN VSS
+    DIRECTION INPUT ;
+    USE GROUND ;
+    PORT
+      LAYER met1 ;
+        RECT 0 0 45.4 0.24 ;
+        RECT 46.6 0 66.24 0.24 ;
+        RECT 0 5.2 0.48 5.68 ;
+        RECT 65.76 5.2 66.24 5.68 ;
+        RECT 0 10.64 0.48 11.12 ;
+        RECT 65.76 10.64 66.24 11.12 ;
+        RECT 0 16.08 0.48 16.56 ;
+        RECT 65.76 16.08 66.24 16.56 ;
+        RECT 0 21.52 0.48 22 ;
+        RECT 65.76 21.52 66.24 22 ;
+        RECT 0 26.96 0.48 27.44 ;
+        RECT 65.76 26.96 66.24 27.44 ;
+        RECT 0 32.4 0.48 32.88 ;
+        RECT 65.76 32.4 66.24 32.88 ;
+        RECT 0 37.84 0.48 38.32 ;
+        RECT 65.76 37.84 66.24 38.32 ;
+        RECT 0 43.28 0.48 43.76 ;
+        RECT 65.76 43.28 66.24 43.76 ;
+        RECT 0 48.72 0.48 49.2 ;
+        RECT 65.76 48.72 66.24 49.2 ;
+        RECT 0 54.16 0.48 54.64 ;
+        RECT 65.76 54.16 66.24 54.64 ;
+        RECT 0 59.6 0.48 60.08 ;
+        RECT 65.76 59.6 66.24 60.08 ;
+        RECT 0 65.04 0.48 65.52 ;
+        RECT 65.76 65.04 66.24 65.52 ;
+        RECT 0 70.48 0.48 70.96 ;
+        RECT 65.76 70.48 66.24 70.96 ;
+        RECT 0 75.92 0.48 76.4 ;
+        RECT 65.76 75.92 66.24 76.4 ;
+        RECT 0 81.36 0.48 81.84 ;
+        RECT 65.76 81.36 66.24 81.84 ;
+        RECT 0 86.8 45.4 87.04 ;
+        RECT 46.6 86.8 66.24 87.04 ;
+      LAYER met5 ;
+        RECT 0 31.72 3.2 34.92 ;
+        RECT 63.04 31.72 66.24 34.92 ;
+        RECT 0 72.52 3.2 75.72 ;
+        RECT 63.04 72.52 66.24 75.72 ;
+      LAYER met4 ;
+        RECT 25.46 0 26.06 0.6 ;
+        RECT 54.9 0 55.5 0.6 ;
+        RECT 25.46 86.44 26.06 87.04 ;
+        RECT 54.9 86.44 55.5 87.04 ;
+    END
+  END VSS
+  OBS
+    LAYER met3 ;
+      POLYGON 55.365 87.205 55.365 87.2 55.58 87.2 55.58 86.88 55.365 86.88 55.365 86.875 55.035 86.875 55.035 86.88 54.82 86.88 54.82 87.2 55.035 87.2 55.035 87.205 ;
+      POLYGON 25.925 87.205 25.925 87.2 26.14 87.2 26.14 86.88 25.925 86.88 25.925 86.875 25.595 86.875 25.595 86.88 25.38 86.88 25.38 87.2 25.595 87.2 25.595 87.205 ;
+      POLYGON 65.04 48.09 65.04 48.07 65.59 48.07 65.59 47.79 49.07 47.79 49.07 48.09 ;
+      POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ;
+      POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ;
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diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef
new file mode 100644
index 0000000..7b06400
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef
@@ -0,0 +1,1280 @@
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+END M1M2_PR_R
+
+VIA M1M2_PR_R_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_R_Enc
+
+VIA M1M2_PR_M
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIA M1M2_PR_M_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_M_Enc
+
+VIA M1M2_PR_MR
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIA M1M2_PR_MR_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_MR_Enc
+
+VIA M1M2_PR_C
+  LAYER met1 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIA M2M3_PR
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIA M2M3_PR_R
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIA M2M3_PR_M
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIA M2M3_PR_MR
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIA M2M3_PR_C
+  LAYER met2 ;
+    RECT -0.185 -0.185 0.185 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIA M3M4_PR
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIA M3M4_PR_R
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIA M3M4_PR_M
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIA M3M4_PR_MR
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIA M3M4_PR_C
+  LAYER met3 ;
+    RECT -0.19 -0.19 0.19 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIA M4M5_PR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIA M4M5_PR_R
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIA M4M5_PR_M
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIA M4M5_PR_MR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIA M4M5_PR_C
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+  CLASS CORE ;
+  SYMMETRY Y ;
+  SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+  CLASS CORE ;
+  SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+MACRO cby_0__1_
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 66.24 BY 76.16 ;
+  SYMMETRY X Y ;
+  PIN chany_bottom_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 62.72 0 62.86 0.485 ;
+    END
+  END chany_bottom_in[0]
+  PIN chany_bottom_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 40.18 0 40.32 0.485 ;
+    END
+  END chany_bottom_in[1]
+  PIN chany_bottom_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 51.68 0 51.82 0.485 ;
+    END
+  END chany_bottom_in[2]
+  PIN chany_bottom_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 56.28 0 56.42 0.485 ;
+    END
+  END chany_bottom_in[3]
+  PIN chany_bottom_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.52 0 53.66 0.485 ;
+    END
+  END chany_bottom_in[4]
+  PIN chany_bottom_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 34.66 0 34.8 0.485 ;
+    END
+  END chany_bottom_in[5]
+  PIN chany_bottom_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.96 0 14.1 0.485 ;
+    END
+  END chany_bottom_in[6]
+  PIN chany_bottom_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 16.72 0 16.86 0.485 ;
+    END
+  END chany_bottom_in[7]
+  PIN chany_bottom_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 39.26 0 39.4 0.485 ;
+    END
+  END chany_bottom_in[8]
+  PIN chany_bottom_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 35.58 0 35.72 0.485 ;
+    END
+  END chany_bottom_in[9]
+  PIN chany_bottom_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.8 0 61.94 0.485 ;
+    END
+  END chany_bottom_in[10]
+  PIN chany_bottom_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.12 0 58.26 0.485 ;
+    END
+  END chany_bottom_in[11]
+  PIN chany_bottom_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 33.74 0 33.88 0.485 ;
+    END
+  END chany_bottom_in[12]
+  PIN chany_bottom_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 38.34 0 38.48 0.485 ;
+    END
+  END chany_bottom_in[13]
+  PIN chany_bottom_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 14.88 0 15.02 0.485 ;
+    END
+  END chany_bottom_in[14]
+  PIN chany_bottom_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 36.5 0 36.64 0.485 ;
+    END
+  END chany_bottom_in[15]
+  PIN chany_bottom_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.96 0 60.1 0.485 ;
+    END
+  END chany_bottom_in[16]
+  PIN chany_bottom_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 15.8 0 15.94 0.485 ;
+    END
+  END chany_bottom_in[17]
+  PIN chany_bottom_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 37.42 0 37.56 0.485 ;
+    END
+  END chany_bottom_in[18]
+  PIN chany_bottom_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 57.2 0 57.34 0.485 ;
+    END
+  END chany_bottom_in[19]
+  PIN chany_top_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 50.76 75.675 50.9 76.16 ;
+    END
+  END chany_top_in[0]
+  PIN chany_top_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 57.2 75.675 57.34 76.16 ;
+    END
+  END chany_top_in[1]
+  PIN chany_top_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 41.1 75.675 41.24 76.16 ;
+    END
+  END chany_top_in[2]
+  PIN chany_top_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 11.2 75.675 11.34 76.16 ;
+    END
+  END chany_top_in[3]
+  PIN chany_top_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 33.74 75.675 33.88 76.16 ;
+    END
+  END chany_top_in[4]
+  PIN chany_top_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 19.48 75.675 19.62 76.16 ;
+    END
+  END chany_top_in[5]
+  PIN chany_top_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 12.12 75.675 12.26 76.16 ;
+    END
+  END chany_top_in[6]
+  PIN chany_top_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 36.5 75.675 36.64 76.16 ;
+    END
+  END chany_top_in[7]
+  PIN chany_top_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 18.56 75.675 18.7 76.16 ;
+    END
+  END chany_top_in[8]
+  PIN chany_top_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.04 75.675 13.18 76.16 ;
+    END
+  END chany_top_in[9]
+  PIN chany_top_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.04 75.675 59.18 76.16 ;
+    END
+  END chany_top_in[10]
+  PIN chany_top_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 17.64 75.675 17.78 76.16 ;
+    END
+  END chany_top_in[11]
+  PIN chany_top_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 10.28 75.675 10.42 76.16 ;
+    END
+  END chany_top_in[12]
+  PIN chany_top_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.96 75.675 14.1 76.16 ;
+    END
+  END chany_top_in[13]
+  PIN chany_top_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 37.42 75.675 37.56 76.16 ;
+    END
+  END chany_top_in[14]
+  PIN chany_top_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 16.72 75.675 16.86 76.16 ;
+    END
+  END chany_top_in[15]
+  PIN chany_top_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 54.44 75.675 54.58 76.16 ;
+    END
+  END chany_top_in[16]
+  PIN chany_top_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 14.88 75.675 15.02 76.16 ;
+    END
+  END chany_top_in[17]
+  PIN chany_top_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 2.46 75.675 2.6 76.16 ;
+    END
+  END chany_top_in[18]
+  PIN chany_top_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 15.8 75.675 15.94 76.16 ;
+    END
+  END chany_top_in[19]
+  PIN ccff_head[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 34.66 75.675 34.8 76.16 ;
+    END
+  END ccff_head[0]
+  PIN chany_bottom_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 48 0 48.14 0.485 ;
+    END
+  END chany_bottom_out[0]
+  PIN chany_bottom_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 54.44 0 54.58 0.485 ;
+    END
+  END chany_bottom_out[1]
+  PIN chany_bottom_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 47.08 0 47.22 0.485 ;
+    END
+  END chany_bottom_out[2]
+  PIN chany_bottom_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 60.88 0 61.02 0.485 ;
+    END
+  END chany_bottom_out[3]
+  PIN chany_bottom_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 50.76 0 50.9 0.485 ;
+    END
+  END chany_bottom_out[4]
+  PIN chany_bottom_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 42.02 0 42.16 0.485 ;
+    END
+  END chany_bottom_out[5]
+  PIN chany_bottom_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 31.9 0 32.04 0.485 ;
+    END
+  END chany_bottom_out[6]
+  PIN chany_bottom_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 42.94 0 43.08 0.485 ;
+    END
+  END chany_bottom_out[7]
+  PIN chany_bottom_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.04 0 13.18 0.485 ;
+    END
+  END chany_bottom_out[8]
+  PIN chany_bottom_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 18.56 0 18.7 0.485 ;
+    END
+  END chany_bottom_out[9]
+  PIN chany_bottom_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 49.84 0 49.98 0.485 ;
+    END
+  END chany_bottom_out[10]
+  PIN chany_bottom_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.6 0 52.74 0.485 ;
+    END
+  END chany_bottom_out[11]
+  PIN chany_bottom_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.04 0 59.18 0.485 ;
+    END
+  END chany_bottom_out[12]
+  PIN chany_bottom_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 41.1 0 41.24 0.485 ;
+    END
+  END chany_bottom_out[13]
+  PIN chany_bottom_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 32.82 0 32.96 0.485 ;
+    END
+  END chany_bottom_out[14]
+  PIN chany_bottom_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 17.64 0 17.78 0.485 ;
+    END
+  END chany_bottom_out[15]
+  PIN chany_bottom_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 25 0 25.14 0.485 ;
+    END
+  END chany_bottom_out[16]
+  PIN chany_bottom_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 30.98 0 31.12 0.485 ;
+    END
+  END chany_bottom_out[17]
+  PIN chany_bottom_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.64 0 63.78 0.485 ;
+    END
+  END chany_bottom_out[18]
+  PIN chany_bottom_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 48.92 0 49.06 0.485 ;
+    END
+  END chany_bottom_out[19]
+  PIN chany_top_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 49.84 75.675 49.98 76.16 ;
+    END
+  END chany_top_out[0]
+  PIN chany_top_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.96 75.675 60.1 76.16 ;
+    END
+  END chany_top_out[1]
+  PIN chany_top_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 60.88 75.675 61.02 76.16 ;
+    END
+  END chany_top_out[2]
+  PIN chany_top_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.64 75.675 63.78 76.16 ;
+    END
+  END chany_top_out[3]
+  PIN chany_top_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.6 75.675 52.74 76.16 ;
+    END
+  END chany_top_out[4]
+  PIN chany_top_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 39.26 75.675 39.4 76.16 ;
+    END
+  END chany_top_out[5]
+  PIN chany_top_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 35.58 75.675 35.72 76.16 ;
+    END
+  END chany_top_out[6]
+  PIN chany_top_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 62.72 75.675 62.86 76.16 ;
+    END
+  END chany_top_out[7]
+  PIN chany_top_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 9.36 75.675 9.5 76.16 ;
+    END
+  END chany_top_out[8]
+  PIN chany_top_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 8.44 75.675 8.58 76.16 ;
+    END
+  END chany_top_out[9]
+  PIN chany_top_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 26.38 75.675 26.52 76.16 ;
+    END
+  END chany_top_out[10]
+  PIN chany_top_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 51.68 75.675 51.82 76.16 ;
+    END
+  END chany_top_out[11]
+  PIN chany_top_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.52 75.675 53.66 76.16 ;
+    END
+  END chany_top_out[12]
+  PIN chany_top_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 56.28 75.675 56.42 76.16 ;
+    END
+  END chany_top_out[13]
+  PIN chany_top_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.12 75.675 58.26 76.16 ;
+    END
+  END chany_top_out[14]
+  PIN chany_top_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 38.34 75.675 38.48 76.16 ;
+    END
+  END chany_top_out[15]
+  PIN chany_top_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.8 75.675 61.94 76.16 ;
+    END
+  END chany_top_out[16]
+  PIN chany_top_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 32.82 75.675 32.96 76.16 ;
+    END
+  END chany_top_out[17]
+  PIN chany_top_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 21.32 75.675 21.46 76.16 ;
+    END
+  END chany_top_out[18]
+  PIN chany_top_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 40.18 75.675 40.32 76.16 ;
+    END
+  END chany_top_out[19]
+  PIN left_grid_pin_0_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 20.59 0.8 20.89 ;
+    END
+  END left_grid_pin_0_[0]
+  PIN ccff_tail[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 23.99 66.24 24.29 ;
+    END
+  END ccff_tail[0]
+  PIN IO_ISOL_N[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 3.59 66.24 3.89 ;
+    END
+  END IO_ISOL_N[0]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 13.79 0.8 14.09 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 8.35 0.8 8.65 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 9.71 0.8 10.01 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]
+  PIN right_width_0_height_0__pin_0_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 21.95 0.8 22.25 ;
+    END
+  END right_width_0_height_0__pin_0_[0]
+  PIN right_width_0_height_0__pin_1_upper[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 20.4 75.675 20.54 76.16 ;
+    END
+  END right_width_0_height_0__pin_1_upper[0]
+  PIN right_width_0_height_0__pin_1_lower[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 26.38 0 26.52 0.485 ;
+    END
+  END right_width_0_height_0__pin_1_lower[0]
+  PIN prog_clk_0_E_in
+    DIRECTION INPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 10.39 66.24 10.69 ;
+    END
+  END prog_clk_0_E_in
+  PIN VDD
+    DIRECTION INPUT ;
+    USE POWER ;
+    PORT
+      LAYER met1 ;
+        RECT 0 2.48 0.48 2.96 ;
+        RECT 65.76 2.48 66.24 2.96 ;
+        RECT 0 7.92 0.48 8.4 ;
+        RECT 65.76 7.92 66.24 8.4 ;
+        RECT 0 13.36 0.48 13.84 ;
+        RECT 65.76 13.36 66.24 13.84 ;
+        RECT 0 18.8 0.48 19.28 ;
+        RECT 65.76 18.8 66.24 19.28 ;
+        RECT 0 24.24 0.48 24.72 ;
+        RECT 65.76 24.24 66.24 24.72 ;
+        RECT 0 29.68 0.48 30.16 ;
+        RECT 65.76 29.68 66.24 30.16 ;
+        RECT 0 35.12 0.48 35.6 ;
+        RECT 65.76 35.12 66.24 35.6 ;
+        RECT 0 40.56 0.48 41.04 ;
+        RECT 65.76 40.56 66.24 41.04 ;
+        RECT 0 46 0.48 46.48 ;
+        RECT 65.76 46 66.24 46.48 ;
+        RECT 0 51.44 0.48 51.92 ;
+        RECT 65.76 51.44 66.24 51.92 ;
+        RECT 0 56.88 0.48 57.36 ;
+        RECT 65.76 56.88 66.24 57.36 ;
+        RECT 0 62.32 0.48 62.8 ;
+        RECT 65.76 62.32 66.24 62.8 ;
+        RECT 0 67.76 0.48 68.24 ;
+        RECT 65.76 67.76 66.24 68.24 ;
+        RECT 0 73.2 0.48 73.68 ;
+        RECT 65.76 73.2 66.24 73.68 ;
+      LAYER met4 ;
+        RECT 10.74 0 11.34 0.6 ;
+        RECT 40.18 0 40.78 0.6 ;
+        RECT 10.74 75.56 11.34 76.16 ;
+        RECT 40.18 75.56 40.78 76.16 ;
+      LAYER met5 ;
+        RECT 0 5.88 3.2 9.08 ;
+        RECT 63.04 5.88 66.24 9.08 ;
+        RECT 0 46.68 3.2 49.88 ;
+        RECT 63.04 46.68 66.24 49.88 ;
+    END
+  END VDD
+  PIN VSS
+    DIRECTION INPUT ;
+    USE GROUND ;
+    PORT
+      LAYER met1 ;
+        RECT 0 0 45.4 0.24 ;
+        RECT 46.6 0 66.24 0.24 ;
+        RECT 0 5.2 0.48 5.68 ;
+        RECT 65.76 5.2 66.24 5.68 ;
+        RECT 0 10.64 0.48 11.12 ;
+        RECT 65.76 10.64 66.24 11.12 ;
+        RECT 0 16.08 0.48 16.56 ;
+        RECT 65.76 16.08 66.24 16.56 ;
+        RECT 0 21.52 0.48 22 ;
+        RECT 65.76 21.52 66.24 22 ;
+        RECT 0 26.96 0.48 27.44 ;
+        RECT 65.76 26.96 66.24 27.44 ;
+        RECT 0 32.4 0.48 32.88 ;
+        RECT 65.76 32.4 66.24 32.88 ;
+        RECT 0 37.84 0.48 38.32 ;
+        RECT 65.76 37.84 66.24 38.32 ;
+        RECT 0 43.28 0.48 43.76 ;
+        RECT 65.76 43.28 66.24 43.76 ;
+        RECT 0 48.72 0.48 49.2 ;
+        RECT 65.76 48.72 66.24 49.2 ;
+        RECT 0 54.16 0.48 54.64 ;
+        RECT 65.76 54.16 66.24 54.64 ;
+        RECT 0 59.6 0.48 60.08 ;
+        RECT 65.76 59.6 66.24 60.08 ;
+        RECT 0 65.04 0.48 65.52 ;
+        RECT 65.76 65.04 66.24 65.52 ;
+        RECT 0 70.48 0.48 70.96 ;
+        RECT 65.76 70.48 66.24 70.96 ;
+        RECT 0 75.92 45.4 76.16 ;
+        RECT 46.6 75.92 66.24 76.16 ;
+      LAYER met4 ;
+        RECT 25.46 0 26.06 0.6 ;
+        RECT 54.9 0 55.5 0.6 ;
+        RECT 25.46 75.56 26.06 76.16 ;
+        RECT 54.9 75.56 55.5 76.16 ;
+      LAYER met5 ;
+        RECT 0 26.28 3.2 29.48 ;
+        RECT 63.04 26.28 66.24 29.48 ;
+        RECT 0 67.08 3.2 70.28 ;
+        RECT 63.04 67.08 66.24 70.28 ;
+    END
+  END VSS
+  OBS
+    LAYER met2 ;
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+      RECT 25.62 75.975 25.9 76.345 ;
+      RECT 55.06 -0.185 55.34 0.185 ;
+      RECT 25.62 -0.185 25.9 0.185 ;
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+    LAYER met3 ;
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+      RECT 0 54.315 3.68 54.485 ;
+      RECT 65.78 51.595 66.24 51.765 ;
+      RECT 0 51.595 3.68 51.765 ;
+      RECT 65.78 48.875 66.24 49.045 ;
+      RECT 0 48.875 3.68 49.045 ;
+      RECT 65.78 46.155 66.24 46.325 ;
+      RECT 0 46.155 3.68 46.325 ;
+      RECT 62.56 43.435 66.24 43.605 ;
+      RECT 0 43.435 3.68 43.605 ;
+      RECT 62.56 40.715 66.24 40.885 ;
+      RECT 0 40.715 3.68 40.885 ;
+      RECT 64.4 37.995 66.24 38.165 ;
+      RECT 0 37.995 3.68 38.165 ;
+      RECT 62.56 35.275 66.24 35.445 ;
+      RECT 0 35.275 3.68 35.445 ;
+      RECT 62.56 32.555 66.24 32.725 ;
+      RECT 0 32.555 3.68 32.725 ;
+      RECT 62.56 29.835 66.24 30.005 ;
+      RECT 0 29.835 3.68 30.005 ;
+      RECT 62.56 27.115 66.24 27.285 ;
+      RECT 0 27.115 3.68 27.285 ;
+      RECT 65.32 24.395 66.24 24.565 ;
+      RECT 0 24.395 3.68 24.565 ;
+      RECT 65.32 21.675 66.24 21.845 ;
+      RECT 0 21.675 3.68 21.845 ;
+      RECT 65.32 18.955 66.24 19.125 ;
+      RECT 0 18.955 3.68 19.125 ;
+      RECT 65.78 16.235 66.24 16.405 ;
+      RECT 0 16.235 3.68 16.405 ;
+      RECT 65.32 13.515 66.24 13.685 ;
+      RECT 0 13.515 3.68 13.685 ;
+      RECT 65.32 10.795 66.24 10.965 ;
+      RECT 0 10.795 3.68 10.965 ;
+      RECT 65.32 8.075 66.24 8.245 ;
+      RECT 0 8.075 3.68 8.245 ;
+      RECT 65.32 5.355 66.24 5.525 ;
+      RECT 0 5.355 3.68 5.525 ;
+      RECT 62.56 2.635 66.24 2.805 ;
+      RECT 0 2.635 3.68 2.805 ;
+      RECT 0 -0.085 66.24 0.085 ;
+      RECT 0.17 0.17 66.07 75.99 ;
+    LAYER via ;
+      RECT 55.125 76.085 55.275 76.235 ;
+      RECT 25.685 76.085 25.835 76.235 ;
+      RECT 55.125 -0.075 55.275 0.075 ;
+      RECT 25.685 -0.075 25.835 0.075 ;
+    LAYER via2 ;
+      RECT 55.1 76.06 55.3 76.26 ;
+      RECT 25.66 76.06 25.86 76.26 ;
+      RECT 55.1 -0.1 55.3 0.1 ;
+      RECT 25.66 -0.1 25.86 0.1 ;
+    LAYER via3 ;
+      RECT 55.1 76.06 55.3 76.26 ;
+      RECT 25.66 76.06 25.86 76.26 ;
+      RECT 55.1 -0.1 55.3 0.1 ;
+      RECT 25.66 -0.1 25.86 0.1 ;
+    LAYER OVERLAP ;
+      POLYGON 0 0 0 76.16 66.24 76.16 66.24 0 ;
+  END
+END cby_0__1_
+
+END LIBRARY
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef
new file mode 100644
index 0000000..c831c57
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef
@@ -0,0 +1,1538 @@
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+
+UNITS
+  DATABASE MICRONS 1000 ;
+END UNITS
+
+MANUFACTURINGGRID 0.005 ;
+
+LAYER li1
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.17 ;
+END li1
+
+LAYER mcon
+  TYPE CUT ;
+END mcon
+
+LAYER met1
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.34 ;
+  WIDTH 0.14 ;
+END met1
+
+LAYER via
+  TYPE CUT ;
+END via
+
+LAYER met2
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.14 ;
+END met2
+
+LAYER via2
+  TYPE CUT ;
+END via2
+
+LAYER met3
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.68 ;
+  WIDTH 0.3 ;
+END met3
+
+LAYER via3
+  TYPE CUT ;
+END via3
+
+LAYER met4
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.92 ;
+  WIDTH 0.3 ;
+END met4
+
+LAYER via4
+  TYPE CUT ;
+END via4
+
+LAYER met5
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 3.4 ;
+  WIDTH 1.6 ;
+END met5
+
+LAYER nwell
+  TYPE MASTERSLICE ;
+END nwell
+
+LAYER pwell
+  TYPE MASTERSLICE ;
+END pwell
+
+LAYER OVERLAP
+  TYPE OVERLAP ;
+END OVERLAP
+
+VIA L1M1_PR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR
+
+VIA L1M1_PR_R
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_R
+
+VIA L1M1_PR_M
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_M
+
+VIA L1M1_PR_MR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR_MR
+
+VIA L1M1_PR_C
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.145 0.145 0.145 ;
+END L1M1_PR_C
+
+VIA M1M2_PR
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR
+
+VIA M1M2_PR_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_Enc
+
+VIA M1M2_PR_R
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_R
+
+VIA M1M2_PR_R_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_R_Enc
+
+VIA M1M2_PR_M
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIA M1M2_PR_M_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_M_Enc
+
+VIA M1M2_PR_MR
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIA M1M2_PR_MR_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_MR_Enc
+
+VIA M1M2_PR_C
+  LAYER met1 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIA M2M3_PR
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIA M2M3_PR_R
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIA M2M3_PR_M
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIA M2M3_PR_MR
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIA M2M3_PR_C
+  LAYER met2 ;
+    RECT -0.185 -0.185 0.185 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIA M3M4_PR
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIA M3M4_PR_R
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIA M3M4_PR_M
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIA M3M4_PR_MR
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIA M3M4_PR_C
+  LAYER met3 ;
+    RECT -0.19 -0.19 0.19 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIA M4M5_PR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIA M4M5_PR_R
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIA M4M5_PR_M
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIA M4M5_PR_MR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIA M4M5_PR_C
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+  CLASS CORE ;
+  SYMMETRY Y ;
+  SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+  CLASS CORE ;
+  SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+MACRO cby_1__1_
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 66.24 BY 76.16 ;
+  SYMMETRY X Y ;
+  PIN chany_bottom_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 45.24 0 45.38 0.485 ;
+    END
+  END chany_bottom_in[0]
+  PIN chany_bottom_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 51.68 0 51.82 0.485 ;
+    END
+  END chany_bottom_in[1]
+  PIN chany_bottom_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 48.92 0 49.06 0.485 ;
+    END
+  END chany_bottom_in[2]
+  PIN chany_bottom_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.6 0 52.74 0.485 ;
+    END
+  END chany_bottom_in[3]
+  PIN chany_bottom_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.5 0 13.64 0.485 ;
+    END
+  END chany_bottom_in[4]
+  PIN chany_bottom_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 34.66 0 34.8 0.485 ;
+    END
+  END chany_bottom_in[5]
+  PIN chany_bottom_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 28.68 0 28.82 0.485 ;
+    END
+  END chany_bottom_in[6]
+  PIN chany_bottom_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 39.72 0 39.86 0.485 ;
+    END
+  END chany_bottom_in[7]
+  PIN chany_bottom_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 40.64 0 40.78 0.485 ;
+    END
+  END chany_bottom_in[8]
+  PIN chany_bottom_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.52 0 53.66 0.485 ;
+    END
+  END chany_bottom_in[9]
+  PIN chany_bottom_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 31.9 0 32.04 0.485 ;
+    END
+  END chany_bottom_in[10]
+  PIN chany_bottom_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 37.42 0 37.56 0.485 ;
+    END
+  END chany_bottom_in[11]
+  PIN chany_bottom_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 43.4 0 43.54 0.485 ;
+    END
+  END chany_bottom_in[12]
+  PIN chany_bottom_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 50.76 0 50.9 0.485 ;
+    END
+  END chany_bottom_in[13]
+  PIN chany_bottom_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 26.38 0 26.52 0.485 ;
+    END
+  END chany_bottom_in[14]
+  PIN chany_bottom_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 38.8 0 38.94 0.485 ;
+    END
+  END chany_bottom_in[15]
+  PIN chany_bottom_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 27.3 0 27.44 0.485 ;
+    END
+  END chany_bottom_in[16]
+  PIN chany_bottom_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 44.32 0 44.46 0.485 ;
+    END
+  END chany_bottom_in[17]
+  PIN chany_bottom_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 33.74 0 33.88 0.485 ;
+    END
+  END chany_bottom_in[18]
+  PIN chany_bottom_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 49.84 0 49.98 0.485 ;
+    END
+  END chany_bottom_in[19]
+  PIN chany_top_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 40.18 75.675 40.32 76.16 ;
+    END
+  END chany_top_in[0]
+  PIN chany_top_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.5 75.675 59.64 76.16 ;
+    END
+  END chany_top_in[1]
+  PIN chany_top_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 9.82 75.675 9.96 76.16 ;
+    END
+  END chany_top_in[2]
+  PIN chany_top_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 57.66 75.675 57.8 76.16 ;
+    END
+  END chany_top_in[3]
+  PIN chany_top_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 12.58 75.675 12.72 76.16 ;
+    END
+  END chany_top_in[4]
+  PIN chany_top_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 47.54 75.675 47.68 76.16 ;
+    END
+  END chany_top_in[5]
+  PIN chany_top_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 50.3 75.675 50.44 76.16 ;
+    END
+  END chany_top_in[6]
+  PIN chany_top_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 11.66 75.675 11.8 76.16 ;
+    END
+  END chany_top_in[7]
+  PIN chany_top_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 34.66 75.675 34.8 76.16 ;
+    END
+  END chany_top_in[8]
+  PIN chany_top_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 38.34 75.675 38.48 76.16 ;
+    END
+  END chany_top_in[9]
+  PIN chany_top_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 42.02 75.675 42.16 76.16 ;
+    END
+  END chany_top_in[10]
+  PIN chany_top_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 48.46 75.675 48.6 76.16 ;
+    END
+  END chany_top_in[11]
+  PIN chany_top_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 33.74 75.675 33.88 76.16 ;
+    END
+  END chany_top_in[12]
+  PIN chany_top_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 29.14 75.675 29.28 76.16 ;
+    END
+  END chany_top_in[13]
+  PIN chany_top_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 28.22 75.675 28.36 76.16 ;
+    END
+  END chany_top_in[14]
+  PIN chany_top_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 39.26 75.675 39.4 76.16 ;
+    END
+  END chany_top_in[15]
+  PIN chany_top_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 32.82 75.675 32.96 76.16 ;
+    END
+  END chany_top_in[16]
+  PIN chany_top_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 37.42 75.675 37.56 76.16 ;
+    END
+  END chany_top_in[17]
+  PIN chany_top_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 26.38 75.675 26.52 76.16 ;
+    END
+  END chany_top_in[18]
+  PIN chany_top_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 27.3 75.675 27.44 76.16 ;
+    END
+  END chany_top_in[19]
+  PIN ccff_head[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 6.31 0.8 6.61 ;
+    END
+  END ccff_head[0]
+  PIN chany_bottom_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 36.19 0 36.49 0.8 ;
+    END
+  END chany_bottom_out[0]
+  PIN chany_bottom_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.58 0 58.72 0.485 ;
+    END
+  END chany_bottom_out[1]
+  PIN chany_bottom_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 57.66 0 57.8 0.485 ;
+    END
+  END chany_bottom_out[2]
+  PIN chany_bottom_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 48.15 0 48.45 0.8 ;
+    END
+  END chany_bottom_out[3]
+  PIN chany_bottom_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 55.82 0 55.96 0.485 ;
+    END
+  END chany_bottom_out[4]
+  PIN chany_bottom_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 30.67 0 30.97 0.8 ;
+    END
+  END chany_bottom_out[5]
+  PIN chany_bottom_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 29.6 0 29.74 0.485 ;
+    END
+  END chany_bottom_out[6]
+  PIN chany_bottom_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 34.35 0 34.65 0.8 ;
+    END
+  END chany_bottom_out[7]
+  PIN chany_bottom_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.5 0 59.64 0.485 ;
+    END
+  END chany_bottom_out[8]
+  PIN chany_bottom_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 62.26 0 62.4 0.485 ;
+    END
+  END chany_bottom_out[9]
+  PIN chany_bottom_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 56.74 0 56.88 0.485 ;
+    END
+  END chany_bottom_out[10]
+  PIN chany_bottom_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.18 0 63.32 0.485 ;
+    END
+  END chany_bottom_out[11]
+  PIN chany_bottom_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 41.71 0 42.01 0.8 ;
+    END
+  END chany_bottom_out[12]
+  PIN chany_bottom_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 41.56 0 41.7 0.485 ;
+    END
+  END chany_bottom_out[13]
+  PIN chany_bottom_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 26.99 0 27.29 0.8 ;
+    END
+  END chany_bottom_out[14]
+  PIN chany_bottom_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 32.51 0 32.81 0.8 ;
+    END
+  END chany_bottom_out[15]
+  PIN chany_bottom_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 32.82 0 32.96 0.485 ;
+    END
+  END chany_bottom_out[16]
+  PIN chany_bottom_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 28.83 0 29.13 0.8 ;
+    END
+  END chany_bottom_out[17]
+  PIN chany_bottom_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 38.03 0 38.33 0.8 ;
+    END
+  END chany_bottom_out[18]
+  PIN chany_bottom_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 43.55 0 43.85 0.8 ;
+    END
+  END chany_bottom_out[19]
+  PIN chany_top_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.64 75.675 63.78 76.16 ;
+    END
+  END chany_top_out[0]
+  PIN chany_top_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 26.99 75.36 27.29 76.16 ;
+    END
+  END chany_top_out[1]
+  PIN chany_top_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.58 75.675 58.72 76.16 ;
+    END
+  END chany_top_out[2]
+  PIN chany_top_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 54.44 75.675 54.58 76.16 ;
+    END
+  END chany_top_out[3]
+  PIN chany_top_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 55.82 75.675 55.96 76.16 ;
+    END
+  END chany_top_out[4]
+  PIN chany_top_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.5 75.675 13.64 76.16 ;
+    END
+  END chany_top_out[5]
+  PIN chany_top_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 49.07 75.36 49.37 76.16 ;
+    END
+  END chany_top_out[6]
+  PIN chany_top_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 8.9 75.675 9.04 76.16 ;
+    END
+  END chany_top_out[7]
+  PIN chany_top_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.52 75.675 53.66 76.16 ;
+    END
+  END chany_top_out[8]
+  PIN chany_top_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 41.1 75.675 41.24 76.16 ;
+    END
+  END chany_top_out[9]
+  PIN chany_top_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 51.22 75.675 51.36 76.16 ;
+    END
+  END chany_top_out[10]
+  PIN chany_top_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 49.38 75.675 49.52 76.16 ;
+    END
+  END chany_top_out[11]
+  PIN chany_top_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 60.42 75.675 60.56 76.16 ;
+    END
+  END chany_top_out[12]
+  PIN chany_top_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 14.42 75.675 14.56 76.16 ;
+    END
+  END chany_top_out[13]
+  PIN chany_top_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.06 75.675 7.2 76.16 ;
+    END
+  END chany_top_out[14]
+  PIN chany_top_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 10.74 75.675 10.88 76.16 ;
+    END
+  END chany_top_out[15]
+  PIN chany_top_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 56.74 75.675 56.88 76.16 ;
+    END
+  END chany_top_out[16]
+  PIN chany_top_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 31.9 75.675 32.04 76.16 ;
+    END
+  END chany_top_out[17]
+  PIN chany_top_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 36.5 75.675 36.64 76.16 ;
+    END
+  END chany_top_out[18]
+  PIN chany_top_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 30.06 75.675 30.2 76.16 ;
+    END
+  END chany_top_out[19]
+  PIN left_grid_pin_16_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 26.03 0.8 26.33 ;
+    END
+  END left_grid_pin_16_[0]
+  PIN left_grid_pin_17_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 21.95 0.8 22.25 ;
+    END
+  END left_grid_pin_17_[0]
+  PIN left_grid_pin_18_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 23.31 0.8 23.61 ;
+    END
+  END left_grid_pin_18_[0]
+  PIN left_grid_pin_19_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 43.03 0.8 43.33 ;
+    END
+  END left_grid_pin_19_[0]
+  PIN left_grid_pin_20_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 45.75 0.8 46.05 ;
+    END
+  END left_grid_pin_20_[0]
+  PIN left_grid_pin_21_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 47.11 0.8 47.41 ;
+    END
+  END left_grid_pin_21_[0]
+  PIN left_grid_pin_22_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 44.39 0.8 44.69 ;
+    END
+  END left_grid_pin_22_[0]
+  PIN left_grid_pin_23_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 24.67 0.8 24.97 ;
+    END
+  END left_grid_pin_23_[0]
+  PIN left_grid_pin_24_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 49.83 0.8 50.13 ;
+    END
+  END left_grid_pin_24_[0]
+  PIN left_grid_pin_25_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 19.23 0.8 19.53 ;
+    END
+  END left_grid_pin_25_[0]
+  PIN left_grid_pin_26_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 4.95 0.8 5.25 ;
+    END
+  END left_grid_pin_26_[0]
+  PIN left_grid_pin_27_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 7.67 0.8 7.97 ;
+    END
+  END left_grid_pin_27_[0]
+  PIN left_grid_pin_28_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 10.39 0.8 10.69 ;
+    END
+  END left_grid_pin_28_[0]
+  PIN left_grid_pin_29_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 9.03 0.8 9.33 ;
+    END
+  END left_grid_pin_29_[0]
+  PIN left_grid_pin_30_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 48.47 0.8 48.77 ;
+    END
+  END left_grid_pin_30_[0]
+  PIN left_grid_pin_31_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 20.59 0.8 20.89 ;
+    END
+  END left_grid_pin_31_[0]
+  PIN ccff_tail[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 23.99 66.24 24.29 ;
+    END
+  END ccff_tail[0]
+  PIN Test_en_S_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 48 0 48.14 0.485 ;
+    END
+  END Test_en_S_in
+  PIN Test_en_E_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 38.27 66.24 38.57 ;
+    END
+  END Test_en_E_in
+  PIN Test_en_W_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 33.51 0.8 33.81 ;
+    END
+  END Test_en_W_in
+  PIN Test_en_N_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.6 75.675 52.74 76.16 ;
+    END
+  END Test_en_N_out
+  PIN Test_en_W_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 34.87 0.8 35.17 ;
+    END
+  END Test_en_W_out
+  PIN Test_en_E_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 34.87 66.24 35.17 ;
+    END
+  END Test_en_E_out
+  PIN prog_clk_0_W_in
+    DIRECTION INPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met3 ;
+        RECT 0 3.59 0.8 3.89 ;
+    END
+  END prog_clk_0_W_in
+  PIN prog_clk_0_S_out
+    DIRECTION OUTPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met2 ;
+        RECT 12.58 0 12.72 0.485 ;
+    END
+  END prog_clk_0_S_out
+  PIN prog_clk_0_N_out
+    DIRECTION OUTPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met2 ;
+        RECT 7.98 75.675 8.12 76.16 ;
+    END
+  END prog_clk_0_N_out
+  PIN prog_clk_2_N_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 43.4 75.675 43.54 76.16 ;
+    END
+  END prog_clk_2_N_in
+  PIN prog_clk_2_S_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.34 0 61.48 0.485 ;
+    END
+  END prog_clk_2_S_in
+  PIN prog_clk_2_S_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 35.58 0 35.72 0.485 ;
+    END
+  END prog_clk_2_S_out
+  PIN prog_clk_2_N_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 35.58 75.675 35.72 76.16 ;
+    END
+  END prog_clk_2_N_out
+  PIN prog_clk_3_S_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 60.42 0 60.56 0.485 ;
+    END
+  END prog_clk_3_S_in
+  PIN prog_clk_3_N_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 44.32 75.675 44.46 76.16 ;
+    END
+  END prog_clk_3_N_in
+  PIN prog_clk_3_N_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.8 75.675 61.94 76.16 ;
+    END
+  END prog_clk_3_N_out
+  PIN prog_clk_3_S_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 46.62 0 46.76 0.485 ;
+    END
+  END prog_clk_3_S_out
+  PIN clk_2_N_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 45.24 75.675 45.38 76.16 ;
+    END
+  END clk_2_N_in
+  PIN clk_2_S_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 54.44 0 54.58 0.485 ;
+    END
+  END clk_2_S_in
+  PIN clk_2_S_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 30.98 0 31.12 0.485 ;
+    END
+  END clk_2_S_out
+  PIN clk_2_N_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 30.98 75.675 31.12 76.16 ;
+    END
+  END clk_2_N_out
+  PIN clk_3_S_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 42.48 0 42.62 0.485 ;
+    END
+  END clk_3_S_in
+  PIN clk_3_N_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 46.62 75.675 46.76 76.16 ;
+    END
+  END clk_3_N_in
+  PIN clk_3_N_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 62.72 75.675 62.86 76.16 ;
+    END
+  END clk_3_N_out
+  PIN clk_3_S_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 36.5 0 36.64 0.485 ;
+    END
+  END clk_3_S_out
+  PIN VDD
+    DIRECTION INPUT ;
+    USE POWER ;
+    PORT
+      LAYER met1 ;
+        RECT 0 2.48 0.48 2.96 ;
+        RECT 65.76 2.48 66.24 2.96 ;
+        RECT 0 7.92 0.48 8.4 ;
+        RECT 65.76 7.92 66.24 8.4 ;
+        RECT 0 13.36 0.48 13.84 ;
+        RECT 65.76 13.36 66.24 13.84 ;
+        RECT 0 18.8 0.48 19.28 ;
+        RECT 65.76 18.8 66.24 19.28 ;
+        RECT 0 24.24 0.48 24.72 ;
+        RECT 65.76 24.24 66.24 24.72 ;
+        RECT 0 29.68 0.48 30.16 ;
+        RECT 65.76 29.68 66.24 30.16 ;
+        RECT 0 35.12 0.48 35.6 ;
+        RECT 65.76 35.12 66.24 35.6 ;
+        RECT 0 40.56 0.48 41.04 ;
+        RECT 65.76 40.56 66.24 41.04 ;
+        RECT 0 46 0.48 46.48 ;
+        RECT 65.76 46 66.24 46.48 ;
+        RECT 0 51.44 0.48 51.92 ;
+        RECT 65.76 51.44 66.24 51.92 ;
+        RECT 0 56.88 0.48 57.36 ;
+        RECT 65.76 56.88 66.24 57.36 ;
+        RECT 0 62.32 0.48 62.8 ;
+        RECT 65.76 62.32 66.24 62.8 ;
+        RECT 0 67.76 0.48 68.24 ;
+        RECT 65.76 67.76 66.24 68.24 ;
+        RECT 0 73.2 0.48 73.68 ;
+        RECT 65.76 73.2 66.24 73.68 ;
+      LAYER met4 ;
+        RECT 10.74 0 11.34 0.6 ;
+        RECT 40.18 0 40.78 0.6 ;
+        RECT 10.74 75.56 11.34 76.16 ;
+        RECT 40.18 75.56 40.78 76.16 ;
+      LAYER met5 ;
+        RECT 0 5.88 3.2 9.08 ;
+        RECT 63.04 5.88 66.24 9.08 ;
+        RECT 0 46.68 3.2 49.88 ;
+        RECT 63.04 46.68 66.24 49.88 ;
+    END
+  END VDD
+  PIN VSS
+    DIRECTION INPUT ;
+    USE GROUND ;
+    PORT
+      LAYER met1 ;
+        RECT 0 0 45.4 0.24 ;
+        RECT 46.6 0 66.24 0.24 ;
+        RECT 0 5.2 0.48 5.68 ;
+        RECT 65.76 5.2 66.24 5.68 ;
+        RECT 0 10.64 0.48 11.12 ;
+        RECT 65.76 10.64 66.24 11.12 ;
+        RECT 0 16.08 0.48 16.56 ;
+        RECT 65.76 16.08 66.24 16.56 ;
+        RECT 0 21.52 0.48 22 ;
+        RECT 65.76 21.52 66.24 22 ;
+        RECT 0 26.96 0.48 27.44 ;
+        RECT 65.76 26.96 66.24 27.44 ;
+        RECT 0 32.4 0.48 32.88 ;
+        RECT 65.76 32.4 66.24 32.88 ;
+        RECT 0 37.84 0.48 38.32 ;
+        RECT 65.76 37.84 66.24 38.32 ;
+        RECT 0 43.28 0.48 43.76 ;
+        RECT 65.76 43.28 66.24 43.76 ;
+        RECT 0 48.72 0.48 49.2 ;
+        RECT 65.76 48.72 66.24 49.2 ;
+        RECT 0 54.16 0.48 54.64 ;
+        RECT 65.76 54.16 66.24 54.64 ;
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diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef
new file mode 100644
index 0000000..d0d6b9c
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef
@@ -0,0 +1,1427 @@
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+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR_MR
+
+VIA L1M1_PR_C
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.145 0.145 0.145 ;
+END L1M1_PR_C
+
+VIA M1M2_PR
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR
+
+VIA M1M2_PR_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_Enc
+
+VIA M1M2_PR_R
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_R
+
+VIA M1M2_PR_R_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_R_Enc
+
+VIA M1M2_PR_M
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIA M1M2_PR_M_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_M_Enc
+
+VIA M1M2_PR_MR
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIA M1M2_PR_MR_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_MR_Enc
+
+VIA M1M2_PR_C
+  LAYER met1 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIA M2M3_PR
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIA M2M3_PR_R
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIA M2M3_PR_M
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIA M2M3_PR_MR
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIA M2M3_PR_C
+  LAYER met2 ;
+    RECT -0.185 -0.185 0.185 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIA M3M4_PR
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIA M3M4_PR_R
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIA M3M4_PR_M
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIA M3M4_PR_MR
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIA M3M4_PR_C
+  LAYER met3 ;
+    RECT -0.19 -0.19 0.19 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIA M4M5_PR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIA M4M5_PR_R
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIA M4M5_PR_M
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIA M4M5_PR_MR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIA M4M5_PR_C
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+  CLASS CORE ;
+  SYMMETRY Y ;
+  SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+  CLASS CORE ;
+  SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+MACRO cby_2__1_
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 66.24 BY 76.16 ;
+  SYMMETRY X Y ;
+  PIN chany_bottom_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 50.76 0 50.9 0.485 ;
+    END
+  END chany_bottom_in[0]
+  PIN chany_bottom_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 18.1 0 18.24 0.485 ;
+    END
+  END chany_bottom_in[1]
+  PIN chany_bottom_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 49.84 0 49.98 0.485 ;
+    END
+  END chany_bottom_in[2]
+  PIN chany_bottom_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 51.68 0 51.82 0.485 ;
+    END
+  END chany_bottom_in[3]
+  PIN chany_bottom_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 34.2 0 34.34 0.485 ;
+    END
+  END chany_bottom_in[4]
+  PIN chany_bottom_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 20.86 0 21 0.485 ;
+    END
+  END chany_bottom_in[5]
+  PIN chany_bottom_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 29.14 0 29.28 0.485 ;
+    END
+  END chany_bottom_in[6]
+  PIN chany_bottom_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.6 0 52.74 0.485 ;
+    END
+  END chany_bottom_in[7]
+  PIN chany_bottom_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 41.1 0 41.24 0.485 ;
+    END
+  END chany_bottom_in[8]
+  PIN chany_bottom_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 30.06 0 30.2 0.485 ;
+    END
+  END chany_bottom_in[9]
+  PIN chany_bottom_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 21.78 0 21.92 0.485 ;
+    END
+  END chany_bottom_in[10]
+  PIN chany_bottom_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 35.58 0 35.72 0.485 ;
+    END
+  END chany_bottom_in[11]
+  PIN chany_bottom_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 12.58 0 12.72 0.485 ;
+    END
+  END chany_bottom_in[12]
+  PIN chany_bottom_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.52 0 53.66 0.485 ;
+    END
+  END chany_bottom_in[13]
+  PIN chany_bottom_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 25 0 25.14 0.485 ;
+    END
+  END chany_bottom_in[14]
+  PIN chany_bottom_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 24.08 0 24.22 0.485 ;
+    END
+  END chany_bottom_in[15]
+  PIN chany_bottom_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 6.6 0 6.74 0.485 ;
+    END
+  END chany_bottom_in[16]
+  PIN chany_bottom_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 46.16 0 46.3 0.485 ;
+    END
+  END chany_bottom_in[17]
+  PIN chany_bottom_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.52 0 7.66 0.485 ;
+    END
+  END chany_bottom_in[18]
+  PIN chany_bottom_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 45.24 0 45.38 0.485 ;
+    END
+  END chany_bottom_in[19]
+  PIN chany_top_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 12.58 75.675 12.72 76.16 ;
+    END
+  END chany_top_in[0]
+  PIN chany_top_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 48.92 75.675 49.06 76.16 ;
+    END
+  END chany_top_in[1]
+  PIN chany_top_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 5.68 75.675 5.82 76.16 ;
+    END
+  END chany_top_in[2]
+  PIN chany_top_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 36.5 75.675 36.64 76.16 ;
+    END
+  END chany_top_in[3]
+  PIN chany_top_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 39.72 75.675 39.86 76.16 ;
+    END
+  END chany_top_in[4]
+  PIN chany_top_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 23.62 75.675 23.76 76.16 ;
+    END
+  END chany_top_in[5]
+  PIN chany_top_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 41.56 75.675 41.7 76.16 ;
+    END
+  END chany_top_in[6]
+  PIN chany_top_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 42.48 75.675 42.62 76.16 ;
+    END
+  END chany_top_in[7]
+  PIN chany_top_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 33.28 75.675 33.42 76.16 ;
+    END
+  END chany_top_in[8]
+  PIN chany_top_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 24.54 75.675 24.68 76.16 ;
+    END
+  END chany_top_in[9]
+  PIN chany_top_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 9.36 75.675 9.5 76.16 ;
+    END
+  END chany_top_in[10]
+  PIN chany_top_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 35.58 75.675 35.72 76.16 ;
+    END
+  END chany_top_in[11]
+  PIN chany_top_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 34.2 75.675 34.34 76.16 ;
+    END
+  END chany_top_in[12]
+  PIN chany_top_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 56.74 75.675 56.88 76.16 ;
+    END
+  END chany_top_in[13]
+  PIN chany_top_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 30.52 75.675 30.66 76.16 ;
+    END
+  END chany_top_in[14]
+  PIN chany_top_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 32.36 75.675 32.5 76.16 ;
+    END
+  END chany_top_in[15]
+  PIN chany_top_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 22.24 75.675 22.38 76.16 ;
+    END
+  END chany_top_in[16]
+  PIN chany_top_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 47.08 75.675 47.22 76.16 ;
+    END
+  END chany_top_in[17]
+  PIN chany_top_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.98 75.675 8.12 76.16 ;
+    END
+  END chany_top_in[18]
+  PIN chany_top_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 46.16 75.675 46.3 76.16 ;
+    END
+  END chany_top_in[19]
+  PIN ccff_head[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 6.31 0.8 6.61 ;
+    END
+  END ccff_head[0]
+  PIN chany_bottom_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 30.98 0 31.12 0.485 ;
+    END
+  END chany_bottom_out[0]
+  PIN chany_bottom_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 33.28 0 33.42 0.485 ;
+    END
+  END chany_bottom_out[1]
+  PIN chany_bottom_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 39.26 0 39.4 0.485 ;
+    END
+  END chany_bottom_out[2]
+  PIN chany_bottom_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 44.32 0 44.46 0.485 ;
+    END
+  END chany_bottom_out[3]
+  PIN chany_bottom_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 37.42 0 37.56 0.485 ;
+    END
+  END chany_bottom_out[4]
+  PIN chany_bottom_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 42.02 0 42.16 0.485 ;
+    END
+  END chany_bottom_out[5]
+  PIN chany_bottom_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 26.38 0 26.52 0.485 ;
+    END
+  END chany_bottom_out[6]
+  PIN chany_bottom_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 27.3 0 27.44 0.485 ;
+    END
+  END chany_bottom_out[7]
+  PIN chany_bottom_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 19.94 0 20.08 0.485 ;
+    END
+  END chany_bottom_out[8]
+  PIN chany_bottom_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 40.18 0 40.32 0.485 ;
+    END
+  END chany_bottom_out[9]
+  PIN chany_bottom_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 38.34 0 38.48 0.485 ;
+    END
+  END chany_bottom_out[10]
+  PIN chany_bottom_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 48.92 0 49.06 0.485 ;
+    END
+  END chany_bottom_out[11]
+  PIN chany_bottom_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 36.5 0 36.64 0.485 ;
+    END
+  END chany_bottom_out[12]
+  PIN chany_bottom_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 47.08 0 47.22 0.485 ;
+    END
+  END chany_bottom_out[13]
+  PIN chany_bottom_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 28.22 0 28.36 0.485 ;
+    END
+  END chany_bottom_out[14]
+  PIN chany_bottom_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 32.36 0 32.5 0.485 ;
+    END
+  END chany_bottom_out[15]
+  PIN chany_bottom_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 22.7 0 22.84 0.485 ;
+    END
+  END chany_bottom_out[16]
+  PIN chany_bottom_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 48 0 48.14 0.485 ;
+    END
+  END chany_bottom_out[17]
+  PIN chany_bottom_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 19.02 0 19.16 0.485 ;
+    END
+  END chany_bottom_out[18]
+  PIN chany_bottom_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 43.4 0 43.54 0.485 ;
+    END
+  END chany_bottom_out[19]
+  PIN chany_top_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 44.32 75.675 44.46 76.16 ;
+    END
+  END chany_top_out[0]
+  PIN chany_top_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 55.82 75.675 55.96 76.16 ;
+    END
+  END chany_top_out[1]
+  PIN chany_top_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 31.44 75.675 31.58 76.16 ;
+    END
+  END chany_top_out[2]
+  PIN chany_top_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 54.44 75.675 54.58 76.16 ;
+    END
+  END chany_top_out[3]
+  PIN chany_top_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 38.8 75.675 38.94 76.16 ;
+    END
+  END chany_top_out[4]
+  PIN chany_top_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 50.76 75.675 50.9 76.16 ;
+    END
+  END chany_top_out[5]
+  PIN chany_top_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 29.6 75.675 29.74 76.16 ;
+    END
+  END chany_top_out[6]
+  PIN chany_top_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 48 75.675 48.14 76.16 ;
+    END
+  END chany_top_out[7]
+  PIN chany_top_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 37.88 75.675 38.02 76.16 ;
+    END
+  END chany_top_out[8]
+  PIN chany_top_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 43.4 75.675 43.54 76.16 ;
+    END
+  END chany_top_out[9]
+  PIN chany_top_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 26.38 75.675 26.52 76.16 ;
+    END
+  END chany_top_out[10]
+  PIN chany_top_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 45.24 75.675 45.38 76.16 ;
+    END
+  END chany_top_out[11]
+  PIN chany_top_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 49.84 75.675 49.98 76.16 ;
+    END
+  END chany_top_out[12]
+  PIN chany_top_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.6 75.675 52.74 76.16 ;
+    END
+  END chany_top_out[13]
+  PIN chany_top_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 28.68 75.675 28.82 76.16 ;
+    END
+  END chany_top_out[14]
+  PIN chany_top_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 40.64 75.675 40.78 76.16 ;
+    END
+  END chany_top_out[15]
+  PIN chany_top_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 21.32 75.675 21.46 76.16 ;
+    END
+  END chany_top_out[16]
+  PIN chany_top_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 51.68 75.675 51.82 76.16 ;
+    END
+  END chany_top_out[17]
+  PIN chany_top_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 27.3 75.675 27.44 76.16 ;
+    END
+  END chany_top_out[18]
+  PIN chany_top_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.52 75.675 53.66 76.16 ;
+    END
+  END chany_top_out[19]
+  PIN right_grid_pin_0_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 14.47 0.8 14.77 ;
+    END
+  END right_grid_pin_0_[0]
+  PIN left_grid_pin_16_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 26.03 0.8 26.33 ;
+    END
+  END left_grid_pin_16_[0]
+  PIN left_grid_pin_17_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 21.95 0.8 22.25 ;
+    END
+  END left_grid_pin_17_[0]
+  PIN left_grid_pin_18_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 23.31 0.8 23.61 ;
+    END
+  END left_grid_pin_18_[0]
+  PIN left_grid_pin_19_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 43.03 0.8 43.33 ;
+    END
+  END left_grid_pin_19_[0]
+  PIN left_grid_pin_20_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 45.75 0.8 46.05 ;
+    END
+  END left_grid_pin_20_[0]
+  PIN left_grid_pin_21_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 47.11 0.8 47.41 ;
+    END
+  END left_grid_pin_21_[0]
+  PIN left_grid_pin_22_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 44.39 0.8 44.69 ;
+    END
+  END left_grid_pin_22_[0]
+  PIN left_grid_pin_23_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 24.67 0.8 24.97 ;
+    END
+  END left_grid_pin_23_[0]
+  PIN left_grid_pin_24_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 49.83 0.8 50.13 ;
+    END
+  END left_grid_pin_24_[0]
+  PIN left_grid_pin_25_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 19.23 0.8 19.53 ;
+    END
+  END left_grid_pin_25_[0]
+  PIN left_grid_pin_26_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 4.95 0.8 5.25 ;
+    END
+  END left_grid_pin_26_[0]
+  PIN left_grid_pin_27_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 7.67 0.8 7.97 ;
+    END
+  END left_grid_pin_27_[0]
+  PIN left_grid_pin_28_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 10.39 0.8 10.69 ;
+    END
+  END left_grid_pin_28_[0]
+  PIN left_grid_pin_29_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 9.03 0.8 9.33 ;
+    END
+  END left_grid_pin_29_[0]
+  PIN left_grid_pin_30_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 48.47 0.8 48.77 ;
+    END
+  END left_grid_pin_30_[0]
+  PIN left_grid_pin_31_[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 20.59 0.8 20.89 ;
+    END
+  END left_grid_pin_31_[0]
+  PIN ccff_tail[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 4.76 0 4.9 0.485 ;
+    END
+  END ccff_tail[0]
+  PIN IO_ISOL_N[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 11.75 0.8 12.05 ;
+    END
+  END IO_ISOL_N[0]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 10.39 66.24 10.69 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 6.31 66.24 6.61 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]
+  PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 65.44 4.95 66.24 5.25 ;
+    END
+  END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]
+  PIN left_width_0_height_0__pin_0_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 13.11 0.8 13.41 ;
+    END
+  END left_width_0_height_0__pin_0_[0]
+  PIN left_width_0_height_0__pin_1_upper[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 6.6 75.675 6.74 76.16 ;
+    END
+  END left_width_0_height_0__pin_1_upper[0]
+  PIN left_width_0_height_0__pin_1_lower[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 5.68 0 5.82 0.485 ;
+    END
+  END left_width_0_height_0__pin_1_lower[0]
+  PIN prog_clk_0_W_in
+    DIRECTION INPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met3 ;
+        RECT 0 3.59 0.8 3.89 ;
+    END
+  END prog_clk_0_W_in
+  PIN prog_clk_0_S_out
+    DIRECTION OUTPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met2 ;
+        RECT 11.66 0 11.8 0.485 ;
+    END
+  END prog_clk_0_S_out
+  PIN prog_clk_0_N_out
+    DIRECTION OUTPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met2 ;
+        RECT 13.5 75.675 13.64 76.16 ;
+    END
+  END prog_clk_0_N_out
+  PIN VDD
+    DIRECTION INPUT ;
+    USE POWER ;
+    PORT
+      LAYER met1 ;
+        RECT 0 2.48 0.48 2.96 ;
+        RECT 65.76 2.48 66.24 2.96 ;
+        RECT 0 7.92 0.48 8.4 ;
+        RECT 65.76 7.92 66.24 8.4 ;
+        RECT 0 13.36 0.48 13.84 ;
+        RECT 65.76 13.36 66.24 13.84 ;
+        RECT 0 18.8 0.48 19.28 ;
+        RECT 65.76 18.8 66.24 19.28 ;
+        RECT 0 24.24 0.48 24.72 ;
+        RECT 65.76 24.24 66.24 24.72 ;
+        RECT 0 29.68 0.48 30.16 ;
+        RECT 65.76 29.68 66.24 30.16 ;
+        RECT 0 35.12 0.48 35.6 ;
+        RECT 65.76 35.12 66.24 35.6 ;
+        RECT 0 40.56 0.48 41.04 ;
+        RECT 65.76 40.56 66.24 41.04 ;
+        RECT 0 46 0.48 46.48 ;
+        RECT 65.76 46 66.24 46.48 ;
+        RECT 0 51.44 0.48 51.92 ;
+        RECT 65.76 51.44 66.24 51.92 ;
+        RECT 0 56.88 0.48 57.36 ;
+        RECT 65.76 56.88 66.24 57.36 ;
+        RECT 0 62.32 0.48 62.8 ;
+        RECT 65.76 62.32 66.24 62.8 ;
+        RECT 0 67.76 0.48 68.24 ;
+        RECT 65.76 67.76 66.24 68.24 ;
+        RECT 0 73.2 0.48 73.68 ;
+        RECT 65.76 73.2 66.24 73.68 ;
+      LAYER met4 ;
+        RECT 10.74 0 11.34 0.6 ;
+        RECT 40.18 0 40.78 0.6 ;
+        RECT 10.74 75.56 11.34 76.16 ;
+        RECT 40.18 75.56 40.78 76.16 ;
+      LAYER met5 ;
+        RECT 0 5.88 3.2 9.08 ;
+        RECT 63.04 5.88 66.24 9.08 ;
+        RECT 0 46.68 3.2 49.88 ;
+        RECT 63.04 46.68 66.24 49.88 ;
+    END
+  END VDD
+  PIN VSS
+    DIRECTION INPUT ;
+    USE GROUND ;
+    PORT
+      LAYER met1 ;
+        RECT 0 0 45.4 0.24 ;
+        RECT 46.6 0 66.24 0.24 ;
+        RECT 0 5.2 0.48 5.68 ;
+        RECT 65.76 5.2 66.24 5.68 ;
+        RECT 0 10.64 0.48 11.12 ;
+        RECT 65.76 10.64 66.24 11.12 ;
+        RECT 0 16.08 0.48 16.56 ;
+        RECT 65.76 16.08 66.24 16.56 ;
+        RECT 0 21.52 0.48 22 ;
+        RECT 65.76 21.52 66.24 22 ;
+        RECT 0 26.96 0.48 27.44 ;
+        RECT 65.76 26.96 66.24 27.44 ;
+        RECT 0 32.4 0.48 32.88 ;
+        RECT 65.76 32.4 66.24 32.88 ;
+        RECT 0 37.84 0.48 38.32 ;
+        RECT 65.76 37.84 66.24 38.32 ;
+        RECT 0 43.28 0.48 43.76 ;
+        RECT 65.76 43.28 66.24 43.76 ;
+        RECT 0 48.72 0.48 49.2 ;
+        RECT 65.76 48.72 66.24 49.2 ;
+        RECT 0 54.16 0.48 54.64 ;
+        RECT 65.76 54.16 66.24 54.64 ;
+        RECT 0 59.6 0.48 60.08 ;
+        RECT 65.76 59.6 66.24 60.08 ;
+        RECT 0 65.04 0.48 65.52 ;
+        RECT 65.76 65.04 66.24 65.52 ;
+        RECT 0 70.48 0.48 70.96 ;
+        RECT 65.76 70.48 66.24 70.96 ;
+        RECT 0 75.92 45.4 76.16 ;
+        RECT 46.6 75.92 66.24 76.16 ;
+      LAYER met4 ;
+        RECT 25.46 0 26.06 0.6 ;
+        RECT 54.9 0 55.5 0.6 ;
+        RECT 25.46 75.56 26.06 76.16 ;
+        RECT 54.9 75.56 55.5 76.16 ;
+      LAYER met5 ;
+        RECT 0 26.28 3.2 29.48 ;
+        RECT 63.04 26.28 66.24 29.48 ;
+        RECT 0 67.08 3.2 70.28 ;
+        RECT 63.04 67.08 66.24 70.28 ;
+    END
+  END VSS
+  OBS
+    LAYER met2 ;
+      RECT 55.06 75.975 55.34 76.345 ;
+      RECT 25.62 75.975 25.9 76.345 ;
+      RECT 55.06 -0.185 55.34 0.185 ;
+      RECT 25.62 -0.185 25.9 0.185 ;
+      POLYGON 65.96 75.88 65.96 0.28 53.94 0.28 53.94 0.765 53.24 0.765 53.24 0.28 53.02 0.28 53.02 0.765 52.32 0.765 52.32 0.28 52.1 0.28 52.1 0.765 51.4 0.765 51.4 0.28 51.18 0.28 51.18 0.765 50.48 0.765 50.48 0.28 50.26 0.28 50.26 0.765 49.56 0.765 49.56 0.28 49.34 0.28 49.34 0.765 48.64 0.765 48.64 0.28 48.42 0.28 48.42 0.765 47.72 0.765 47.72 0.28 47.5 0.28 47.5 0.765 46.8 0.765 46.8 0.28 46.58 0.28 46.58 0.765 45.88 0.765 45.88 0.28 45.66 0.28 45.66 0.765 44.96 0.765 44.96 0.28 44.74 0.28 44.74 0.765 44.04 0.765 44.04 0.28 43.82 0.28 43.82 0.765 43.12 0.765 43.12 0.28 42.44 0.28 42.44 0.765 41.74 0.765 41.74 0.28 41.52 0.28 41.52 0.765 40.82 0.765 40.82 0.28 40.6 0.28 40.6 0.765 39.9 0.765 39.9 0.28 39.68 0.28 39.68 0.765 38.98 0.765 38.98 0.28 38.76 0.28 38.76 0.765 38.06 0.765 38.06 0.28 37.84 0.28 37.84 0.765 37.14 0.765 37.14 0.28 36.92 0.28 36.92 0.765 36.22 0.765 36.22 0.28 36 0.28 36 0.765 35.3 0.765 35.3 0.28 34.62 0.28 34.62 0.765 33.92 0.765 33.92 0.28 33.7 0.28 33.7 0.765 33 0.765 33 0.28 32.78 0.28 32.78 0.765 32.08 0.765 32.08 0.28 31.4 0.28 31.4 0.765 30.7 0.765 30.7 0.28 30.48 0.28 30.48 0.765 29.78 0.765 29.78 0.28 29.56 0.28 29.56 0.765 28.86 0.765 28.86 0.28 28.64 0.28 28.64 0.765 27.94 0.765 27.94 0.28 27.72 0.28 27.72 0.765 27.02 0.765 27.02 0.28 26.8 0.28 26.8 0.765 26.1 0.765 26.1 0.28 25.42 0.28 25.42 0.765 24.72 0.765 24.72 0.28 24.5 0.28 24.5 0.765 23.8 0.765 23.8 0.28 23.12 0.28 23.12 0.765 22.42 0.765 22.42 0.28 22.2 0.28 22.2 0.765 21.5 0.765 21.5 0.28 21.28 0.28 21.28 0.765 20.58 0.765 20.58 0.28 20.36 0.28 20.36 0.765 19.66 0.765 19.66 0.28 19.44 0.28 19.44 0.765 18.74 0.765 18.74 0.28 18.52 0.28 18.52 0.765 17.82 0.765 17.82 0.28 13 0.28 13 0.765 12.3 0.765 12.3 0.28 12.08 0.28 12.08 0.765 11.38 0.765 11.38 0.28 7.94 0.28 7.94 0.765 7.24 0.765 7.24 0.28 7.02 0.28 7.02 0.765 6.32 0.765 6.32 0.28 6.1 0.28 6.1 0.765 5.4 0.765 5.4 0.28 5.18 0.28 5.18 0.765 4.48 0.765 4.48 0.28 0.28 0.28 0.28 75.88 5.4 75.88 5.4 75.395 6.1 75.395 6.1 75.88 6.32 75.88 6.32 75.395 7.02 75.395 7.02 75.88 7.7 75.88 7.7 75.395 8.4 75.395 8.4 75.88 9.08 75.88 9.08 75.395 9.78 75.395 9.78 75.88 12.3 75.88 12.3 75.395 13 75.395 13 75.88 13.22 75.88 13.22 75.395 13.92 75.395 13.92 75.88 21.04 75.88 21.04 75.395 21.74 75.395 21.74 75.88 21.96 75.88 21.96 75.395 22.66 75.395 22.66 75.88 23.34 75.88 23.34 75.395 24.04 75.395 24.04 75.88 24.26 75.88 24.26 75.395 24.96 75.395 24.96 75.88 26.1 75.88 26.1 75.395 26.8 75.395 26.8 75.88 27.02 75.88 27.02 75.395 27.72 75.395 27.72 75.88 28.4 75.88 28.4 75.395 29.1 75.395 29.1 75.88 29.32 75.88 29.32 75.395 30.02 75.395 30.02 75.88 30.24 75.88 30.24 75.395 30.94 75.395 30.94 75.88 31.16 75.88 31.16 75.395 31.86 75.395 31.86 75.88 32.08 75.88 32.08 75.395 32.78 75.395 32.78 75.88 33 75.88 33 75.395 33.7 75.395 33.7 75.88 33.92 75.88 33.92 75.395 34.62 75.395 34.62 75.88 35.3 75.88 35.3 75.395 36 75.395 36 75.88 36.22 75.88 36.22 75.395 36.92 75.395 36.92 75.88 37.6 75.88 37.6 75.395 38.3 75.395 38.3 75.88 38.52 75.88 38.52 75.395 39.22 75.395 39.22 75.88 39.44 75.88 39.44 75.395 40.14 75.395 40.14 75.88 40.36 75.88 40.36 75.395 41.06 75.395 41.06 75.88 41.28 75.88 41.28 75.395 41.98 75.395 41.98 75.88 42.2 75.88 42.2 75.395 42.9 75.395 42.9 75.88 43.12 75.88 43.12 75.395 43.82 75.395 43.82 75.88 44.04 75.88 44.04 75.395 44.74 75.395 44.74 75.88 44.96 75.88 44.96 75.395 45.66 75.395 45.66 75.88 45.88 75.88 45.88 75.395 46.58 75.395 46.58 75.88 46.8 75.88 46.8 75.395 47.5 75.395 47.5 75.88 47.72 75.88 47.72 75.395 48.42 75.395 48.42 75.88 48.64 75.88 48.64 75.395 49.34 75.395 49.34 75.88 49.56 75.88 49.56 75.395 50.26 75.395 50.26 75.88 50.48 75.88 50.48 75.395 51.18 75.395 51.18 75.88 51.4 75.88 51.4 75.395 52.1 75.395 52.1 75.88 52.32 75.88 52.32 75.395 53.02 75.395 53.02 75.88 53.24 75.88 53.24 75.395 53.94 75.395 53.94 75.88 54.16 75.88 54.16 75.395 54.86 75.395 54.86 75.88 55.54 75.88 55.54 75.395 56.24 75.395 56.24 75.88 56.46 75.88 56.46 75.395 57.16 75.395 57.16 75.88 ;
+    LAYER met3 ;
+      POLYGON 55.365 76.325 55.365 76.32 55.58 76.32 55.58 76 55.365 76 55.365 75.995 55.035 75.995 55.035 76 54.82 76 54.82 76.32 55.035 76.32 55.035 76.325 ;
+      POLYGON 25.925 76.325 25.925 76.32 26.14 76.32 26.14 76 25.925 76 25.925 75.995 25.595 75.995 25.595 76 25.38 76 25.38 76.32 25.595 76.32 25.595 76.325 ;
+      POLYGON 7.74 12.73 7.74 12.43 0.65 12.43 0.65 12.71 1.2 12.71 1.2 12.73 ;
+      POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ;
+      POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ;
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+      RECT 25.685 -0.075 25.835 0.075 ;
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+      RECT 1.05 45.8 1.25 46 ;
+      RECT 64.99 6.36 65.19 6.56 ;
+      RECT 55.1 -0.1 55.3 0.1 ;
+      RECT 25.66 -0.1 25.86 0.1 ;
+    LAYER via3 ;
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+      RECT 25.66 76.06 25.86 76.26 ;
+      RECT 55.1 -0.1 55.3 0.1 ;
+      RECT 25.66 -0.1 25.86 0.1 ;
+    LAYER OVERLAP ;
+      POLYGON 0 0 0 76.16 66.24 76.16 66.24 0 ;
+  END
+END cby_2__1_
+
+END LIBRARY
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef
new file mode 100644
index 0000000..cc01410
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef
@@ -0,0 +1,1347 @@
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+
+UNITS
+  DATABASE MICRONS 1000 ;
+END UNITS
+
+MANUFACTURINGGRID 0.005 ;
+
+LAYER li1
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.17 ;
+END li1
+
+LAYER mcon
+  TYPE CUT ;
+END mcon
+
+LAYER met1
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.34 ;
+  WIDTH 0.14 ;
+END met1
+
+LAYER via
+  TYPE CUT ;
+END via
+
+LAYER met2
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.14 ;
+END met2
+
+LAYER via2
+  TYPE CUT ;
+END via2
+
+LAYER met3
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.68 ;
+  WIDTH 0.3 ;
+END met3
+
+LAYER via3
+  TYPE CUT ;
+END via3
+
+LAYER met4
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.92 ;
+  WIDTH 0.3 ;
+END met4
+
+LAYER via4
+  TYPE CUT ;
+END via4
+
+LAYER met5
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 3.4 ;
+  WIDTH 1.6 ;
+END met5
+
+LAYER nwell
+  TYPE MASTERSLICE ;
+END nwell
+
+LAYER pwell
+  TYPE MASTERSLICE ;
+END pwell
+
+LAYER OVERLAP
+  TYPE OVERLAP ;
+END OVERLAP
+
+VIA L1M1_PR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
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+END L1M1_PR
+
+VIA L1M1_PR_R
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
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+END L1M1_PR_R
+
+VIA L1M1_PR_M
+  LAYER li1 ;
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+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
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+END L1M1_PR_M
+
+VIA L1M1_PR_MR
+  LAYER li1 ;
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+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
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+END L1M1_PR_MR
+
+VIA L1M1_PR_C
+  LAYER li1 ;
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+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
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+END L1M1_PR_C
+
+VIA M1M2_PR
+  LAYER met1 ;
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+  LAYER via ;
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+END M1M2_PR
+
+VIA M1M2_PR_Enc
+  LAYER met1 ;
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+  LAYER via ;
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+END M1M2_PR_Enc
+
+VIA M1M2_PR_R
+  LAYER met1 ;
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+END M1M2_PR_R
+
+VIA M1M2_PR_R_Enc
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+END M1M2_PR_R_Enc
+
+VIA M1M2_PR_M
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+END M1M2_PR_M
+
+VIA M1M2_PR_M_Enc
+  LAYER met1 ;
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+END M1M2_PR_M_Enc
+
+VIA M1M2_PR_MR
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+END M1M2_PR_MR
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+VIA M1M2_PR_MR_Enc
+  LAYER met1 ;
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+END M1M2_PR_MR_Enc
+
+VIA M1M2_PR_C
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+END M1M2_PR_C
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+VIA M2M3_PR
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+END M2M3_PR
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+VIA M2M3_PR_R
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+END M2M3_PR_R
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+VIA M2M3_PR_M
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+END M2M3_PR_M
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+VIA M2M3_PR_MR
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+VIA M3M4_PR_R
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+VIA M4M5_PR_R
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+END M4M5_PR_R
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+VIA M4M5_PR_M
+  LAYER met4 ;
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+END M4M5_PR_M
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+VIA M4M5_PR_MR
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+  LAYER via4 ;
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+END M4M5_PR_MR
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+VIA M4M5_PR_C
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+END M4M5_PR_C
+
+SITE unit
+  CLASS CORE ;
+  SYMMETRY Y ;
+  SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+  CLASS CORE ;
+  SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+MACRO sb_0__0_
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 92 BY 97.92 ;
+  SYMMETRY X Y ;
+  PIN chany_top_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 48 97.435 48.14 97.92 ;
+    END
+  END chany_top_in[0]
+  PIN chany_top_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 54.44 97.435 54.58 97.92 ;
+    END
+  END chany_top_in[1]
+  PIN chany_top_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 47.08 97.435 47.22 97.92 ;
+    END
+  END chany_top_in[2]
+  PIN chany_top_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 60.88 97.435 61.02 97.92 ;
+    END
+  END chany_top_in[3]
+  PIN chany_top_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 50.76 97.435 50.9 97.92 ;
+    END
+  END chany_top_in[4]
+  PIN chany_top_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 42.02 97.435 42.16 97.92 ;
+    END
+  END chany_top_in[5]
+  PIN chany_top_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 31.9 97.435 32.04 97.92 ;
+    END
+  END chany_top_in[6]
+  PIN chany_top_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 42.94 97.435 43.08 97.92 ;
+    END
+  END chany_top_in[7]
+  PIN chany_top_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.04 97.435 13.18 97.92 ;
+    END
+  END chany_top_in[8]
+  PIN chany_top_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 18.56 97.435 18.7 97.92 ;
+    END
+  END chany_top_in[9]
+  PIN chany_top_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 49.84 97.435 49.98 97.92 ;
+    END
+  END chany_top_in[10]
+  PIN chany_top_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.6 97.435 52.74 97.92 ;
+    END
+  END chany_top_in[11]
+  PIN chany_top_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.04 97.435 59.18 97.92 ;
+    END
+  END chany_top_in[12]
+  PIN chany_top_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 41.1 97.435 41.24 97.92 ;
+    END
+  END chany_top_in[13]
+  PIN chany_top_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 32.82 97.435 32.96 97.92 ;
+    END
+  END chany_top_in[14]
+  PIN chany_top_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 17.64 97.435 17.78 97.92 ;
+    END
+  END chany_top_in[15]
+  PIN chany_top_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 25 97.435 25.14 97.92 ;
+    END
+  END chany_top_in[16]
+  PIN chany_top_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 30.98 97.435 31.12 97.92 ;
+    END
+  END chany_top_in[17]
+  PIN chany_top_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.64 97.435 63.78 97.92 ;
+    END
+  END chany_top_in[18]
+  PIN chany_top_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 48.92 97.435 49.06 97.92 ;
+    END
+  END chany_top_in[19]
+  PIN top_left_grid_pin_1_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 26.38 97.435 26.52 97.92 ;
+    END
+  END top_left_grid_pin_1_[0]
+  PIN chanx_right_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 66.83 92 67.13 ;
+    END
+  END chanx_right_in[0]
+  PIN chanx_right_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 77.71 92 78.01 ;
+    END
+  END chanx_right_in[1]
+  PIN chanx_right_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 75.67 92 75.97 ;
+    END
+  END chanx_right_in[2]
+  PIN chanx_right_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 59.35 92 59.65 ;
+    END
+  END chanx_right_in[3]
+  PIN chanx_right_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 57.99 92 58.29 ;
+    END
+  END chanx_right_in[4]
+  PIN chanx_right_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 79.07 92 79.37 ;
+    END
+  END chanx_right_in[5]
+  PIN chanx_right_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 48.47 92 48.77 ;
+    END
+  END chanx_right_in[6]
+  PIN chanx_right_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 60.71 92 61.01 ;
+    END
+  END chanx_right_in[7]
+  PIN chanx_right_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 25.35 92 25.65 ;
+    END
+  END chanx_right_in[8]
+  PIN chanx_right_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 22.63 92 22.93 ;
+    END
+  END chanx_right_in[9]
+  PIN chanx_right_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 43.03 92 43.33 ;
+    END
+  END chanx_right_in[10]
+  PIN chanx_right_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 39.63 92 39.93 ;
+    END
+  END chanx_right_in[11]
+  PIN chanx_right_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 29.43 92 29.73 ;
+    END
+  END chanx_right_in[12]
+  PIN chanx_right_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 44.39 92 44.69 ;
+    END
+  END chanx_right_in[13]
+  PIN chanx_right_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 26.71 92 27.01 ;
+    END
+  END chanx_right_in[14]
+  PIN chanx_right_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 49.83 92 50.13 ;
+    END
+  END chanx_right_in[15]
+  PIN chanx_right_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 28.07 92 28.37 ;
+    END
+  END chanx_right_in[16]
+  PIN chanx_right_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 13.11 92 13.41 ;
+    END
+  END chanx_right_in[17]
+  PIN chanx_right_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 41.67 92 41.97 ;
+    END
+  END chanx_right_in[18]
+  PIN chanx_right_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 82.5 86.555 82.64 87.04 ;
+    END
+  END chanx_right_in[19]
+  PIN right_bottom_grid_pin_1_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 53.91 92 54.21 ;
+    END
+  END right_bottom_grid_pin_1_[0]
+  PIN right_bottom_grid_pin_3_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 72.95 92 73.25 ;
+    END
+  END right_bottom_grid_pin_3_[0]
+  PIN right_bottom_grid_pin_5_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 70.91 92 71.21 ;
+    END
+  END right_bottom_grid_pin_5_[0]
+  PIN right_bottom_grid_pin_7_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 32.83 92 33.13 ;
+    END
+  END right_bottom_grid_pin_7_[0]
+  PIN right_bottom_grid_pin_9_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 18.55 92 18.85 ;
+    END
+  END right_bottom_grid_pin_9_[0]
+  PIN right_bottom_grid_pin_11_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 56.63 92 56.93 ;
+    END
+  END right_bottom_grid_pin_11_[0]
+  PIN right_bottom_grid_pin_13_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 19.91 92 20.21 ;
+    END
+  END right_bottom_grid_pin_13_[0]
+  PIN right_bottom_grid_pin_15_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 17.19 92 17.49 ;
+    END
+  END right_bottom_grid_pin_15_[0]
+  PIN right_bottom_grid_pin_17_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 21.27 92 21.57 ;
+    END
+  END right_bottom_grid_pin_17_[0]
+  PIN ccff_head[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 51.19 92 51.49 ;
+    END
+  END ccff_head[0]
+  PIN chany_top_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 62.72 97.435 62.86 97.92 ;
+    END
+  END chany_top_out[0]
+  PIN chany_top_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 40.18 97.435 40.32 97.92 ;
+    END
+  END chany_top_out[1]
+  PIN chany_top_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 51.68 97.435 51.82 97.92 ;
+    END
+  END chany_top_out[2]
+  PIN chany_top_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 56.28 97.435 56.42 97.92 ;
+    END
+  END chany_top_out[3]
+  PIN chany_top_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.52 97.435 53.66 97.92 ;
+    END
+  END chany_top_out[4]
+  PIN chany_top_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 34.66 97.435 34.8 97.92 ;
+    END
+  END chany_top_out[5]
+  PIN chany_top_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.96 97.435 14.1 97.92 ;
+    END
+  END chany_top_out[6]
+  PIN chany_top_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 16.72 97.435 16.86 97.92 ;
+    END
+  END chany_top_out[7]
+  PIN chany_top_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 39.26 97.435 39.4 97.92 ;
+    END
+  END chany_top_out[8]
+  PIN chany_top_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 35.58 97.435 35.72 97.92 ;
+    END
+  END chany_top_out[9]
+  PIN chany_top_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.8 97.435 61.94 97.92 ;
+    END
+  END chany_top_out[10]
+  PIN chany_top_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.12 97.435 58.26 97.92 ;
+    END
+  END chany_top_out[11]
+  PIN chany_top_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 33.74 97.435 33.88 97.92 ;
+    END
+  END chany_top_out[12]
+  PIN chany_top_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 38.34 97.435 38.48 97.92 ;
+    END
+  END chany_top_out[13]
+  PIN chany_top_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 14.88 97.435 15.02 97.92 ;
+    END
+  END chany_top_out[14]
+  PIN chany_top_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 36.5 97.435 36.64 97.92 ;
+    END
+  END chany_top_out[15]
+  PIN chany_top_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.96 97.435 60.1 97.92 ;
+    END
+  END chany_top_out[16]
+  PIN chany_top_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 15.8 97.435 15.94 97.92 ;
+    END
+  END chany_top_out[17]
+  PIN chany_top_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 37.42 97.435 37.56 97.92 ;
+    END
+  END chany_top_out[18]
+  PIN chany_top_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 57.2 97.435 57.34 97.92 ;
+    END
+  END chany_top_out[19]
+  PIN chanx_right_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 69.55 92 69.85 ;
+    END
+  END chanx_right_out[0]
+  PIN chanx_right_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 52.55 92 52.85 ;
+    END
+  END chanx_right_out[1]
+  PIN chanx_right_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 47.11 92 47.41 ;
+    END
+  END chanx_right_out[2]
+  PIN chanx_right_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 65.47 92 65.77 ;
+    END
+  END chanx_right_out[3]
+  PIN chanx_right_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 36.91 92 37.21 ;
+    END
+  END chanx_right_out[4]
+  PIN chanx_right_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 15.83 92 16.13 ;
+    END
+  END chanx_right_out[5]
+  PIN chanx_right_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 68.19 92 68.49 ;
+    END
+  END chanx_right_out[6]
+  PIN chanx_right_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 62.07 92 62.37 ;
+    END
+  END chanx_right_out[7]
+  PIN chanx_right_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 55.27 92 55.57 ;
+    END
+  END chanx_right_out[8]
+  PIN chanx_right_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 74.31 92 74.61 ;
+    END
+  END chanx_right_out[9]
+  PIN chanx_right_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 31.47 92 31.77 ;
+    END
+  END chanx_right_out[10]
+  PIN chanx_right_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 23.99 92 24.29 ;
+    END
+  END chanx_right_out[11]
+  PIN chanx_right_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 64.11 92 64.41 ;
+    END
+  END chanx_right_out[12]
+  PIN chanx_right_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 81.79 92 82.09 ;
+    END
+  END chanx_right_out[13]
+  PIN chanx_right_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 80.43 92 80.73 ;
+    END
+  END chanx_right_out[14]
+  PIN chanx_right_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 83.15 92 83.45 ;
+    END
+  END chanx_right_out[15]
+  PIN chanx_right_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 35.55 92 35.85 ;
+    END
+  END chanx_right_out[16]
+  PIN chanx_right_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 45.75 92 46.05 ;
+    END
+  END chanx_right_out[17]
+  PIN chanx_right_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 38.27 92 38.57 ;
+    END
+  END chanx_right_out[18]
+  PIN chanx_right_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 34.19 92 34.49 ;
+    END
+  END chanx_right_out[19]
+  PIN ccff_tail[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 65.94 0 66.08 0.485 ;
+    END
+  END ccff_tail[0]
+  PIN prog_clk_0_E_in
+    DIRECTION INPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 7.67 92 7.97 ;
+    END
+  END prog_clk_0_E_in
+  PIN VDD
+    DIRECTION INPUT ;
+    USE POWER ;
+    PORT
+      LAYER met5 ;
+        RECT 0 11.32 3.2 14.52 ;
+        RECT 88.8 11.32 92 14.52 ;
+        RECT 0 52.12 3.2 55.32 ;
+        RECT 88.8 52.12 92 55.32 ;
+      LAYER met4 ;
+        RECT 10.74 0 11.34 0.6 ;
+        RECT 40.18 0 40.78 0.6 ;
+        RECT 80.66 0 81.26 0.6 ;
+        RECT 80.66 86.44 81.26 87.04 ;
+        RECT 10.74 97.32 11.34 97.92 ;
+        RECT 40.18 97.32 40.78 97.92 ;
+      LAYER met1 ;
+        RECT 0 2.48 0.48 2.96 ;
+        RECT 91.52 2.48 92 2.96 ;
+        RECT 0 7.92 0.48 8.4 ;
+        RECT 91.52 7.92 92 8.4 ;
+        RECT 0 13.36 0.48 13.84 ;
+        RECT 91.52 13.36 92 13.84 ;
+        RECT 0 18.8 0.48 19.28 ;
+        RECT 91.52 18.8 92 19.28 ;
+        RECT 0 24.24 0.48 24.72 ;
+        RECT 91.52 24.24 92 24.72 ;
+        RECT 0 29.68 0.48 30.16 ;
+        RECT 91.52 29.68 92 30.16 ;
+        RECT 0 35.12 0.48 35.6 ;
+        RECT 91.52 35.12 92 35.6 ;
+        RECT 0 40.56 0.48 41.04 ;
+        RECT 91.52 40.56 92 41.04 ;
+        RECT 0 46 0.48 46.48 ;
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+      RECT 25.66 97.82 25.86 98.02 ;
+      RECT 55.1 -0.1 55.3 0.1 ;
+      RECT 25.66 -0.1 25.86 0.1 ;
+    LAYER OVERLAP ;
+      POLYGON 0 0 0 97.92 66.24 97.92 66.24 87.04 92 87.04 92 0 ;
+  END
+END sb_0__0_
+
+END LIBRARY
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef
new file mode 100644
index 0000000..9474689
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef
@@ -0,0 +1,1680 @@
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+
+UNITS
+  DATABASE MICRONS 1000 ;
+END UNITS
+
+MANUFACTURINGGRID 0.005 ;
+
+LAYER li1
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.17 ;
+END li1
+
+LAYER mcon
+  TYPE CUT ;
+END mcon
+
+LAYER met1
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.34 ;
+  WIDTH 0.14 ;
+END met1
+
+LAYER via
+  TYPE CUT ;
+END via
+
+LAYER met2
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.14 ;
+END met2
+
+LAYER via2
+  TYPE CUT ;
+END via2
+
+LAYER met3
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.68 ;
+  WIDTH 0.3 ;
+END met3
+
+LAYER via3
+  TYPE CUT ;
+END via3
+
+LAYER met4
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.92 ;
+  WIDTH 0.3 ;
+END met4
+
+LAYER via4
+  TYPE CUT ;
+END via4
+
+LAYER met5
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 3.4 ;
+  WIDTH 1.6 ;
+END met5
+
+LAYER nwell
+  TYPE MASTERSLICE ;
+END nwell
+
+LAYER pwell
+  TYPE MASTERSLICE ;
+END pwell
+
+LAYER OVERLAP
+  TYPE OVERLAP ;
+END OVERLAP
+
+VIA L1M1_PR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR
+
+VIA L1M1_PR_R
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_R
+
+VIA L1M1_PR_M
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_M
+
+VIA L1M1_PR_MR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR_MR
+
+VIA L1M1_PR_C
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.145 0.145 0.145 ;
+END L1M1_PR_C
+
+VIA M1M2_PR
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR
+
+VIA M1M2_PR_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_Enc
+
+VIA M1M2_PR_R
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_R
+
+VIA M1M2_PR_R_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_R_Enc
+
+VIA M1M2_PR_M
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIA M1M2_PR_M_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_M_Enc
+
+VIA M1M2_PR_MR
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIA M1M2_PR_MR_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_MR_Enc
+
+VIA M1M2_PR_C
+  LAYER met1 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIA M2M3_PR
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIA M2M3_PR_R
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIA M2M3_PR_M
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIA M2M3_PR_MR
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIA M2M3_PR_C
+  LAYER met2 ;
+    RECT -0.185 -0.185 0.185 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIA M3M4_PR
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIA M3M4_PR_R
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIA M3M4_PR_M
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIA M3M4_PR_MR
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIA M3M4_PR_C
+  LAYER met3 ;
+    RECT -0.19 -0.19 0.19 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIA M4M5_PR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIA M4M5_PR_R
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIA M4M5_PR_M
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIA M4M5_PR_MR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIA M4M5_PR_C
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+  CLASS CORE ;
+  SYMMETRY Y ;
+  SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+  CLASS CORE ;
+  SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+MACRO sb_0__1_
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 92 BY 108.8 ;
+  SYMMETRY X Y ;
+  PIN chany_top_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 48 108.315 48.14 108.8 ;
+    END
+  END chany_top_in[0]
+  PIN chany_top_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 54.44 108.315 54.58 108.8 ;
+    END
+  END chany_top_in[1]
+  PIN chany_top_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 47.08 108.315 47.22 108.8 ;
+    END
+  END chany_top_in[2]
+  PIN chany_top_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 60.88 108.315 61.02 108.8 ;
+    END
+  END chany_top_in[3]
+  PIN chany_top_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 50.76 108.315 50.9 108.8 ;
+    END
+  END chany_top_in[4]
+  PIN chany_top_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 42.02 108.315 42.16 108.8 ;
+    END
+  END chany_top_in[5]
+  PIN chany_top_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 31.9 108.315 32.04 108.8 ;
+    END
+  END chany_top_in[6]
+  PIN chany_top_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 42.94 108.315 43.08 108.8 ;
+    END
+  END chany_top_in[7]
+  PIN chany_top_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.04 108.315 13.18 108.8 ;
+    END
+  END chany_top_in[8]
+  PIN chany_top_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 18.56 108.315 18.7 108.8 ;
+    END
+  END chany_top_in[9]
+  PIN chany_top_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 49.84 108.315 49.98 108.8 ;
+    END
+  END chany_top_in[10]
+  PIN chany_top_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.6 108.315 52.74 108.8 ;
+    END
+  END chany_top_in[11]
+  PIN chany_top_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.04 108.315 59.18 108.8 ;
+    END
+  END chany_top_in[12]
+  PIN chany_top_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 41.1 108.315 41.24 108.8 ;
+    END
+  END chany_top_in[13]
+  PIN chany_top_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 32.82 108.315 32.96 108.8 ;
+    END
+  END chany_top_in[14]
+  PIN chany_top_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 17.64 108.315 17.78 108.8 ;
+    END
+  END chany_top_in[15]
+  PIN chany_top_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 25 108.315 25.14 108.8 ;
+    END
+  END chany_top_in[16]
+  PIN chany_top_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 30.98 108.315 31.12 108.8 ;
+    END
+  END chany_top_in[17]
+  PIN chany_top_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.64 108.315 63.78 108.8 ;
+    END
+  END chany_top_in[18]
+  PIN chany_top_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 48.92 108.315 49.06 108.8 ;
+    END
+  END chany_top_in[19]
+  PIN top_left_grid_pin_1_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 26.38 108.315 26.52 108.8 ;
+    END
+  END top_left_grid_pin_1_[0]
+  PIN chanx_right_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 66.15 92 66.45 ;
+    END
+  END chanx_right_in[0]
+  PIN chanx_right_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 87.91 92 88.21 ;
+    END
+  END chanx_right_in[1]
+  PIN chanx_right_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 36.23 92 36.53 ;
+    END
+  END chanx_right_in[2]
+  PIN chanx_right_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 48.47 92 48.77 ;
+    END
+  END chanx_right_in[3]
+  PIN chanx_right_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 71.59 92 71.89 ;
+    END
+  END chanx_right_in[4]
+  PIN chanx_right_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 86.55 92 86.85 ;
+    END
+  END chanx_right_in[5]
+  PIN chanx_right_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 62.07 92 62.37 ;
+    END
+  END chanx_right_in[6]
+  PIN chanx_right_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 22.63 92 22.93 ;
+    END
+  END chanx_right_in[7]
+  PIN chanx_right_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 34.87 92 35.17 ;
+    END
+  END chanx_right_in[8]
+  PIN chanx_right_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 41.67 92 41.97 ;
+    END
+  END chanx_right_in[9]
+  PIN chanx_right_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 64.79 92 65.09 ;
+    END
+  END chanx_right_in[10]
+  PIN chanx_right_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 51.19 92 51.49 ;
+    END
+  END chanx_right_in[11]
+  PIN chanx_right_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 23.99 92 24.29 ;
+    END
+  END chanx_right_in[12]
+  PIN chanx_right_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 44.39 92 44.69 ;
+    END
+  END chanx_right_in[13]
+  PIN chanx_right_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 60.71 92 61.01 ;
+    END
+  END chanx_right_in[14]
+  PIN chanx_right_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 57.99 92 58.29 ;
+    END
+  END chanx_right_in[15]
+  PIN chanx_right_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 67.51 92 67.81 ;
+    END
+  END chanx_right_in[16]
+  PIN chanx_right_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 45.75 92 46.05 ;
+    END
+  END chanx_right_in[17]
+  PIN chanx_right_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 63.43 92 63.73 ;
+    END
+  END chanx_right_in[18]
+  PIN chanx_right_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 43.03 92 43.33 ;
+    END
+  END chanx_right_in[19]
+  PIN right_bottom_grid_pin_34_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 79.28 10.88 79.42 11.365 ;
+    END
+  END right_bottom_grid_pin_34_[0]
+  PIN right_bottom_grid_pin_35_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 85.72 10.88 85.86 11.365 ;
+    END
+  END right_bottom_grid_pin_35_[0]
+  PIN right_bottom_grid_pin_36_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 82.04 10.88 82.18 11.365 ;
+    END
+  END right_bottom_grid_pin_36_[0]
+  PIN right_bottom_grid_pin_37_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 87.1 10.88 87.24 11.365 ;
+    END
+  END right_bottom_grid_pin_37_[0]
+  PIN right_bottom_grid_pin_38_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 81.12 10.88 81.26 11.365 ;
+    END
+  END right_bottom_grid_pin_38_[0]
+  PIN right_bottom_grid_pin_39_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 78.36 10.88 78.5 11.365 ;
+    END
+  END right_bottom_grid_pin_39_[0]
+  PIN right_bottom_grid_pin_40_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 80.2 10.88 80.34 11.365 ;
+    END
+  END right_bottom_grid_pin_40_[0]
+  PIN right_bottom_grid_pin_41_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 82.96 10.88 83.1 11.365 ;
+    END
+  END right_bottom_grid_pin_41_[0]
+  PIN chany_bottom_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 49.84 0 49.98 0.485 ;
+    END
+  END chany_bottom_in[0]
+  PIN chany_bottom_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.96 0 60.1 0.485 ;
+    END
+  END chany_bottom_in[1]
+  PIN chany_bottom_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 60.88 0 61.02 0.485 ;
+    END
+  END chany_bottom_in[2]
+  PIN chany_bottom_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.64 0 63.78 0.485 ;
+    END
+  END chany_bottom_in[3]
+  PIN chany_bottom_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.6 0 52.74 0.485 ;
+    END
+  END chany_bottom_in[4]
+  PIN chany_bottom_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 39.26 0 39.4 0.485 ;
+    END
+  END chany_bottom_in[5]
+  PIN chany_bottom_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 35.58 0 35.72 0.485 ;
+    END
+  END chany_bottom_in[6]
+  PIN chany_bottom_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 62.72 0 62.86 0.485 ;
+    END
+  END chany_bottom_in[7]
+  PIN chany_bottom_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 9.36 0 9.5 0.485 ;
+    END
+  END chany_bottom_in[8]
+  PIN chany_bottom_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 8.44 0 8.58 0.485 ;
+    END
+  END chany_bottom_in[9]
+  PIN chany_bottom_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 26.38 0 26.52 0.485 ;
+    END
+  END chany_bottom_in[10]
+  PIN chany_bottom_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 51.68 0 51.82 0.485 ;
+    END
+  END chany_bottom_in[11]
+  PIN chany_bottom_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.52 0 53.66 0.485 ;
+    END
+  END chany_bottom_in[12]
+  PIN chany_bottom_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 56.28 0 56.42 0.485 ;
+    END
+  END chany_bottom_in[13]
+  PIN chany_bottom_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.12 0 58.26 0.485 ;
+    END
+  END chany_bottom_in[14]
+  PIN chany_bottom_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 38.34 0 38.48 0.485 ;
+    END
+  END chany_bottom_in[15]
+  PIN chany_bottom_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.8 0 61.94 0.485 ;
+    END
+  END chany_bottom_in[16]
+  PIN chany_bottom_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 32.82 0 32.96 0.485 ;
+    END
+  END chany_bottom_in[17]
+  PIN chany_bottom_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 21.32 0 21.46 0.485 ;
+    END
+  END chany_bottom_in[18]
+  PIN chany_bottom_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 40.18 0 40.32 0.485 ;
+    END
+  END chany_bottom_in[19]
+  PIN bottom_left_grid_pin_1_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 20.4 0 20.54 0.485 ;
+    END
+  END bottom_left_grid_pin_1_[0]
+  PIN ccff_head[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 29.43 92 29.73 ;
+    END
+  END ccff_head[0]
+  PIN chany_top_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 62.72 108.315 62.86 108.8 ;
+    END
+  END chany_top_out[0]
+  PIN chany_top_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 40.18 108.315 40.32 108.8 ;
+    END
+  END chany_top_out[1]
+  PIN chany_top_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 51.68 108.315 51.82 108.8 ;
+    END
+  END chany_top_out[2]
+  PIN chany_top_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 56.28 108.315 56.42 108.8 ;
+    END
+  END chany_top_out[3]
+  PIN chany_top_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.52 108.315 53.66 108.8 ;
+    END
+  END chany_top_out[4]
+  PIN chany_top_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 34.66 108.315 34.8 108.8 ;
+    END
+  END chany_top_out[5]
+  PIN chany_top_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.96 108.315 14.1 108.8 ;
+    END
+  END chany_top_out[6]
+  PIN chany_top_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 16.72 108.315 16.86 108.8 ;
+    END
+  END chany_top_out[7]
+  PIN chany_top_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 39.26 108.315 39.4 108.8 ;
+    END
+  END chany_top_out[8]
+  PIN chany_top_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 35.58 108.315 35.72 108.8 ;
+    END
+  END chany_top_out[9]
+  PIN chany_top_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.8 108.315 61.94 108.8 ;
+    END
+  END chany_top_out[10]
+  PIN chany_top_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.12 108.315 58.26 108.8 ;
+    END
+  END chany_top_out[11]
+  PIN chany_top_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 33.74 108.315 33.88 108.8 ;
+    END
+  END chany_top_out[12]
+  PIN chany_top_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 38.34 108.315 38.48 108.8 ;
+    END
+  END chany_top_out[13]
+  PIN chany_top_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 14.88 108.315 15.02 108.8 ;
+    END
+  END chany_top_out[14]
+  PIN chany_top_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 36.5 108.315 36.64 108.8 ;
+    END
+  END chany_top_out[15]
+  PIN chany_top_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.96 108.315 60.1 108.8 ;
+    END
+  END chany_top_out[16]
+  PIN chany_top_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 15.8 108.315 15.94 108.8 ;
+    END
+  END chany_top_out[17]
+  PIN chany_top_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 37.42 108.315 37.56 108.8 ;
+    END
+  END chany_top_out[18]
+  PIN chany_top_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 57.2 108.315 57.34 108.8 ;
+    END
+  END chany_top_out[19]
+  PIN chanx_right_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 70.23 92 70.53 ;
+    END
+  END chanx_right_out[0]
+  PIN chanx_right_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 72.95 92 73.25 ;
+    END
+  END chanx_right_out[1]
+  PIN chanx_right_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 25.35 92 25.65 ;
+    END
+  END chanx_right_out[2]
+  PIN chanx_right_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 49.83 92 50.13 ;
+    END
+  END chanx_right_out[3]
+  PIN chanx_right_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 56.63 92 56.93 ;
+    END
+  END chanx_right_out[4]
+  PIN chanx_right_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 53.91 92 54.21 ;
+    END
+  END chanx_right_out[5]
+  PIN chanx_right_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 85.19 92 85.49 ;
+    END
+  END chanx_right_out[6]
+  PIN chanx_right_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 33.51 92 33.81 ;
+    END
+  END chanx_right_out[7]
+  PIN chanx_right_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 32.15 92 32.45 ;
+    END
+  END chanx_right_out[8]
+  PIN chanx_right_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 55.27 92 55.57 ;
+    END
+  END chanx_right_out[9]
+  PIN chanx_right_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 26.71 92 27.01 ;
+    END
+  END chanx_right_out[10]
+  PIN chanx_right_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 52.55 92 52.85 ;
+    END
+  END chanx_right_out[11]
+  PIN chanx_right_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 15.83 92 16.13 ;
+    END
+  END chanx_right_out[12]
+  PIN chanx_right_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 47.11 92 47.41 ;
+    END
+  END chanx_right_out[13]
+  PIN chanx_right_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 30.79 92 31.09 ;
+    END
+  END chanx_right_out[14]
+  PIN chanx_right_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 68.87 92 69.17 ;
+    END
+  END chanx_right_out[15]
+  PIN chanx_right_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 14.47 92 14.77 ;
+    END
+  END chanx_right_out[16]
+  PIN chanx_right_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 59.35 92 59.65 ;
+    END
+  END chanx_right_out[17]
+  PIN chanx_right_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 28.07 92 28.37 ;
+    END
+  END chanx_right_out[18]
+  PIN chanx_right_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 89.27 92 89.57 ;
+    END
+  END chanx_right_out[19]
+  PIN chany_bottom_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 50.76 0 50.9 0.485 ;
+    END
+  END chany_bottom_out[0]
+  PIN chany_bottom_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 57.2 0 57.34 0.485 ;
+    END
+  END chany_bottom_out[1]
+  PIN chany_bottom_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 41.1 0 41.24 0.485 ;
+    END
+  END chany_bottom_out[2]
+  PIN chany_bottom_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 11.2 0 11.34 0.485 ;
+    END
+  END chany_bottom_out[3]
+  PIN chany_bottom_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 33.74 0 33.88 0.485 ;
+    END
+  END chany_bottom_out[4]
+  PIN chany_bottom_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 19.48 0 19.62 0.485 ;
+    END
+  END chany_bottom_out[5]
+  PIN chany_bottom_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 12.12 0 12.26 0.485 ;
+    END
+  END chany_bottom_out[6]
+  PIN chany_bottom_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 36.5 0 36.64 0.485 ;
+    END
+  END chany_bottom_out[7]
+  PIN chany_bottom_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 18.56 0 18.7 0.485 ;
+    END
+  END chany_bottom_out[8]
+  PIN chany_bottom_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.04 0 13.18 0.485 ;
+    END
+  END chany_bottom_out[9]
+  PIN chany_bottom_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.04 0 59.18 0.485 ;
+    END
+  END chany_bottom_out[10]
+  PIN chany_bottom_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 17.64 0 17.78 0.485 ;
+    END
+  END chany_bottom_out[11]
+  PIN chany_bottom_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 10.28 0 10.42 0.485 ;
+    END
+  END chany_bottom_out[12]
+  PIN chany_bottom_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.96 0 14.1 0.485 ;
+    END
+  END chany_bottom_out[13]
+  PIN chany_bottom_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 37.42 0 37.56 0.485 ;
+    END
+  END chany_bottom_out[14]
+  PIN chany_bottom_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 16.72 0 16.86 0.485 ;
+    END
+  END chany_bottom_out[15]
+  PIN chany_bottom_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 54.44 0 54.58 0.485 ;
+    END
+  END chany_bottom_out[16]
+  PIN chany_bottom_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 14.88 0 15.02 0.485 ;
+    END
+  END chany_bottom_out[17]
+  PIN chany_bottom_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 2.46 0 2.6 0.485 ;
+    END
+  END chany_bottom_out[18]
+  PIN chany_bottom_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 15.8 0 15.94 0.485 ;
+    END
+  END chany_bottom_out[19]
+  PIN ccff_tail[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 34.66 0 34.8 0.485 ;
+    END
+  END ccff_tail[0]
+  PIN prog_clk_0_E_in
+    DIRECTION INPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 40.31 92 40.61 ;
+    END
+  END prog_clk_0_E_in
+  PIN VDD
+    DIRECTION INPUT ;
+    USE POWER ;
+    PORT
+      LAYER met1 ;
+        RECT 0 2.48 0.48 2.96 ;
+        RECT 65.76 2.48 66.24 2.96 ;
+        RECT 0 7.92 0.48 8.4 ;
+        RECT 65.76 7.92 66.24 8.4 ;
+        RECT 0 13.36 0.48 13.84 ;
+        RECT 91.52 13.36 92 13.84 ;
+        RECT 0 18.8 0.48 19.28 ;
+        RECT 91.52 18.8 92 19.28 ;
+        RECT 0 24.24 0.48 24.72 ;
+        RECT 91.52 24.24 92 24.72 ;
+        RECT 0 29.68 0.48 30.16 ;
+        RECT 91.52 29.68 92 30.16 ;
+        RECT 0 35.12 0.48 35.6 ;
+        RECT 91.52 35.12 92 35.6 ;
+        RECT 0 40.56 0.48 41.04 ;
+        RECT 91.52 40.56 92 41.04 ;
+        RECT 0 46 0.48 46.48 ;
+        RECT 91.52 46 92 46.48 ;
+        RECT 0 51.44 0.48 51.92 ;
+        RECT 91.52 51.44 92 51.92 ;
+        RECT 0 56.88 0.48 57.36 ;
+        RECT 91.52 56.88 92 57.36 ;
+        RECT 0 62.32 0.48 62.8 ;
+        RECT 91.52 62.32 92 62.8 ;
+        RECT 0 67.76 0.48 68.24 ;
+        RECT 91.52 67.76 92 68.24 ;
+        RECT 0 73.2 0.48 73.68 ;
+        RECT 91.52 73.2 92 73.68 ;
+        RECT 0 78.64 0.48 79.12 ;
+        RECT 91.52 78.64 92 79.12 ;
+        RECT 0 84.08 0.48 84.56 ;
+        RECT 91.52 84.08 92 84.56 ;
+        RECT 0 89.52 0.48 90 ;
+        RECT 91.52 89.52 92 90 ;
+        RECT 0 94.96 0.48 95.44 ;
+        RECT 91.52 94.96 92 95.44 ;
+        RECT 0 100.4 0.48 100.88 ;
+        RECT 65.76 100.4 66.24 100.88 ;
+        RECT 0 105.84 0.48 106.32 ;
+        RECT 65.76 105.84 66.24 106.32 ;
+      LAYER met5 ;
+        RECT 0 22.2 3.2 25.4 ;
+        RECT 88.8 22.2 92 25.4 ;
+        RECT 0 63 3.2 66.2 ;
+        RECT 88.8 63 92 66.2 ;
+      LAYER met4 ;
+        RECT 10.74 0 11.34 0.6 ;
+        RECT 40.18 0 40.78 0.6 ;
+        RECT 80.66 10.88 81.26 11.48 ;
+        RECT 80.66 97.32 81.26 97.92 ;
+        RECT 10.74 108.2 11.34 108.8 ;
+        RECT 40.18 108.2 40.78 108.8 ;
+    END
+  END VDD
+  PIN VSS
+    DIRECTION INPUT ;
+    USE GROUND ;
+    PORT
+      LAYER met1 ;
+        RECT 0 0 45.4 0.24 ;
+        RECT 46.6 0 66.24 0.24 ;
+        RECT 0 5.2 0.48 5.68 ;
+        RECT 65.76 5.2 66.24 5.68 ;
+        RECT 0 10.64 0.48 11.12 ;
+        RECT 46.6 10.64 92 11.12 ;
+        RECT 0 16.08 0.48 16.56 ;
+        RECT 91.52 16.08 92 16.56 ;
+        RECT 0 21.52 0.48 22 ;
+        RECT 91.52 21.52 92 22 ;
+        RECT 0 26.96 0.48 27.44 ;
+        RECT 91.52 26.96 92 27.44 ;
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+      RECT 91.08 27.115 92 27.285 ;
+      RECT 0 27.115 3.68 27.285 ;
+      RECT 91.08 24.395 92 24.565 ;
+      RECT 0 24.395 3.68 24.565 ;
+      RECT 91.08 21.675 92 21.845 ;
+      RECT 0 21.675 3.68 21.845 ;
+      RECT 90.16 18.955 92 19.125 ;
+      RECT 0 18.955 3.68 19.125 ;
+      RECT 90.16 16.235 92 16.405 ;
+      RECT 0 16.235 3.68 16.405 ;
+      RECT 91.08 13.515 92 13.685 ;
+      RECT 0 13.515 3.68 13.685 ;
+      RECT 62.56 10.795 92 10.965 ;
+      RECT 0 10.795 3.68 10.965 ;
+      RECT 62.56 8.075 66.24 8.245 ;
+      RECT 0 8.075 3.68 8.245 ;
+      RECT 65.32 5.355 66.24 5.525 ;
+      RECT 0 5.355 3.68 5.525 ;
+      RECT 62.56 2.635 66.24 2.805 ;
+      RECT 0 2.635 3.68 2.805 ;
+      RECT 0 -0.085 66.24 0.085 ;
+      POLYGON 66.07 108.63 66.07 97.75 91.83 97.75 91.83 11.05 66.07 11.05 66.07 0.17 0.17 0.17 0.17 108.63 ;
+    LAYER mcon ;
+      RECT 62.46 98.345 62.63 98.515 ;
+      RECT 47.065 98.345 47.235 98.515 ;
+      RECT 48.045 11.305 48.215 11.475 ;
+      RECT 47.525 10.285 47.695 10.455 ;
+    LAYER via ;
+      RECT 55.125 108.725 55.275 108.875 ;
+      RECT 25.685 108.725 25.835 108.875 ;
+      RECT 58.575 98.355 58.725 98.505 ;
+      RECT 55.125 97.845 55.275 97.995 ;
+      RECT 49.835 11.315 49.985 11.465 ;
+      RECT 55.125 10.805 55.275 10.955 ;
+      RECT 55.125 -0.075 55.275 0.075 ;
+      RECT 25.685 -0.075 25.835 0.075 ;
+    LAYER via2 ;
+      RECT 55.1 108.7 55.3 108.9 ;
+      RECT 25.66 108.7 25.86 108.9 ;
+      RECT 90.75 53.96 90.95 54.16 ;
+      RECT 55.1 -0.1 55.3 0.1 ;
+      RECT 25.66 -0.1 25.86 0.1 ;
+    LAYER via3 ;
+      RECT 55.1 108.7 55.3 108.9 ;
+      RECT 25.66 108.7 25.86 108.9 ;
+      RECT 55.1 -0.1 55.3 0.1 ;
+      RECT 25.66 -0.1 25.86 0.1 ;
+    LAYER OVERLAP ;
+      POLYGON 0 0 0 108.8 66.24 108.8 66.24 97.92 92 97.92 92 10.88 66.24 10.88 66.24 0 ;
+  END
+END sb_0__1_
+
+END LIBRARY
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef
new file mode 100644
index 0000000..40310c3
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef
@@ -0,0 +1,1366 @@
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+
+UNITS
+  DATABASE MICRONS 1000 ;
+END UNITS
+
+MANUFACTURINGGRID 0.005 ;
+
+LAYER li1
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.17 ;
+END li1
+
+LAYER mcon
+  TYPE CUT ;
+END mcon
+
+LAYER met1
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.34 ;
+  WIDTH 0.14 ;
+END met1
+
+LAYER via
+  TYPE CUT ;
+END via
+
+LAYER met2
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.14 ;
+END met2
+
+LAYER via2
+  TYPE CUT ;
+END via2
+
+LAYER met3
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.68 ;
+  WIDTH 0.3 ;
+END met3
+
+LAYER via3
+  TYPE CUT ;
+END via3
+
+LAYER met4
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.92 ;
+  WIDTH 0.3 ;
+END met4
+
+LAYER via4
+  TYPE CUT ;
+END via4
+
+LAYER met5
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 3.4 ;
+  WIDTH 1.6 ;
+END met5
+
+LAYER nwell
+  TYPE MASTERSLICE ;
+END nwell
+
+LAYER pwell
+  TYPE MASTERSLICE ;
+END pwell
+
+LAYER OVERLAP
+  TYPE OVERLAP ;
+END OVERLAP
+
+VIA L1M1_PR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR
+
+VIA L1M1_PR_R
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_R
+
+VIA L1M1_PR_M
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_M
+
+VIA L1M1_PR_MR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR_MR
+
+VIA L1M1_PR_C
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.145 0.145 0.145 ;
+END L1M1_PR_C
+
+VIA M1M2_PR
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR
+
+VIA M1M2_PR_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_Enc
+
+VIA M1M2_PR_R
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_R
+
+VIA M1M2_PR_R_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_R_Enc
+
+VIA M1M2_PR_M
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIA M1M2_PR_M_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_M_Enc
+
+VIA M1M2_PR_MR
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIA M1M2_PR_MR_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_MR_Enc
+
+VIA M1M2_PR_C
+  LAYER met1 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIA M2M3_PR
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIA M2M3_PR_R
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIA M2M3_PR_M
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIA M2M3_PR_MR
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIA M2M3_PR_C
+  LAYER met2 ;
+    RECT -0.185 -0.185 0.185 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIA M3M4_PR
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIA M3M4_PR_R
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIA M3M4_PR_M
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIA M3M4_PR_MR
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIA M3M4_PR_C
+  LAYER met3 ;
+    RECT -0.19 -0.19 0.19 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIA M4M5_PR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIA M4M5_PR_R
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIA M4M5_PR_M
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIA M4M5_PR_MR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIA M4M5_PR_C
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+  CLASS CORE ;
+  SYMMETRY Y ;
+  SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+  CLASS CORE ;
+  SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+MACRO sb_0__2_
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 92 BY 97.92 ;
+  SYMMETRY X Y ;
+  PIN chanx_right_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 90.63 92 90.93 ;
+    END
+  END chanx_right_in[0]
+  PIN chanx_right_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 74.99 92 75.29 ;
+    END
+  END chanx_right_in[1]
+  PIN chanx_right_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 65.47 92 65.77 ;
+    END
+  END chanx_right_in[2]
+  PIN chanx_right_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 76.35 92 76.65 ;
+    END
+  END chanx_right_in[3]
+  PIN chanx_right_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 32.15 92 32.45 ;
+    END
+  END chanx_right_in[4]
+  PIN chanx_right_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 60.03 92 60.33 ;
+    END
+  END chanx_right_in[5]
+  PIN chanx_right_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 51.19 92 51.49 ;
+    END
+  END chanx_right_in[6]
+  PIN chanx_right_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 45.07 92 45.37 ;
+    END
+  END chanx_right_in[7]
+  PIN chanx_right_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 64.11 92 64.41 ;
+    END
+  END chanx_right_in[8]
+  PIN chanx_right_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 29.43 92 29.73 ;
+    END
+  END chanx_right_in[9]
+  PIN chanx_right_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 69.55 92 69.85 ;
+    END
+  END chanx_right_in[10]
+  PIN chanx_right_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 73.63 92 73.93 ;
+    END
+  END chanx_right_in[11]
+  PIN chanx_right_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 35.55 92 35.85 ;
+    END
+  END chanx_right_in[12]
+  PIN chanx_right_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 19.23 92 19.53 ;
+    END
+  END chanx_right_in[13]
+  PIN chanx_right_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 36.91 92 37.21 ;
+    END
+  END chanx_right_in[14]
+  PIN chanx_right_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 40.99 92 41.29 ;
+    END
+  END chanx_right_in[15]
+  PIN chanx_right_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 57.31 92 57.61 ;
+    END
+  END chanx_right_in[16]
+  PIN chanx_right_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 70.91 92 71.21 ;
+    END
+  END chanx_right_in[17]
+  PIN chanx_right_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 49.83 92 50.13 ;
+    END
+  END chanx_right_in[18]
+  PIN chanx_right_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 68.19 92 68.49 ;
+    END
+  END chanx_right_in[19]
+  PIN right_top_grid_pin_1_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 43.71 92 44.01 ;
+    END
+  END right_top_grid_pin_1_[0]
+  PIN right_bottom_grid_pin_34_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 79.28 10.88 79.42 11.365 ;
+    END
+  END right_bottom_grid_pin_34_[0]
+  PIN right_bottom_grid_pin_35_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 85.72 10.88 85.86 11.365 ;
+    END
+  END right_bottom_grid_pin_35_[0]
+  PIN right_bottom_grid_pin_36_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 82.04 10.88 82.18 11.365 ;
+    END
+  END right_bottom_grid_pin_36_[0]
+  PIN right_bottom_grid_pin_37_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 87.1 10.88 87.24 11.365 ;
+    END
+  END right_bottom_grid_pin_37_[0]
+  PIN right_bottom_grid_pin_38_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 81.12 10.88 81.26 11.365 ;
+    END
+  END right_bottom_grid_pin_38_[0]
+  PIN right_bottom_grid_pin_39_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 78.36 10.88 78.5 11.365 ;
+    END
+  END right_bottom_grid_pin_39_[0]
+  PIN right_bottom_grid_pin_40_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 80.2 10.88 80.34 11.365 ;
+    END
+  END right_bottom_grid_pin_40_[0]
+  PIN right_bottom_grid_pin_41_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 82.96 10.88 83.1 11.365 ;
+    END
+  END right_bottom_grid_pin_41_[0]
+  PIN chany_bottom_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 49.84 0 49.98 0.485 ;
+    END
+  END chany_bottom_in[0]
+  PIN chany_bottom_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.96 0 60.1 0.485 ;
+    END
+  END chany_bottom_in[1]
+  PIN chany_bottom_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 60.88 0 61.02 0.485 ;
+    END
+  END chany_bottom_in[2]
+  PIN chany_bottom_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.64 0 63.78 0.485 ;
+    END
+  END chany_bottom_in[3]
+  PIN chany_bottom_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.6 0 52.74 0.485 ;
+    END
+  END chany_bottom_in[4]
+  PIN chany_bottom_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 39.26 0 39.4 0.485 ;
+    END
+  END chany_bottom_in[5]
+  PIN chany_bottom_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 35.58 0 35.72 0.485 ;
+    END
+  END chany_bottom_in[6]
+  PIN chany_bottom_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 62.72 0 62.86 0.485 ;
+    END
+  END chany_bottom_in[7]
+  PIN chany_bottom_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 9.36 0 9.5 0.485 ;
+    END
+  END chany_bottom_in[8]
+  PIN chany_bottom_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 8.44 0 8.58 0.485 ;
+    END
+  END chany_bottom_in[9]
+  PIN chany_bottom_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 26.38 0 26.52 0.485 ;
+    END
+  END chany_bottom_in[10]
+  PIN chany_bottom_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 51.68 0 51.82 0.485 ;
+    END
+  END chany_bottom_in[11]
+  PIN chany_bottom_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.52 0 53.66 0.485 ;
+    END
+  END chany_bottom_in[12]
+  PIN chany_bottom_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 56.28 0 56.42 0.485 ;
+    END
+  END chany_bottom_in[13]
+  PIN chany_bottom_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.12 0 58.26 0.485 ;
+    END
+  END chany_bottom_in[14]
+  PIN chany_bottom_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 38.34 0 38.48 0.485 ;
+    END
+  END chany_bottom_in[15]
+  PIN chany_bottom_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.8 0 61.94 0.485 ;
+    END
+  END chany_bottom_in[16]
+  PIN chany_bottom_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 32.82 0 32.96 0.485 ;
+    END
+  END chany_bottom_in[17]
+  PIN chany_bottom_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 21.32 0 21.46 0.485 ;
+    END
+  END chany_bottom_in[18]
+  PIN chany_bottom_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 40.18 0 40.32 0.485 ;
+    END
+  END chany_bottom_in[19]
+  PIN bottom_left_grid_pin_1_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 20.4 0 20.54 0.485 ;
+    END
+  END bottom_left_grid_pin_1_[0]
+  PIN ccff_head[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 61.39 92 61.69 ;
+    END
+  END ccff_head[0]
+  PIN chanx_right_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 17.87 92 18.17 ;
+    END
+  END chanx_right_out[0]
+  PIN chanx_right_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 46.43 92 46.73 ;
+    END
+  END chanx_right_out[1]
+  PIN chanx_right_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 39.63 92 39.93 ;
+    END
+  END chanx_right_out[2]
+  PIN chanx_right_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 25.35 92 25.65 ;
+    END
+  END chanx_right_out[3]
+  PIN chanx_right_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 47.79 92 48.09 ;
+    END
+  END chanx_right_out[4]
+  PIN chanx_right_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 28.07 92 28.37 ;
+    END
+  END chanx_right_out[5]
+  PIN chanx_right_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 58.67 92 58.97 ;
+    END
+  END chanx_right_out[6]
+  PIN chanx_right_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 23.99 92 24.29 ;
+    END
+  END chanx_right_out[7]
+  PIN chanx_right_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 42.35 92 42.65 ;
+    END
+  END chanx_right_out[8]
+  PIN chanx_right_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 30.79 92 31.09 ;
+    END
+  END chanx_right_out[9]
+  PIN chanx_right_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 53.23 92 53.53 ;
+    END
+  END chanx_right_out[10]
+  PIN chanx_right_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 26.71 92 27.01 ;
+    END
+  END chanx_right_out[11]
+  PIN chanx_right_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 72.27 92 72.57 ;
+    END
+  END chanx_right_out[12]
+  PIN chanx_right_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 20.59 92 20.89 ;
+    END
+  END chanx_right_out[13]
+  PIN chanx_right_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 55.95 92 56.25 ;
+    END
+  END chanx_right_out[14]
+  PIN chanx_right_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 33.51 92 33.81 ;
+    END
+  END chanx_right_out[15]
+  PIN chanx_right_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 66.83 92 67.13 ;
+    END
+  END chanx_right_out[16]
+  PIN chanx_right_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 38.27 92 38.57 ;
+    END
+  END chanx_right_out[17]
+  PIN chanx_right_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 54.59 92 54.89 ;
+    END
+  END chanx_right_out[18]
+  PIN chanx_right_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 22.63 92 22.93 ;
+    END
+  END chanx_right_out[19]
+  PIN chany_bottom_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 50.76 0 50.9 0.485 ;
+    END
+  END chany_bottom_out[0]
+  PIN chany_bottom_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 57.2 0 57.34 0.485 ;
+    END
+  END chany_bottom_out[1]
+  PIN chany_bottom_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 41.1 0 41.24 0.485 ;
+    END
+  END chany_bottom_out[2]
+  PIN chany_bottom_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 11.2 0 11.34 0.485 ;
+    END
+  END chany_bottom_out[3]
+  PIN chany_bottom_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 33.74 0 33.88 0.485 ;
+    END
+  END chany_bottom_out[4]
+  PIN chany_bottom_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 19.48 0 19.62 0.485 ;
+    END
+  END chany_bottom_out[5]
+  PIN chany_bottom_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 12.12 0 12.26 0.485 ;
+    END
+  END chany_bottom_out[6]
+  PIN chany_bottom_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 36.5 0 36.64 0.485 ;
+    END
+  END chany_bottom_out[7]
+  PIN chany_bottom_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 18.56 0 18.7 0.485 ;
+    END
+  END chany_bottom_out[8]
+  PIN chany_bottom_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.04 0 13.18 0.485 ;
+    END
+  END chany_bottom_out[9]
+  PIN chany_bottom_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.04 0 59.18 0.485 ;
+    END
+  END chany_bottom_out[10]
+  PIN chany_bottom_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 17.64 0 17.78 0.485 ;
+    END
+  END chany_bottom_out[11]
+  PIN chany_bottom_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 10.28 0 10.42 0.485 ;
+    END
+  END chany_bottom_out[12]
+  PIN chany_bottom_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.96 0 14.1 0.485 ;
+    END
+  END chany_bottom_out[13]
+  PIN chany_bottom_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 37.42 0 37.56 0.485 ;
+    END
+  END chany_bottom_out[14]
+  PIN chany_bottom_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 16.72 0 16.86 0.485 ;
+    END
+  END chany_bottom_out[15]
+  PIN chany_bottom_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 54.44 0 54.58 0.485 ;
+    END
+  END chany_bottom_out[16]
+  PIN chany_bottom_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 14.88 0 15.02 0.485 ;
+    END
+  END chany_bottom_out[17]
+  PIN chany_bottom_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 2.46 0 2.6 0.485 ;
+    END
+  END chany_bottom_out[18]
+  PIN chany_bottom_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 15.8 0 15.94 0.485 ;
+    END
+  END chany_bottom_out[19]
+  PIN ccff_tail[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 34.66 0 34.8 0.485 ;
+    END
+  END ccff_tail[0]
+  PIN SC_IN_TOP
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 68.7 10.88 68.84 11.365 ;
+    END
+  END SC_IN_TOP
+  PIN SC_OUT_BOT
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 14.47 92 14.77 ;
+    END
+  END SC_OUT_BOT
+  PIN prog_clk_0_E_in
+    DIRECTION INPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 62.75 92 63.05 ;
+    END
+  END prog_clk_0_E_in
+  PIN VDD
+    DIRECTION INPUT ;
+    USE POWER ;
+    PORT
+      LAYER met5 ;
+        RECT 0 22.2 3.2 25.4 ;
+        RECT 88.8 22.2 92 25.4 ;
+        RECT 0 63 3.2 66.2 ;
+        RECT 88.8 63 92 66.2 ;
+      LAYER met4 ;
+        RECT 10.74 0 11.34 0.6 ;
+        RECT 40.18 0 40.78 0.6 ;
+        RECT 80.66 10.88 81.26 11.48 ;
+        RECT 10.74 97.32 11.34 97.92 ;
+        RECT 40.18 97.32 40.78 97.92 ;
+        RECT 80.66 97.32 81.26 97.92 ;
+      LAYER met1 ;
+        RECT 0 2.48 0.48 2.96 ;
+        RECT 65.76 2.48 66.24 2.96 ;
+        RECT 0 7.92 0.48 8.4 ;
+        RECT 65.76 7.92 66.24 8.4 ;
+        RECT 0 13.36 0.48 13.84 ;
+        RECT 91.52 13.36 92 13.84 ;
+        RECT 0 18.8 0.48 19.28 ;
+        RECT 91.52 18.8 92 19.28 ;
+        RECT 0 24.24 0.48 24.72 ;
+        RECT 91.52 24.24 92 24.72 ;
+        RECT 0 29.68 0.48 30.16 ;
+        RECT 91.52 29.68 92 30.16 ;
+        RECT 0 35.12 0.48 35.6 ;
+        RECT 91.52 35.12 92 35.6 ;
+        RECT 0 40.56 0.48 41.04 ;
+        RECT 91.52 40.56 92 41.04 ;
+        RECT 0 46 0.48 46.48 ;
+        RECT 91.52 46 92 46.48 ;
+        RECT 0 51.44 0.48 51.92 ;
+        RECT 91.52 51.44 92 51.92 ;
+        RECT 0 56.88 0.48 57.36 ;
+        RECT 91.52 56.88 92 57.36 ;
+        RECT 0 62.32 0.48 62.8 ;
+        RECT 91.52 62.32 92 62.8 ;
+        RECT 0 67.76 0.48 68.24 ;
+        RECT 91.52 67.76 92 68.24 ;
+        RECT 0 73.2 0.48 73.68 ;
+        RECT 91.52 73.2 92 73.68 ;
+        RECT 0 78.64 0.48 79.12 ;
+        RECT 91.52 78.64 92 79.12 ;
+        RECT 0 84.08 0.48 84.56 ;
+        RECT 91.52 84.08 92 84.56 ;
+        RECT 0 89.52 0.48 90 ;
+        RECT 91.52 89.52 92 90 ;
+        RECT 0 94.96 0.48 95.44 ;
+        RECT 91.52 94.96 92 95.44 ;
+    END
+  END VDD
+  PIN VSS
+    DIRECTION INPUT ;
+    USE GROUND ;
+    PORT
+      LAYER met4 ;
+        RECT 25.46 0 26.06 0.6 ;
+        RECT 54.9 0 55.5 0.6 ;
+        RECT 25.46 97.32 26.06 97.92 ;
+        RECT 54.9 97.32 55.5 97.92 ;
+      LAYER met5 ;
+        RECT 0 42.6 3.2 45.8 ;
+        RECT 88.8 42.6 92 45.8 ;
+        RECT 0 83.4 3.2 86.6 ;
+        RECT 88.8 83.4 92 86.6 ;
+      LAYER met1 ;
+        RECT 0 0 45.4 0.24 ;
+        RECT 46.6 0 66.24 0.24 ;
+        RECT 0 5.2 0.48 5.68 ;
+        RECT 65.76 5.2 66.24 5.68 ;
+        RECT 0 10.64 0.48 11.12 ;
+        RECT 46.6 10.64 92 11.12 ;
+        RECT 0 16.08 0.48 16.56 ;
+        RECT 91.52 16.08 92 16.56 ;
+        RECT 0 21.52 0.48 22 ;
+        RECT 91.52 21.52 92 22 ;
+        RECT 0 26.96 0.48 27.44 ;
+        RECT 91.52 26.96 92 27.44 ;
+        RECT 0 32.4 0.48 32.88 ;
+        RECT 91.52 32.4 92 32.88 ;
+        RECT 0 37.84 0.48 38.32 ;
+        RECT 91.52 37.84 92 38.32 ;
+        RECT 0 43.28 0.48 43.76 ;
+        RECT 91.52 43.28 92 43.76 ;
+        RECT 0 48.72 0.48 49.2 ;
+        RECT 91.52 48.72 92 49.2 ;
+        RECT 0 54.16 0.48 54.64 ;
+        RECT 91.52 54.16 92 54.64 ;
+        RECT 0 59.6 0.48 60.08 ;
+        RECT 91.52 59.6 92 60.08 ;
+        RECT 0 65.04 0.48 65.52 ;
+        RECT 91.52 65.04 92 65.52 ;
+        RECT 0 70.48 0.48 70.96 ;
+        RECT 91.52 70.48 92 70.96 ;
+        RECT 0 75.92 0.48 76.4 ;
+        RECT 91.52 75.92 92 76.4 ;
+        RECT 0 81.36 0.48 81.84 ;
+        RECT 91.52 81.36 92 81.84 ;
+        RECT 0 86.8 0.48 87.28 ;
+        RECT 91.52 86.8 92 87.28 ;
+        RECT 0 92.24 0.48 92.72 ;
+        RECT 91.52 92.24 92 92.72 ;
+        RECT 0 97.68 45.4 97.92 ;
+        RECT 46.6 97.68 92 97.92 ;
+    END
+  END VSS
+  OBS
+    LAYER met3 ;
+      POLYGON 55.365 98.085 55.365 98.08 55.58 98.08 55.58 97.76 55.365 97.76 55.365 97.755 55.035 97.755 55.035 97.76 54.82 97.76 54.82 98.08 55.035 98.08 55.035 98.085 ;
+      POLYGON 25.925 98.085 25.925 98.08 26.14 98.08 26.14 97.76 25.925 97.76 25.925 97.755 25.595 97.755 25.595 97.76 25.38 97.76 25.38 98.08 25.595 98.08 25.595 98.085 ;
+      POLYGON 66.175 11.385 66.175 11.055 65.845 11.055 65.845 11.07 57.12 11.07 57.12 11.37 65.845 11.37 65.845 11.385 ;
+      POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ;
+      POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ;
+      POLYGON 91.6 97.52 91.6 91.33 90.8 91.33 90.8 90.23 91.6 90.23 91.6 77.05 90.8 77.05 90.8 75.95 91.6 75.95 91.6 75.69 90.8 75.69 90.8 74.59 91.6 74.59 91.6 74.33 90.8 74.33 90.8 73.23 91.6 73.23 91.6 72.97 90.8 72.97 90.8 71.87 91.6 71.87 91.6 71.61 90.8 71.61 90.8 70.51 91.6 70.51 91.6 70.25 90.8 70.25 90.8 69.15 91.6 69.15 91.6 68.89 90.8 68.89 90.8 67.79 91.6 67.79 91.6 67.53 90.8 67.53 90.8 66.43 91.6 66.43 91.6 66.17 90.8 66.17 90.8 65.07 91.6 65.07 91.6 64.81 90.8 64.81 90.8 63.71 91.6 63.71 91.6 63.45 90.8 63.45 90.8 62.35 91.6 62.35 91.6 62.09 90.8 62.09 90.8 60.99 91.6 60.99 91.6 60.73 90.8 60.73 90.8 59.63 91.6 59.63 91.6 59.37 90.8 59.37 90.8 58.27 91.6 58.27 91.6 58.01 90.8 58.01 90.8 56.91 91.6 56.91 91.6 56.65 90.8 56.65 90.8 55.55 91.6 55.55 91.6 55.29 90.8 55.29 90.8 54.19 91.6 54.19 91.6 53.93 90.8 53.93 90.8 52.83 91.6 52.83 91.6 51.89 90.8 51.89 90.8 50.79 91.6 50.79 91.6 50.53 90.8 50.53 90.8 49.43 91.6 49.43 91.6 48.49 90.8 48.49 90.8 47.39 91.6 47.39 91.6 47.13 90.8 47.13 90.8 46.03 91.6 46.03 91.6 45.77 90.8 45.77 90.8 44.67 91.6 44.67 91.6 44.41 90.8 44.41 90.8 43.31 91.6 43.31 91.6 43.05 90.8 43.05 90.8 41.95 91.6 41.95 91.6 41.69 90.8 41.69 90.8 40.59 91.6 40.59 91.6 40.33 90.8 40.33 90.8 39.23 91.6 39.23 91.6 38.97 90.8 38.97 90.8 37.87 91.6 37.87 91.6 37.61 90.8 37.61 90.8 36.51 91.6 36.51 91.6 36.25 90.8 36.25 90.8 35.15 91.6 35.15 91.6 34.21 90.8 34.21 90.8 33.11 91.6 33.11 91.6 32.85 90.8 32.85 90.8 31.75 91.6 31.75 91.6 31.49 90.8 31.49 90.8 30.39 91.6 30.39 91.6 30.13 90.8 30.13 90.8 29.03 91.6 29.03 91.6 28.77 90.8 28.77 90.8 27.67 91.6 27.67 91.6 27.41 90.8 27.41 90.8 26.31 91.6 26.31 91.6 26.05 90.8 26.05 90.8 24.95 91.6 24.95 91.6 24.69 90.8 24.69 90.8 23.59 91.6 23.59 91.6 23.33 90.8 23.33 90.8 22.23 91.6 22.23 91.6 21.29 90.8 21.29 90.8 20.19 91.6 20.19 91.6 19.93 90.8 19.93 90.8 18.83 91.6 18.83 91.6 18.57 90.8 18.57 90.8 17.47 91.6 17.47 91.6 15.17 90.8 15.17 90.8 14.07 91.6 14.07 91.6 11.28 65.84 11.28 65.84 0.4 0.4 0.4 0.4 97.52 ;
+    LAYER met2 ;
+      RECT 55.06 97.735 55.34 98.105 ;
+      RECT 25.62 97.735 25.9 98.105 ;
+      POLYGON 66.08 12.82 66.08 11.405 66.15 11.405 66.15 11.035 65.87 11.035 65.87 11.405 65.94 11.405 65.94 12.82 ;
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diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef
new file mode 100644
index 0000000..43bd84e
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef
@@ -0,0 +1,1883 @@
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+  LAYER met2 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIA M2M3_PR
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIA M2M3_PR_R
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIA M2M3_PR_M
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIA M2M3_PR_MR
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIA M2M3_PR_C
+  LAYER met2 ;
+    RECT -0.185 -0.185 0.185 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIA M3M4_PR
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIA M3M4_PR_R
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIA M3M4_PR_M
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIA M3M4_PR_MR
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIA M3M4_PR_C
+  LAYER met3 ;
+    RECT -0.19 -0.19 0.19 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIA M4M5_PR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIA M4M5_PR_R
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIA M4M5_PR_M
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIA M4M5_PR_MR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIA M4M5_PR_C
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+  CLASS CORE ;
+  SYMMETRY Y ;
+  SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+  CLASS CORE ;
+  SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+MACRO sb_1__0_
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 117.76 BY 97.92 ;
+  SYMMETRY X Y ;
+  PIN chany_top_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 61.95 97.12 62.25 97.92 ;
+    END
+  END chany_top_in[0]
+  PIN chany_top_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 84.34 97.435 84.48 97.92 ;
+    END
+  END chany_top_in[1]
+  PIN chany_top_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 83.42 97.435 83.56 97.92 ;
+    END
+  END chany_top_in[2]
+  PIN chany_top_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 73.91 97.12 74.21 97.92 ;
+    END
+  END chany_top_in[3]
+  PIN chany_top_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 81.58 97.435 81.72 97.92 ;
+    END
+  END chany_top_in[4]
+  PIN chany_top_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 56.43 97.12 56.73 97.92 ;
+    END
+  END chany_top_in[5]
+  PIN chany_top_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 55.36 97.435 55.5 97.92 ;
+    END
+  END chany_top_in[6]
+  PIN chany_top_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 60.11 97.12 60.41 97.92 ;
+    END
+  END chany_top_in[7]
+  PIN chany_top_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 85.26 97.435 85.4 97.92 ;
+    END
+  END chany_top_in[8]
+  PIN chany_top_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 88.02 97.435 88.16 97.92 ;
+    END
+  END chany_top_in[9]
+  PIN chany_top_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 82.5 97.435 82.64 97.92 ;
+    END
+  END chany_top_in[10]
+  PIN chany_top_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 88.94 97.435 89.08 97.92 ;
+    END
+  END chany_top_in[11]
+  PIN chany_top_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 67.47 97.12 67.77 97.92 ;
+    END
+  END chany_top_in[12]
+  PIN chany_top_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 67.32 97.435 67.46 97.92 ;
+    END
+  END chany_top_in[13]
+  PIN chany_top_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 52.75 97.12 53.05 97.92 ;
+    END
+  END chany_top_in[14]
+  PIN chany_top_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 58.27 97.12 58.57 97.92 ;
+    END
+  END chany_top_in[15]
+  PIN chany_top_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.58 97.435 58.72 97.92 ;
+    END
+  END chany_top_in[16]
+  PIN chany_top_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 54.59 97.12 54.89 97.92 ;
+    END
+  END chany_top_in[17]
+  PIN chany_top_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 63.79 97.12 64.09 97.92 ;
+    END
+  END chany_top_in[18]
+  PIN chany_top_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 69.31 97.12 69.61 97.92 ;
+    END
+  END chany_top_in[19]
+  PIN top_left_grid_pin_42_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.5 86.555 13.64 87.04 ;
+    END
+  END top_left_grid_pin_42_[0]
+  PIN top_left_grid_pin_43_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 11.66 86.555 11.8 87.04 ;
+    END
+  END top_left_grid_pin_43_[0]
+  PIN top_left_grid_pin_44_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 8.44 86.555 8.58 87.04 ;
+    END
+  END top_left_grid_pin_44_[0]
+  PIN top_left_grid_pin_45_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 12.58 86.555 12.72 87.04 ;
+    END
+  END top_left_grid_pin_45_[0]
+  PIN top_left_grid_pin_46_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 10.28 86.555 10.42 87.04 ;
+    END
+  END top_left_grid_pin_46_[0]
+  PIN top_left_grid_pin_47_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 4.3 86.555 4.44 87.04 ;
+    END
+  END top_left_grid_pin_47_[0]
+  PIN top_left_grid_pin_48_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 9.36 86.555 9.5 87.04 ;
+    END
+  END top_left_grid_pin_48_[0]
+  PIN top_left_grid_pin_49_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.06 86.555 7.2 87.04 ;
+    END
+  END top_left_grid_pin_49_[0]
+  PIN chanx_right_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 66.83 117.76 67.13 ;
+    END
+  END chanx_right_in[0]
+  PIN chanx_right_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 77.71 117.76 78.01 ;
+    END
+  END chanx_right_in[1]
+  PIN chanx_right_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 75.67 117.76 75.97 ;
+    END
+  END chanx_right_in[2]
+  PIN chanx_right_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 59.35 117.76 59.65 ;
+    END
+  END chanx_right_in[3]
+  PIN chanx_right_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 57.99 117.76 58.29 ;
+    END
+  END chanx_right_in[4]
+  PIN chanx_right_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 79.07 117.76 79.37 ;
+    END
+  END chanx_right_in[5]
+  PIN chanx_right_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 48.47 117.76 48.77 ;
+    END
+  END chanx_right_in[6]
+  PIN chanx_right_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 60.71 117.76 61.01 ;
+    END
+  END chanx_right_in[7]
+  PIN chanx_right_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 25.35 117.76 25.65 ;
+    END
+  END chanx_right_in[8]
+  PIN chanx_right_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 22.63 117.76 22.93 ;
+    END
+  END chanx_right_in[9]
+  PIN chanx_right_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 43.03 117.76 43.33 ;
+    END
+  END chanx_right_in[10]
+  PIN chanx_right_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 39.63 117.76 39.93 ;
+    END
+  END chanx_right_in[11]
+  PIN chanx_right_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 29.43 117.76 29.73 ;
+    END
+  END chanx_right_in[12]
+  PIN chanx_right_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 44.39 117.76 44.69 ;
+    END
+  END chanx_right_in[13]
+  PIN chanx_right_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 26.71 117.76 27.01 ;
+    END
+  END chanx_right_in[14]
+  PIN chanx_right_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 49.83 117.76 50.13 ;
+    END
+  END chanx_right_in[15]
+  PIN chanx_right_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 28.07 117.76 28.37 ;
+    END
+  END chanx_right_in[16]
+  PIN chanx_right_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 13.11 117.76 13.41 ;
+    END
+  END chanx_right_in[17]
+  PIN chanx_right_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 41.67 117.76 41.97 ;
+    END
+  END chanx_right_in[18]
+  PIN chanx_right_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 14.47 117.76 14.77 ;
+    END
+  END chanx_right_in[19]
+  PIN right_bottom_grid_pin_1_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 53.91 117.76 54.21 ;
+    END
+  END right_bottom_grid_pin_1_[0]
+  PIN right_bottom_grid_pin_3_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 72.95 117.76 73.25 ;
+    END
+  END right_bottom_grid_pin_3_[0]
+  PIN right_bottom_grid_pin_5_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 70.91 117.76 71.21 ;
+    END
+  END right_bottom_grid_pin_5_[0]
+  PIN right_bottom_grid_pin_7_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 32.83 117.76 33.13 ;
+    END
+  END right_bottom_grid_pin_7_[0]
+  PIN right_bottom_grid_pin_9_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 18.55 117.76 18.85 ;
+    END
+  END right_bottom_grid_pin_9_[0]
+  PIN right_bottom_grid_pin_11_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 56.63 117.76 56.93 ;
+    END
+  END right_bottom_grid_pin_11_[0]
+  PIN right_bottom_grid_pin_13_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 19.91 117.76 20.21 ;
+    END
+  END right_bottom_grid_pin_13_[0]
+  PIN right_bottom_grid_pin_15_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 17.19 117.76 17.49 ;
+    END
+  END right_bottom_grid_pin_15_[0]
+  PIN right_bottom_grid_pin_17_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 21.27 117.76 21.57 ;
+    END
+  END right_bottom_grid_pin_17_[0]
+  PIN chanx_left_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 36.91 0.8 37.21 ;
+    END
+  END chanx_left_in[0]
+  PIN chanx_left_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 21.27 0.8 21.57 ;
+    END
+  END chanx_left_in[1]
+  PIN chanx_left_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 63.43 0.8 63.73 ;
+    END
+  END chanx_left_in[2]
+  PIN chanx_left_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 47.11 0.8 47.41 ;
+    END
+  END chanx_left_in[3]
+  PIN chanx_left_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 45.75 0.8 46.05 ;
+    END
+  END chanx_left_in[4]
+  PIN chanx_left_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 49.83 0.8 50.13 ;
+    END
+  END chanx_left_in[5]
+  PIN chanx_left_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 60.71 0.8 61.01 ;
+    END
+  END chanx_left_in[6]
+  PIN chanx_left_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 55.95 0.8 56.25 ;
+    END
+  END chanx_left_in[7]
+  PIN chanx_left_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 64.79 0.8 65.09 ;
+    END
+  END chanx_left_in[8]
+  PIN chanx_left_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 51.19 0.8 51.49 ;
+    END
+  END chanx_left_in[9]
+  PIN chanx_left_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 29.43 0.8 29.73 ;
+    END
+  END chanx_left_in[10]
+  PIN chanx_left_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 15.83 0.8 16.13 ;
+    END
+  END chanx_left_in[11]
+  PIN chanx_left_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 68.19 0.8 68.49 ;
+    END
+  END chanx_left_in[12]
+  PIN chanx_left_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 48.47 0.8 48.77 ;
+    END
+  END chanx_left_in[13]
+  PIN chanx_left_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 38.27 0.8 38.57 ;
+    END
+  END chanx_left_in[14]
+  PIN chanx_left_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 57.31 0.8 57.61 ;
+    END
+  END chanx_left_in[15]
+  PIN chanx_left_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 62.07 0.8 62.37 ;
+    END
+  END chanx_left_in[16]
+  PIN chanx_left_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 73.63 0.8 73.93 ;
+    END
+  END chanx_left_in[17]
+  PIN chanx_left_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 59.35 0.8 59.65 ;
+    END
+  END chanx_left_in[18]
+  PIN chanx_left_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 78.39 0.8 78.69 ;
+    END
+  END chanx_left_in[19]
+  PIN left_bottom_grid_pin_1_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 26.71 0.8 27.01 ;
+    END
+  END left_bottom_grid_pin_1_[0]
+  PIN left_bottom_grid_pin_3_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 25.35 0.8 25.65 ;
+    END
+  END left_bottom_grid_pin_3_[0]
+  PIN left_bottom_grid_pin_5_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 14.47 0.8 14.77 ;
+    END
+  END left_bottom_grid_pin_5_[0]
+  PIN left_bottom_grid_pin_7_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 32.83 0.8 33.13 ;
+    END
+  END left_bottom_grid_pin_7_[0]
+  PIN left_bottom_grid_pin_9_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 13.11 0.8 13.41 ;
+    END
+  END left_bottom_grid_pin_9_[0]
+  PIN left_bottom_grid_pin_11_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 23.99 0.8 24.29 ;
+    END
+  END left_bottom_grid_pin_11_[0]
+  PIN left_bottom_grid_pin_13_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 22.63 0.8 22.93 ;
+    END
+  END left_bottom_grid_pin_13_[0]
+  PIN left_bottom_grid_pin_15_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 11.75 0.8 12.05 ;
+    END
+  END left_bottom_grid_pin_15_[0]
+  PIN left_bottom_grid_pin_17_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 19.91 0.8 20.21 ;
+    END
+  END left_bottom_grid_pin_17_[0]
+  PIN ccff_head[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 51.19 117.76 51.49 ;
+    END
+  END ccff_head[0]
+  PIN chany_top_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 71 97.435 71.14 97.92 ;
+    END
+  END chany_top_out[0]
+  PIN chany_top_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 77.44 97.435 77.58 97.92 ;
+    END
+  END chany_top_out[1]
+  PIN chany_top_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 74.68 97.435 74.82 97.92 ;
+    END
+  END chany_top_out[2]
+  PIN chany_top_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 78.36 97.435 78.5 97.92 ;
+    END
+  END chany_top_out[3]
+  PIN chany_top_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 39.26 97.435 39.4 97.92 ;
+    END
+  END chany_top_out[4]
+  PIN chany_top_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 60.42 97.435 60.56 97.92 ;
+    END
+  END chany_top_out[5]
+  PIN chany_top_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 54.44 97.435 54.58 97.92 ;
+    END
+  END chany_top_out[6]
+  PIN chany_top_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 65.48 97.435 65.62 97.92 ;
+    END
+  END chany_top_out[7]
+  PIN chany_top_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 66.4 97.435 66.54 97.92 ;
+    END
+  END chany_top_out[8]
+  PIN chany_top_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 79.28 97.435 79.42 97.92 ;
+    END
+  END chany_top_out[9]
+  PIN chany_top_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 57.66 97.435 57.8 97.92 ;
+    END
+  END chany_top_out[10]
+  PIN chany_top_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.18 97.435 63.32 97.92 ;
+    END
+  END chany_top_out[11]
+  PIN chany_top_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 69.16 97.435 69.3 97.92 ;
+    END
+  END chany_top_out[12]
+  PIN chany_top_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 76.52 97.435 76.66 97.92 ;
+    END
+  END chany_top_out[13]
+  PIN chany_top_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.14 97.435 52.28 97.92 ;
+    END
+  END chany_top_out[14]
+  PIN chany_top_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 64.56 97.435 64.7 97.92 ;
+    END
+  END chany_top_out[15]
+  PIN chany_top_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.06 97.435 53.2 97.92 ;
+    END
+  END chany_top_out[16]
+  PIN chany_top_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 70.08 97.435 70.22 97.92 ;
+    END
+  END chany_top_out[17]
+  PIN chany_top_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.5 97.435 59.64 97.92 ;
+    END
+  END chany_top_out[18]
+  PIN chany_top_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 75.6 97.435 75.74 97.92 ;
+    END
+  END chany_top_out[19]
+  PIN chanx_right_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 69.55 117.76 69.85 ;
+    END
+  END chanx_right_out[0]
+  PIN chanx_right_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 52.55 117.76 52.85 ;
+    END
+  END chanx_right_out[1]
+  PIN chanx_right_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 47.11 117.76 47.41 ;
+    END
+  END chanx_right_out[2]
+  PIN chanx_right_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 65.47 117.76 65.77 ;
+    END
+  END chanx_right_out[3]
+  PIN chanx_right_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 36.91 117.76 37.21 ;
+    END
+  END chanx_right_out[4]
+  PIN chanx_right_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 15.83 117.76 16.13 ;
+    END
+  END chanx_right_out[5]
+  PIN chanx_right_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 68.19 117.76 68.49 ;
+    END
+  END chanx_right_out[6]
+  PIN chanx_right_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 62.07 117.76 62.37 ;
+    END
+  END chanx_right_out[7]
+  PIN chanx_right_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 55.27 117.76 55.57 ;
+    END
+  END chanx_right_out[8]
+  PIN chanx_right_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 74.31 117.76 74.61 ;
+    END
+  END chanx_right_out[9]
+  PIN chanx_right_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 31.47 117.76 31.77 ;
+    END
+  END chanx_right_out[10]
+  PIN chanx_right_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 23.99 117.76 24.29 ;
+    END
+  END chanx_right_out[11]
+  PIN chanx_right_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 64.11 117.76 64.41 ;
+    END
+  END chanx_right_out[12]
+  PIN chanx_right_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 81.79 117.76 82.09 ;
+    END
+  END chanx_right_out[13]
+  PIN chanx_right_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 80.43 117.76 80.73 ;
+    END
+  END chanx_right_out[14]
+  PIN chanx_right_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 83.15 117.76 83.45 ;
+    END
+  END chanx_right_out[15]
+  PIN chanx_right_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 35.55 117.76 35.85 ;
+    END
+  END chanx_right_out[16]
+  PIN chanx_right_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 45.75 117.76 46.05 ;
+    END
+  END chanx_right_out[17]
+  PIN chanx_right_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 38.27 117.76 38.57 ;
+    END
+  END chanx_right_out[18]
+  PIN chanx_right_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 34.19 117.76 34.49 ;
+    END
+  END chanx_right_out[19]
+  PIN chanx_left_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 53.23 0.8 53.53 ;
+    END
+  END chanx_left_out[0]
+  PIN chanx_left_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 74.99 0.8 75.29 ;
+    END
+  END chanx_left_out[1]
+  PIN chanx_left_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 54.59 0.8 54.89 ;
+    END
+  END chanx_left_out[2]
+  PIN chanx_left_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 44.39 0.8 44.69 ;
+    END
+  END chanx_left_out[3]
+  PIN chanx_left_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 77.03 0.8 77.33 ;
+    END
+  END chanx_left_out[4]
+  PIN chanx_left_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 31.47 0.8 31.77 ;
+    END
+  END chanx_left_out[5]
+  PIN chanx_left_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 69.55 0.8 69.85 ;
+    END
+  END chanx_left_out[6]
+  PIN chanx_left_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 18.55 0.8 18.85 ;
+    END
+  END chanx_left_out[7]
+  PIN chanx_left_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 34.19 0.8 34.49 ;
+    END
+  END chanx_left_out[8]
+  PIN chanx_left_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 66.83 0.8 67.13 ;
+    END
+  END chanx_left_out[9]
+  PIN chanx_left_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 43.03 0.8 43.33 ;
+    END
+  END chanx_left_out[10]
+  PIN chanx_left_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 39.63 0.8 39.93 ;
+    END
+  END chanx_left_out[11]
+  PIN chanx_left_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 35.55 0.8 35.85 ;
+    END
+  END chanx_left_out[12]
+  PIN chanx_left_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 72.27 0.8 72.57 ;
+    END
+  END chanx_left_out[13]
+  PIN chanx_left_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 79.75 0.8 80.05 ;
+    END
+  END chanx_left_out[14]
+  PIN chanx_left_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 83.15 0.8 83.45 ;
+    END
+  END chanx_left_out[15]
+  PIN chanx_left_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 17.19 0.8 17.49 ;
+    END
+  END chanx_left_out[16]
+  PIN chanx_left_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 28.07 0.8 28.37 ;
+    END
+  END chanx_left_out[17]
+  PIN chanx_left_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 41.67 0.8 41.97 ;
+    END
+  END chanx_left_out[18]
+  PIN chanx_left_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 70.91 0.8 71.21 ;
+    END
+  END chanx_left_out[19]
+  PIN ccff_tail[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 81.11 0.8 81.41 ;
+    END
+  END ccff_tail[0]
+  PIN SC_IN_TOP
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 2.46 86.555 2.6 87.04 ;
+    END
+  END SC_IN_TOP
+  PIN SC_OUT_TOP
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 115.16 86.555 115.3 87.04 ;
+    END
+  END SC_OUT_TOP
+  PIN Test_en_S_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 69.62 0 69.76 0.485 ;
+    END
+  END Test_en_S_in
+  PIN Test_en_N_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 73.76 97.435 73.9 97.92 ;
+    END
+  END Test_en_N_out
+  PIN prog_clk_0_N_in
+    DIRECTION INPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met2 ;
+        RECT 38.34 97.435 38.48 97.92 ;
+    END
+  END prog_clk_0_N_in
+  PIN prog_clk_3_S_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.18 0 63.32 0.485 ;
+    END
+  END prog_clk_3_S_in
+  PIN prog_clk_3_N_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 86.18 97.435 86.32 97.92 ;
+    END
+  END prog_clk_3_N_out
+  PIN clk_3_S_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 65.48 0 65.62 0.485 ;
+    END
+  END clk_3_S_in
+  PIN clk_3_N_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 68.24 97.435 68.38 97.92 ;
+    END
+  END clk_3_N_out
+  PIN VDD
+    DIRECTION INPUT ;
+    USE POWER ;
+    PORT
+      LAYER met1 ;
+        RECT 0 2.48 0.48 2.96 ;
+        RECT 117.28 2.48 117.76 2.96 ;
+        RECT 0 7.92 0.48 8.4 ;
+        RECT 117.28 7.92 117.76 8.4 ;
+        RECT 0 13.36 0.48 13.84 ;
+        RECT 117.28 13.36 117.76 13.84 ;
+        RECT 0 18.8 0.48 19.28 ;
+        RECT 117.28 18.8 117.76 19.28 ;
+        RECT 0 24.24 0.48 24.72 ;
+        RECT 117.28 24.24 117.76 24.72 ;
+        RECT 0 29.68 0.48 30.16 ;
+        RECT 117.28 29.68 117.76 30.16 ;
+        RECT 0 35.12 0.48 35.6 ;
+        RECT 117.28 35.12 117.76 35.6 ;
+        RECT 0 40.56 0.48 41.04 ;
+        RECT 117.28 40.56 117.76 41.04 ;
+        RECT 0 46 0.48 46.48 ;
+        RECT 117.28 46 117.76 46.48 ;
+        RECT 0 51.44 0.48 51.92 ;
+        RECT 117.28 51.44 117.76 51.92 ;
+        RECT 0 56.88 0.48 57.36 ;
+        RECT 117.28 56.88 117.76 57.36 ;
+        RECT 0 62.32 0.48 62.8 ;
+        RECT 117.28 62.32 117.76 62.8 ;
+        RECT 0 67.76 0.48 68.24 ;
+        RECT 117.28 67.76 117.76 68.24 ;
+        RECT 0 73.2 0.48 73.68 ;
+        RECT 117.28 73.2 117.76 73.68 ;
+        RECT 0 78.64 0.48 79.12 ;
+        RECT 117.28 78.64 117.76 79.12 ;
+        RECT 0 84.08 0.48 84.56 ;
+        RECT 117.28 84.08 117.76 84.56 ;
+        RECT 25.76 89.52 26.24 90 ;
+        RECT 91.52 89.52 92 90 ;
+        RECT 25.76 94.96 26.24 95.44 ;
+        RECT 91.52 94.96 92 95.44 ;
+      LAYER met5 ;
+        RECT 0 11.32 3.2 14.52 ;
+        RECT 114.56 11.32 117.76 14.52 ;
+        RECT 0 52.12 3.2 55.32 ;
+        RECT 114.56 52.12 117.76 55.32 ;
+      LAYER met4 ;
+        RECT 36.5 0 37.1 0.6 ;
+        RECT 65.94 0 66.54 0.6 ;
+        RECT 106.42 0 107.02 0.6 ;
+        RECT 106.42 86.44 107.02 87.04 ;
+        RECT 36.5 97.32 37.1 97.92 ;
+        RECT 65.94 97.32 66.54 97.92 ;
+    END
+  END VDD
+  PIN VSS
+    DIRECTION INPUT ;
+    USE GROUND ;
+    PORT
+      LAYER met1 ;
+        RECT 0 0 45.4 0.24 ;
+        RECT 96.28 0 117.76 0.24 ;
+        RECT 0 5.2 0.48 5.68 ;
+        RECT 117.28 5.2 117.76 5.68 ;
+        RECT 0 10.64 0.48 11.12 ;
+        RECT 117.28 10.64 117.76 11.12 ;
+        RECT 0 16.08 0.48 16.56 ;
+        RECT 117.28 16.08 117.76 16.56 ;
+        RECT 0 21.52 0.48 22 ;
+        RECT 117.28 21.52 117.76 22 ;
+        RECT 0 26.96 0.48 27.44 ;
+        RECT 117.28 26.96 117.76 27.44 ;
+        RECT 0 32.4 0.48 32.88 ;
+        RECT 117.28 32.4 117.76 32.88 ;
+        RECT 0 37.84 0.48 38.32 ;
+        RECT 117.28 37.84 117.76 38.32 ;
+        RECT 0 43.28 0.48 43.76 ;
+        RECT 117.28 43.28 117.76 43.76 ;
+        RECT 0 48.72 0.48 49.2 ;
+        RECT 117.28 48.72 117.76 49.2 ;
+        RECT 0 54.16 0.48 54.64 ;
+        RECT 117.28 54.16 117.76 54.64 ;
+        RECT 0 59.6 0.48 60.08 ;
+        RECT 117.28 59.6 117.76 60.08 ;
+        RECT 0 65.04 0.48 65.52 ;
+        RECT 117.28 65.04 117.76 65.52 ;
+        RECT 0 70.48 0.48 70.96 ;
+        RECT 117.28 70.48 117.76 70.96 ;
+        RECT 0 75.92 0.48 76.4 ;
+        RECT 117.28 75.92 117.76 76.4 ;
+        RECT 0 81.36 0.48 81.84 ;
+        RECT 117.28 81.36 117.76 81.84 ;
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+      RECT 116.84 65.195 117.76 65.365 ;
+      RECT 0 65.195 3.68 65.365 ;
+      RECT 116.84 62.475 117.76 62.645 ;
+      RECT 0 62.475 1.84 62.645 ;
+      RECT 116.84 59.755 117.76 59.925 ;
+      RECT 0 59.755 1.84 59.925 ;
+      RECT 116.84 57.035 117.76 57.205 ;
+      RECT 0 57.035 1.84 57.205 ;
+      RECT 116.84 54.315 117.76 54.485 ;
+      RECT 0 54.315 3.68 54.485 ;
+      RECT 116.84 51.595 117.76 51.765 ;
+      RECT 0 51.595 3.68 51.765 ;
+      RECT 116.84 48.875 117.76 49.045 ;
+      RECT 0 48.875 3.68 49.045 ;
+      RECT 116.84 46.155 117.76 46.325 ;
+      RECT 0 46.155 3.68 46.325 ;
+      RECT 116.84 43.435 117.76 43.605 ;
+      RECT 0 43.435 3.68 43.605 ;
+      RECT 114.08 40.715 117.76 40.885 ;
+      RECT 0 40.715 3.68 40.885 ;
+      RECT 114.08 37.995 117.76 38.165 ;
+      RECT 0 37.995 3.68 38.165 ;
+      RECT 114.08 35.275 117.76 35.445 ;
+      RECT 0 35.275 3.68 35.445 ;
+      RECT 114.08 32.555 117.76 32.725 ;
+      RECT 0 32.555 3.68 32.725 ;
+      RECT 116.84 29.835 117.76 30.005 ;
+      RECT 0 29.835 3.68 30.005 ;
+      RECT 116.84 27.115 117.76 27.285 ;
+      RECT 0 27.115 3.68 27.285 ;
+      RECT 116.84 24.395 117.76 24.565 ;
+      RECT 0 24.395 3.68 24.565 ;
+      RECT 116.84 21.675 117.76 21.845 ;
+      RECT 0 21.675 3.68 21.845 ;
+      RECT 116.84 18.955 117.76 19.125 ;
+      RECT 0 18.955 3.68 19.125 ;
+      RECT 116.84 16.235 117.76 16.405 ;
+      RECT 0 16.235 3.68 16.405 ;
+      RECT 114.08 13.515 117.76 13.685 ;
+      RECT 0 13.515 3.68 13.685 ;
+      RECT 114.08 10.795 117.76 10.965 ;
+      RECT 0 10.795 3.68 10.965 ;
+      RECT 114.08 8.075 117.76 8.245 ;
+      RECT 0 8.075 3.68 8.245 ;
+      RECT 114.08 5.355 117.76 5.525 ;
+      RECT 0 5.355 3.68 5.525 ;
+      RECT 114.08 2.635 117.76 2.805 ;
+      RECT 0 2.635 3.68 2.805 ;
+      RECT 0 -0.085 117.76 0.085 ;
+      POLYGON 91.83 97.75 91.83 86.87 117.59 86.87 117.59 0.17 0.17 0.17 0.17 86.87 25.93 86.87 25.93 97.75 ;
+    LAYER mcon ;
+      RECT 62.705 87.465 62.875 87.635 ;
+      RECT 62.49 86.445 62.66 86.615 ;
+      RECT 61.325 86.445 61.495 86.615 ;
+      RECT 59.405 86.445 59.575 86.615 ;
+      RECT 37.405 86.445 37.575 86.615 ;
+    LAYER via ;
+      RECT 80.885 97.845 81.035 97.995 ;
+      RECT 51.445 97.845 51.595 97.995 ;
+      RECT 87.095 87.475 87.245 87.625 ;
+      RECT 71.455 87.475 71.605 87.625 ;
+      RECT 62.715 87.475 62.865 87.625 ;
+      RECT 80.885 86.965 81.035 87.115 ;
+      RECT 51.445 86.965 51.595 87.115 ;
+      RECT 10.965 86.965 11.115 87.115 ;
+      RECT 63.635 86.455 63.785 86.605 ;
+      RECT 59.035 86.455 59.185 86.605 ;
+      RECT 50.295 86.455 50.445 86.605 ;
+      RECT 48.455 86.455 48.605 86.605 ;
+      RECT 36.955 86.455 37.105 86.605 ;
+      RECT 80.885 -0.075 81.035 0.075 ;
+      RECT 51.445 -0.075 51.595 0.075 ;
+      RECT 10.965 -0.075 11.115 0.075 ;
+    LAYER via2 ;
+      RECT 80.86 97.82 81.06 98.02 ;
+      RECT 51.42 97.82 51.62 98.02 ;
+      RECT 10.94 86.94 11.14 87.14 ;
+      RECT 116.51 28.12 116.71 28.32 ;
+      RECT 80.86 -0.1 81.06 0.1 ;
+      RECT 51.42 -0.1 51.62 0.1 ;
+      RECT 10.94 -0.1 11.14 0.1 ;
+    LAYER via3 ;
+      RECT 80.86 97.82 81.06 98.02 ;
+      RECT 51.42 97.82 51.62 98.02 ;
+      RECT 10.94 86.94 11.14 87.14 ;
+      RECT 80.86 -0.1 81.06 0.1 ;
+      RECT 51.42 -0.1 51.62 0.1 ;
+      RECT 10.94 -0.1 11.14 0.1 ;
+    LAYER OVERLAP ;
+      POLYGON 0 0 0 87.04 25.76 87.04 25.76 97.92 92 97.92 92 87.04 117.76 87.04 117.76 0 ;
+  END
+END sb_1__0_
+
+END LIBRARY
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef
new file mode 100644
index 0000000..aaf0267
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef
@@ -0,0 +1,2574 @@
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+
+UNITS
+  DATABASE MICRONS 1000 ;
+END UNITS
+
+MANUFACTURINGGRID 0.005 ;
+
+LAYER li1
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.17 ;
+END li1
+
+LAYER mcon
+  TYPE CUT ;
+END mcon
+
+LAYER met1
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.34 ;
+  WIDTH 0.14 ;
+END met1
+
+LAYER via
+  TYPE CUT ;
+END via
+
+LAYER met2
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.14 ;
+END met2
+
+LAYER via2
+  TYPE CUT ;
+END via2
+
+LAYER met3
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.68 ;
+  WIDTH 0.3 ;
+END met3
+
+LAYER via3
+  TYPE CUT ;
+END via3
+
+LAYER met4
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.92 ;
+  WIDTH 0.3 ;
+END met4
+
+LAYER via4
+  TYPE CUT ;
+END via4
+
+LAYER met5
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 3.4 ;
+  WIDTH 1.6 ;
+END met5
+
+LAYER nwell
+  TYPE MASTERSLICE ;
+END nwell
+
+LAYER pwell
+  TYPE MASTERSLICE ;
+END pwell
+
+LAYER OVERLAP
+  TYPE OVERLAP ;
+END OVERLAP
+
+VIA L1M1_PR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR
+
+VIA L1M1_PR_R
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_R
+
+VIA L1M1_PR_M
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_M
+
+VIA L1M1_PR_MR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR_MR
+
+VIA L1M1_PR_C
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.145 0.145 0.145 ;
+END L1M1_PR_C
+
+VIA M1M2_PR
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR
+
+VIA M1M2_PR_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_Enc
+
+VIA M1M2_PR_R
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_R
+
+VIA M1M2_PR_R_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_R_Enc
+
+VIA M1M2_PR_M
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIA M1M2_PR_M_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_M_Enc
+
+VIA M1M2_PR_MR
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIA M1M2_PR_MR_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_MR_Enc
+
+VIA M1M2_PR_C
+  LAYER met1 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIA M2M3_PR
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIA M2M3_PR_R
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIA M2M3_PR_M
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIA M2M3_PR_MR
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIA M2M3_PR_C
+  LAYER met2 ;
+    RECT -0.185 -0.185 0.185 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIA M3M4_PR
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIA M3M4_PR_R
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIA M3M4_PR_M
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIA M3M4_PR_MR
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIA M3M4_PR_C
+  LAYER met3 ;
+    RECT -0.19 -0.19 0.19 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIA M4M5_PR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIA M4M5_PR_R
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIA M4M5_PR_M
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIA M4M5_PR_MR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIA M4M5_PR_C
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+  CLASS CORE ;
+  SYMMETRY Y ;
+  SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+  CLASS CORE ;
+  SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+MACRO sb_1__1_
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 117.76 BY 108.8 ;
+  SYMMETRY X Y ;
+  PIN chany_top_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 63.79 108 64.09 108.8 ;
+    END
+  END chany_top_in[0]
+  PIN chany_top_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 84.34 108.315 84.48 108.8 ;
+    END
+  END chany_top_in[1]
+  PIN chany_top_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 83.42 108.315 83.56 108.8 ;
+    END
+  END chany_top_in[2]
+  PIN chany_top_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 73.91 108 74.21 108.8 ;
+    END
+  END chany_top_in[3]
+  PIN chany_top_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 81.58 108.315 81.72 108.8 ;
+    END
+  END chany_top_in[4]
+  PIN chany_top_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 56.43 108 56.73 108.8 ;
+    END
+  END chany_top_in[5]
+  PIN chany_top_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 55.36 108.315 55.5 108.8 ;
+    END
+  END chany_top_in[6]
+  PIN chany_top_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 60.11 108 60.41 108.8 ;
+    END
+  END chany_top_in[7]
+  PIN chany_top_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 85.26 108.315 85.4 108.8 ;
+    END
+  END chany_top_in[8]
+  PIN chany_top_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 88.02 108.315 88.16 108.8 ;
+    END
+  END chany_top_in[9]
+  PIN chany_top_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 82.5 108.315 82.64 108.8 ;
+    END
+  END chany_top_in[10]
+  PIN chany_top_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 88.94 108.315 89.08 108.8 ;
+    END
+  END chany_top_in[11]
+  PIN chany_top_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 67.47 108 67.77 108.8 ;
+    END
+  END chany_top_in[12]
+  PIN chany_top_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 67.32 108.315 67.46 108.8 ;
+    END
+  END chany_top_in[13]
+  PIN chany_top_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 52.75 108 53.05 108.8 ;
+    END
+  END chany_top_in[14]
+  PIN chany_top_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 58.27 108 58.57 108.8 ;
+    END
+  END chany_top_in[15]
+  PIN chany_top_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.58 108.315 58.72 108.8 ;
+    END
+  END chany_top_in[16]
+  PIN chany_top_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 54.59 108 54.89 108.8 ;
+    END
+  END chany_top_in[17]
+  PIN chany_top_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 64.1 108.315 64.24 108.8 ;
+    END
+  END chany_top_in[18]
+  PIN chany_top_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 69.31 108 69.61 108.8 ;
+    END
+  END chany_top_in[19]
+  PIN top_left_grid_pin_42_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.5 97.435 13.64 97.92 ;
+    END
+  END top_left_grid_pin_42_[0]
+  PIN top_left_grid_pin_43_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 11.66 97.435 11.8 97.92 ;
+    END
+  END top_left_grid_pin_43_[0]
+  PIN top_left_grid_pin_44_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 8.44 97.435 8.58 97.92 ;
+    END
+  END top_left_grid_pin_44_[0]
+  PIN top_left_grid_pin_45_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 12.58 97.435 12.72 97.92 ;
+    END
+  END top_left_grid_pin_45_[0]
+  PIN top_left_grid_pin_46_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 10.28 97.435 10.42 97.92 ;
+    END
+  END top_left_grid_pin_46_[0]
+  PIN top_left_grid_pin_47_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 4.3 97.435 4.44 97.92 ;
+    END
+  END top_left_grid_pin_47_[0]
+  PIN top_left_grid_pin_48_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 9.36 97.435 9.5 97.92 ;
+    END
+  END top_left_grid_pin_48_[0]
+  PIN top_left_grid_pin_49_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.06 97.435 7.2 97.92 ;
+    END
+  END top_left_grid_pin_49_[0]
+  PIN chanx_right_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 66.15 117.76 66.45 ;
+    END
+  END chanx_right_in[0]
+  PIN chanx_right_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 87.91 117.76 88.21 ;
+    END
+  END chanx_right_in[1]
+  PIN chanx_right_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 36.23 117.76 36.53 ;
+    END
+  END chanx_right_in[2]
+  PIN chanx_right_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 48.47 117.76 48.77 ;
+    END
+  END chanx_right_in[3]
+  PIN chanx_right_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 71.59 117.76 71.89 ;
+    END
+  END chanx_right_in[4]
+  PIN chanx_right_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 86.55 117.76 86.85 ;
+    END
+  END chanx_right_in[5]
+  PIN chanx_right_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 62.07 117.76 62.37 ;
+    END
+  END chanx_right_in[6]
+  PIN chanx_right_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 22.63 117.76 22.93 ;
+    END
+  END chanx_right_in[7]
+  PIN chanx_right_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 34.87 117.76 35.17 ;
+    END
+  END chanx_right_in[8]
+  PIN chanx_right_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 41.67 117.76 41.97 ;
+    END
+  END chanx_right_in[9]
+  PIN chanx_right_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 64.79 117.76 65.09 ;
+    END
+  END chanx_right_in[10]
+  PIN chanx_right_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 51.19 117.76 51.49 ;
+    END
+  END chanx_right_in[11]
+  PIN chanx_right_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 23.99 117.76 24.29 ;
+    END
+  END chanx_right_in[12]
+  PIN chanx_right_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 44.39 117.76 44.69 ;
+    END
+  END chanx_right_in[13]
+  PIN chanx_right_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 60.71 117.76 61.01 ;
+    END
+  END chanx_right_in[14]
+  PIN chanx_right_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 57.99 117.76 58.29 ;
+    END
+  END chanx_right_in[15]
+  PIN chanx_right_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 67.51 117.76 67.81 ;
+    END
+  END chanx_right_in[16]
+  PIN chanx_right_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 45.75 117.76 46.05 ;
+    END
+  END chanx_right_in[17]
+  PIN chanx_right_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 63.43 117.76 63.73 ;
+    END
+  END chanx_right_in[18]
+  PIN chanx_right_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 43.03 117.76 43.33 ;
+    END
+  END chanx_right_in[19]
+  PIN right_bottom_grid_pin_34_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 105.04 10.88 105.18 11.365 ;
+    END
+  END right_bottom_grid_pin_34_[0]
+  PIN right_bottom_grid_pin_35_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 111.48 10.88 111.62 11.365 ;
+    END
+  END right_bottom_grid_pin_35_[0]
+  PIN right_bottom_grid_pin_36_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 107.8 10.88 107.94 11.365 ;
+    END
+  END right_bottom_grid_pin_36_[0]
+  PIN right_bottom_grid_pin_37_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 112.86 10.88 113 11.365 ;
+    END
+  END right_bottom_grid_pin_37_[0]
+  PIN right_bottom_grid_pin_38_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 106.88 10.88 107.02 11.365 ;
+    END
+  END right_bottom_grid_pin_38_[0]
+  PIN right_bottom_grid_pin_39_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 104.12 10.88 104.26 11.365 ;
+    END
+  END right_bottom_grid_pin_39_[0]
+  PIN right_bottom_grid_pin_40_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 105.96 10.88 106.1 11.365 ;
+    END
+  END right_bottom_grid_pin_40_[0]
+  PIN right_bottom_grid_pin_41_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 108.72 10.88 108.86 11.365 ;
+    END
+  END right_bottom_grid_pin_41_[0]
+  PIN chany_bottom_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 89.4 0 89.54 0.485 ;
+    END
+  END chany_bottom_in[0]
+  PIN chany_bottom_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 52.75 0 53.05 0.8 ;
+    END
+  END chany_bottom_in[1]
+  PIN chany_bottom_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 84.34 0 84.48 0.485 ;
+    END
+  END chany_bottom_in[2]
+  PIN chany_bottom_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 80.2 0 80.34 0.485 ;
+    END
+  END chany_bottom_in[3]
+  PIN chany_bottom_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 81.58 0 81.72 0.485 ;
+    END
+  END chany_bottom_in[4]
+  PIN chany_bottom_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 39.26 0 39.4 0.485 ;
+    END
+  END chany_bottom_in[5]
+  PIN chany_bottom_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 74.83 0 75.13 0.8 ;
+    END
+  END chany_bottom_in[6]
+  PIN chany_bottom_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 34.66 0 34.8 0.485 ;
+    END
+  END chany_bottom_in[7]
+  PIN chany_bottom_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 79.28 0 79.42 0.485 ;
+    END
+  END chany_bottom_in[8]
+  PIN chany_bottom_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 66.86 0 67 0.485 ;
+    END
+  END chany_bottom_in[9]
+  PIN chany_bottom_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 76.98 0 77.12 0.485 ;
+    END
+  END chany_bottom_in[10]
+  PIN chany_bottom_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 75.14 0 75.28 0.485 ;
+    END
+  END chany_bottom_in[11]
+  PIN chany_bottom_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 86.18 0 86.32 0.485 ;
+    END
+  END chany_bottom_in[12]
+  PIN chany_bottom_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 40.18 0 40.32 0.485 ;
+    END
+  END chany_bottom_in[13]
+  PIN chany_bottom_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 32.82 0 32.96 0.485 ;
+    END
+  END chany_bottom_in[14]
+  PIN chany_bottom_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 36.5 0 36.64 0.485 ;
+    END
+  END chany_bottom_in[15]
+  PIN chany_bottom_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 82.5 0 82.64 0.485 ;
+    END
+  END chany_bottom_in[16]
+  PIN chany_bottom_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 57.66 0 57.8 0.485 ;
+    END
+  END chany_bottom_in[17]
+  PIN chany_bottom_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 62.26 0 62.4 0.485 ;
+    END
+  END chany_bottom_in[18]
+  PIN chany_bottom_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 55.82 0 55.96 0.485 ;
+    END
+  END chany_bottom_in[19]
+  PIN bottom_left_grid_pin_42_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 14.42 10.88 14.56 11.365 ;
+    END
+  END bottom_left_grid_pin_42_[0]
+  PIN bottom_left_grid_pin_43_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 15.34 10.88 15.48 11.365 ;
+    END
+  END bottom_left_grid_pin_43_[0]
+  PIN bottom_left_grid_pin_44_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 2.92 10.88 3.06 11.365 ;
+    END
+  END bottom_left_grid_pin_44_[0]
+  PIN bottom_left_grid_pin_45_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 10.28 10.88 10.42 11.365 ;
+    END
+  END bottom_left_grid_pin_45_[0]
+  PIN bottom_left_grid_pin_46_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 5.22 10.88 5.36 11.365 ;
+    END
+  END bottom_left_grid_pin_46_[0]
+  PIN bottom_left_grid_pin_47_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 4.3 10.88 4.44 11.365 ;
+    END
+  END bottom_left_grid_pin_47_[0]
+  PIN bottom_left_grid_pin_48_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.5 10.88 13.64 11.365 ;
+    END
+  END bottom_left_grid_pin_48_[0]
+  PIN bottom_left_grid_pin_49_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.06 10.88 7.2 11.365 ;
+    END
+  END bottom_left_grid_pin_49_[0]
+  PIN chanx_left_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 59.35 0.8 59.65 ;
+    END
+  END chanx_left_in[0]
+  PIN chanx_left_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 53.91 0.8 54.21 ;
+    END
+  END chanx_left_in[1]
+  PIN chanx_left_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 62.07 0.8 62.37 ;
+    END
+  END chanx_left_in[2]
+  PIN chanx_left_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 56.63 0.8 56.93 ;
+    END
+  END chanx_left_in[3]
+  PIN chanx_left_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 22.63 0.8 22.93 ;
+    END
+  END chanx_left_in[4]
+  PIN chanx_left_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 47.11 0.8 47.41 ;
+    END
+  END chanx_left_in[5]
+  PIN chanx_left_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 43.03 0.8 43.33 ;
+    END
+  END chanx_left_in[6]
+  PIN chanx_left_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 48.47 0.8 48.77 ;
+    END
+  END chanx_left_in[7]
+  PIN chanx_left_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 66.83 0.8 67.13 ;
+    END
+  END chanx_left_in[8]
+  PIN chanx_left_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 72.27 0.8 72.57 ;
+    END
+  END chanx_left_in[9]
+  PIN chanx_left_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 41.67 0.8 41.97 ;
+    END
+  END chanx_left_in[10]
+  PIN chanx_left_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 57.99 0.8 58.29 ;
+    END
+  END chanx_left_in[11]
+  PIN chanx_left_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 60.71 0.8 61.01 ;
+    END
+  END chanx_left_in[12]
+  PIN chanx_left_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 87.91 0.8 88.21 ;
+    END
+  END chanx_left_in[13]
+  PIN chanx_left_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 45.75 0.8 46.05 ;
+    END
+  END chanx_left_in[14]
+  PIN chanx_left_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 69.55 0.8 69.85 ;
+    END
+  END chanx_left_in[15]
+  PIN chanx_left_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 63.43 0.8 63.73 ;
+    END
+  END chanx_left_in[16]
+  PIN chanx_left_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 70.91 0.8 71.21 ;
+    END
+  END chanx_left_in[17]
+  PIN chanx_left_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 85.19 0.8 85.49 ;
+    END
+  END chanx_left_in[18]
+  PIN chanx_left_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 68.19 0.8 68.49 ;
+    END
+  END chanx_left_in[19]
+  PIN left_bottom_grid_pin_34_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 6.75 10.88 7.05 11.68 ;
+    END
+  END left_bottom_grid_pin_34_[0]
+  PIN left_bottom_grid_pin_35_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 8.59 10.88 8.89 11.68 ;
+    END
+  END left_bottom_grid_pin_35_[0]
+  PIN left_bottom_grid_pin_36_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 8.9 10.88 9.04 11.365 ;
+    END
+  END left_bottom_grid_pin_36_[0]
+  PIN left_bottom_grid_pin_37_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.98 10.88 8.12 11.365 ;
+    END
+  END left_bottom_grid_pin_37_[0]
+  PIN left_bottom_grid_pin_38_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 11.66 10.88 11.8 11.365 ;
+    END
+  END left_bottom_grid_pin_38_[0]
+  PIN left_bottom_grid_pin_39_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 12.58 10.88 12.72 11.365 ;
+    END
+  END left_bottom_grid_pin_39_[0]
+  PIN left_bottom_grid_pin_40_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 28.22 0 28.36 0.485 ;
+    END
+  END left_bottom_grid_pin_40_[0]
+  PIN left_bottom_grid_pin_41_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 6.14 10.88 6.28 11.365 ;
+    END
+  END left_bottom_grid_pin_41_[0]
+  PIN ccff_head[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 29.43 117.76 29.73 ;
+    END
+  END ccff_head[0]
+  PIN chany_top_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 71 108.315 71.14 108.8 ;
+    END
+  END chany_top_out[0]
+  PIN chany_top_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 77.44 108.315 77.58 108.8 ;
+    END
+  END chany_top_out[1]
+  PIN chany_top_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 74.68 108.315 74.82 108.8 ;
+    END
+  END chany_top_out[2]
+  PIN chany_top_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 78.36 108.315 78.5 108.8 ;
+    END
+  END chany_top_out[3]
+  PIN chany_top_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 39.26 108.315 39.4 108.8 ;
+    END
+  END chany_top_out[4]
+  PIN chany_top_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 60.42 108.315 60.56 108.8 ;
+    END
+  END chany_top_out[5]
+  PIN chany_top_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 54.44 108.315 54.58 108.8 ;
+    END
+  END chany_top_out[6]
+  PIN chany_top_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 50.76 108.315 50.9 108.8 ;
+    END
+  END chany_top_out[7]
+  PIN chany_top_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 66.4 108.315 66.54 108.8 ;
+    END
+  END chany_top_out[8]
+  PIN chany_top_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 79.28 108.315 79.42 108.8 ;
+    END
+  END chany_top_out[9]
+  PIN chany_top_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 57.66 108.315 57.8 108.8 ;
+    END
+  END chany_top_out[10]
+  PIN chany_top_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.18 108.315 63.32 108.8 ;
+    END
+  END chany_top_out[11]
+  PIN chany_top_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 69.16 108.315 69.3 108.8 ;
+    END
+  END chany_top_out[12]
+  PIN chany_top_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 76.52 108.315 76.66 108.8 ;
+    END
+  END chany_top_out[13]
+  PIN chany_top_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.14 108.315 52.28 108.8 ;
+    END
+  END chany_top_out[14]
+  PIN chany_top_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 65.02 108.315 65.16 108.8 ;
+    END
+  END chany_top_out[15]
+  PIN chany_top_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.06 108.315 53.2 108.8 ;
+    END
+  END chany_top_out[16]
+  PIN chany_top_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 70.08 108.315 70.22 108.8 ;
+    END
+  END chany_top_out[17]
+  PIN chany_top_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.5 108.315 59.64 108.8 ;
+    END
+  END chany_top_out[18]
+  PIN chany_top_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 75.6 108.315 75.74 108.8 ;
+    END
+  END chany_top_out[19]
+  PIN chanx_right_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 70.23 117.76 70.53 ;
+    END
+  END chanx_right_out[0]
+  PIN chanx_right_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 72.95 117.76 73.25 ;
+    END
+  END chanx_right_out[1]
+  PIN chanx_right_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 25.35 117.76 25.65 ;
+    END
+  END chanx_right_out[2]
+  PIN chanx_right_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 49.83 117.76 50.13 ;
+    END
+  END chanx_right_out[3]
+  PIN chanx_right_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 56.63 117.76 56.93 ;
+    END
+  END chanx_right_out[4]
+  PIN chanx_right_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 53.91 117.76 54.21 ;
+    END
+  END chanx_right_out[5]
+  PIN chanx_right_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 85.19 117.76 85.49 ;
+    END
+  END chanx_right_out[6]
+  PIN chanx_right_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 33.51 117.76 33.81 ;
+    END
+  END chanx_right_out[7]
+  PIN chanx_right_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 32.15 117.76 32.45 ;
+    END
+  END chanx_right_out[8]
+  PIN chanx_right_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 55.27 117.76 55.57 ;
+    END
+  END chanx_right_out[9]
+  PIN chanx_right_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 26.71 117.76 27.01 ;
+    END
+  END chanx_right_out[10]
+  PIN chanx_right_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 52.55 117.76 52.85 ;
+    END
+  END chanx_right_out[11]
+  PIN chanx_right_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 15.83 117.76 16.13 ;
+    END
+  END chanx_right_out[12]
+  PIN chanx_right_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 47.11 117.76 47.41 ;
+    END
+  END chanx_right_out[13]
+  PIN chanx_right_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 30.79 117.76 31.09 ;
+    END
+  END chanx_right_out[14]
+  PIN chanx_right_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 68.87 117.76 69.17 ;
+    END
+  END chanx_right_out[15]
+  PIN chanx_right_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 14.47 117.76 14.77 ;
+    END
+  END chanx_right_out[16]
+  PIN chanx_right_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 59.35 117.76 59.65 ;
+    END
+  END chanx_right_out[17]
+  PIN chanx_right_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 28.07 117.76 28.37 ;
+    END
+  END chanx_right_out[18]
+  PIN chanx_right_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 89.27 117.76 89.57 ;
+    END
+  END chanx_right_out[19]
+  PIN chany_bottom_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 65.94 0 66.08 0.485 ;
+    END
+  END chany_bottom_out[0]
+  PIN chany_bottom_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 85.26 0 85.4 0.485 ;
+    END
+  END chany_bottom_out[1]
+  PIN chany_bottom_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 35.58 0 35.72 0.485 ;
+    END
+  END chany_bottom_out[2]
+  PIN chany_bottom_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 83.42 0 83.56 0.485 ;
+    END
+  END chany_bottom_out[3]
+  PIN chany_bottom_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 38.34 0 38.48 0.485 ;
+    END
+  END chany_bottom_out[4]
+  PIN chany_bottom_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 73.3 0 73.44 0.485 ;
+    END
+  END chany_bottom_out[5]
+  PIN chany_bottom_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 76.06 0 76.2 0.485 ;
+    END
+  END chany_bottom_out[6]
+  PIN chany_bottom_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 37.42 0 37.56 0.485 ;
+    END
+  END chany_bottom_out[7]
+  PIN chany_bottom_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 60.42 0 60.56 0.485 ;
+    END
+  END chany_bottom_out[8]
+  PIN chany_bottom_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 64.1 0 64.24 0.485 ;
+    END
+  END chany_bottom_out[9]
+  PIN chany_bottom_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 67.78 0 67.92 0.485 ;
+    END
+  END chany_bottom_out[10]
+  PIN chany_bottom_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 74.22 0 74.36 0.485 ;
+    END
+  END chany_bottom_out[11]
+  PIN chany_bottom_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.5 0 59.64 0.485 ;
+    END
+  END chany_bottom_out[12]
+  PIN chany_bottom_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 54.9 0 55.04 0.485 ;
+    END
+  END chany_bottom_out[13]
+  PIN chany_bottom_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.98 0 54.12 0.485 ;
+    END
+  END chany_bottom_out[14]
+  PIN chany_bottom_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 65.02 0 65.16 0.485 ;
+    END
+  END chany_bottom_out[15]
+  PIN chany_bottom_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.58 0 58.72 0.485 ;
+    END
+  END chany_bottom_out[16]
+  PIN chany_bottom_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.18 0 63.32 0.485 ;
+    END
+  END chany_bottom_out[17]
+  PIN chany_bottom_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.14 0 52.28 0.485 ;
+    END
+  END chany_bottom_out[18]
+  PIN chany_bottom_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.06 0 53.2 0.485 ;
+    END
+  END chany_bottom_out[19]
+  PIN chanx_left_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 23.99 0.8 24.29 ;
+    END
+  END chanx_left_out[0]
+  PIN chanx_left_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 64.79 0.8 65.09 ;
+    END
+  END chanx_left_out[1]
+  PIN chanx_left_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 34.87 0.8 35.17 ;
+    END
+  END chanx_left_out[2]
+  PIN chanx_left_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 55.27 0.8 55.57 ;
+    END
+  END chanx_left_out[3]
+  PIN chanx_left_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 15.83 0.8 16.13 ;
+    END
+  END chanx_left_out[4]
+  PIN chanx_left_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 44.39 0.8 44.69 ;
+    END
+  END chanx_left_out[5]
+  PIN chanx_left_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 33.51 0.8 33.81 ;
+    END
+  END chanx_left_out[6]
+  PIN chanx_left_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 25.35 0.8 25.65 ;
+    END
+  END chanx_left_out[7]
+  PIN chanx_left_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 30.79 0.8 31.09 ;
+    END
+  END chanx_left_out[8]
+  PIN chanx_left_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 49.83 0.8 50.13 ;
+    END
+  END chanx_left_out[9]
+  PIN chanx_left_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 36.23 0.8 36.53 ;
+    END
+  END chanx_left_out[10]
+  PIN chanx_left_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 52.55 0.8 52.85 ;
+    END
+  END chanx_left_out[11]
+  PIN chanx_left_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 17.19 0.8 17.49 ;
+    END
+  END chanx_left_out[12]
+  PIN chanx_left_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 86.55 0.8 86.85 ;
+    END
+  END chanx_left_out[13]
+  PIN chanx_left_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 37.59 0.8 37.89 ;
+    END
+  END chanx_left_out[14]
+  PIN chanx_left_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 28.07 0.8 28.37 ;
+    END
+  END chanx_left_out[15]
+  PIN chanx_left_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 14.47 0.8 14.77 ;
+    END
+  END chanx_left_out[16]
+  PIN chanx_left_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 51.19 0.8 51.49 ;
+    END
+  END chanx_left_out[17]
+  PIN chanx_left_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 32.15 0.8 32.45 ;
+    END
+  END chanx_left_out[18]
+  PIN chanx_left_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 26.71 0.8 27.01 ;
+    END
+  END chanx_left_out[19]
+  PIN ccff_tail[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 29.43 0.8 29.73 ;
+    END
+  END ccff_tail[0]
+  PIN Test_en_S_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 78.36 0 78.5 0.485 ;
+    END
+  END Test_en_S_in
+  PIN Test_en_N_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 73.76 108.315 73.9 108.8 ;
+    END
+  END Test_en_N_out
+  PIN prog_clk_0_N_in
+    DIRECTION INPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met2 ;
+        RECT 38.34 108.315 38.48 108.8 ;
+    END
+  END prog_clk_0_N_in
+  PIN prog_clk_1_N_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.34 108.315 61.48 108.8 ;
+    END
+  END prog_clk_1_N_in
+  PIN prog_clk_1_S_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.34 0 61.48 0.485 ;
+    END
+  END prog_clk_1_S_in
+  PIN prog_clk_1_E_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 37.59 117.76 37.89 ;
+    END
+  END prog_clk_1_E_out
+  PIN prog_clk_1_W_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 40.31 0.8 40.61 ;
+    END
+  END prog_clk_1_W_out
+  PIN prog_clk_2_N_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 72.38 108.315 72.52 108.8 ;
+    END
+  END prog_clk_2_N_in
+  PIN prog_clk_2_E_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 82.47 117.76 82.77 ;
+    END
+  END prog_clk_2_E_in
+  PIN prog_clk_2_S_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 70.23 0 70.53 0.8 ;
+    END
+  END prog_clk_2_S_in
+  PIN prog_clk_2_W_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 74.99 0.8 75.29 ;
+    END
+  END prog_clk_2_W_in
+  PIN prog_clk_2_W_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 73.63 0.8 73.93 ;
+    END
+  END prog_clk_2_W_out
+  PIN prog_clk_2_S_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 69.16 0 69.3 0.485 ;
+    END
+  END prog_clk_2_S_out
+  PIN prog_clk_2_N_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 87.1 108.315 87.24 108.8 ;
+    END
+  END prog_clk_2_N_out
+  PIN prog_clk_2_E_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 74.31 117.76 74.61 ;
+    END
+  END prog_clk_2_E_out
+  PIN prog_clk_3_W_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 76.35 0.8 76.65 ;
+    END
+  END prog_clk_3_W_in
+  PIN prog_clk_3_E_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 77.03 117.76 77.33 ;
+    END
+  END prog_clk_3_E_in
+  PIN prog_clk_3_S_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 87.56 0 87.7 0.485 ;
+    END
+  END prog_clk_3_S_in
+  PIN prog_clk_3_N_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 72.07 108 72.37 108.8 ;
+    END
+  END prog_clk_3_N_in
+  PIN prog_clk_3_E_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 81.11 117.76 81.41 ;
+    END
+  END prog_clk_3_E_out
+  PIN prog_clk_3_W_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 81.79 0.8 82.09 ;
+    END
+  END prog_clk_3_W_out
+  PIN prog_clk_3_N_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 86.18 108.315 86.32 108.8 ;
+    END
+  END prog_clk_3_N_out
+  PIN prog_clk_3_S_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 70.08 0 70.22 0.485 ;
+    END
+  END prog_clk_3_S_out
+  PIN clk_1_N_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 56.74 108.315 56.88 108.8 ;
+    END
+  END clk_1_N_in
+  PIN clk_1_S_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 56.74 0 56.88 0.485 ;
+    END
+  END clk_1_S_in
+  PIN clk_1_E_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 38.95 117.76 39.25 ;
+    END
+  END clk_1_E_out
+  PIN clk_1_W_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 38.95 0.8 39.25 ;
+    END
+  END clk_1_W_out
+  PIN clk_2_N_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 61.95 108 62.25 108.8 ;
+    END
+  END clk_2_N_in
+  PIN clk_2_E_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 83.83 117.76 84.13 ;
+    END
+  END clk_2_E_in
+  PIN clk_2_S_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 72.07 0 72.37 0.8 ;
+    END
+  END clk_2_S_in
+  PIN clk_2_W_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 77.71 0.8 78.01 ;
+    END
+  END clk_2_W_in
+  PIN clk_2_W_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 83.83 0.8 84.13 ;
+    END
+  END clk_2_W_out
+  PIN clk_2_S_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 71 0 71.14 0.485 ;
+    END
+  END clk_2_S_out
+  PIN clk_2_N_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 80.2 108.315 80.34 108.8 ;
+    END
+  END clk_2_N_out
+  PIN clk_2_E_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 75.67 117.76 75.97 ;
+    END
+  END clk_2_E_out
+  PIN clk_3_W_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 79.07 0.8 79.37 ;
+    END
+  END clk_3_W_in
+  PIN clk_3_E_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 79.75 117.76 80.05 ;
+    END
+  END clk_3_E_in
+  PIN clk_3_S_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 88.48 0 88.62 0.485 ;
+    END
+  END clk_3_S_in
+  PIN clk_3_N_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 62.26 108.315 62.4 108.8 ;
+    END
+  END clk_3_N_in
+  PIN clk_3_E_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 78.39 117.76 78.69 ;
+    END
+  END clk_3_E_out
+  PIN clk_3_W_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 80.43 0.8 80.73 ;
+    END
+  END clk_3_W_out
+  PIN clk_3_N_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 68.24 108.315 68.38 108.8 ;
+    END
+  END clk_3_N_out
+  PIN clk_3_S_out
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 72.38 0 72.52 0.485 ;
+    END
+  END clk_3_S_out
+  PIN VDD
+    DIRECTION INPUT ;
+    USE POWER ;
+    PORT
+      LAYER met1 ;
+        RECT 25.76 2.48 26.24 2.96 ;
+        RECT 91.52 2.48 92 2.96 ;
+        RECT 25.76 7.92 26.24 8.4 ;
+        RECT 91.52 7.92 92 8.4 ;
+        RECT 0 13.36 0.48 13.84 ;
+        RECT 117.28 13.36 117.76 13.84 ;
+        RECT 0 18.8 0.48 19.28 ;
+        RECT 117.28 18.8 117.76 19.28 ;
+        RECT 0 24.24 0.48 24.72 ;
+        RECT 117.28 24.24 117.76 24.72 ;
+        RECT 0 29.68 0.48 30.16 ;
+        RECT 117.28 29.68 117.76 30.16 ;
+        RECT 0 35.12 0.48 35.6 ;
+        RECT 117.28 35.12 117.76 35.6 ;
+        RECT 0 40.56 0.48 41.04 ;
+        RECT 117.28 40.56 117.76 41.04 ;
+        RECT 0 46 0.48 46.48 ;
+        RECT 117.28 46 117.76 46.48 ;
+        RECT 0 51.44 0.48 51.92 ;
+        RECT 117.28 51.44 117.76 51.92 ;
+        RECT 0 56.88 0.48 57.36 ;
+        RECT 117.28 56.88 117.76 57.36 ;
+        RECT 0 62.32 0.48 62.8 ;
+        RECT 117.28 62.32 117.76 62.8 ;
+        RECT 0 67.76 0.48 68.24 ;
+        RECT 117.28 67.76 117.76 68.24 ;
+        RECT 0 73.2 0.48 73.68 ;
+        RECT 117.28 73.2 117.76 73.68 ;
+        RECT 0 78.64 0.48 79.12 ;
+        RECT 117.28 78.64 117.76 79.12 ;
+        RECT 0 84.08 0.48 84.56 ;
+        RECT 117.28 84.08 117.76 84.56 ;
+        RECT 0 89.52 0.48 90 ;
+        RECT 117.28 89.52 117.76 90 ;
+        RECT 0 94.96 0.48 95.44 ;
+        RECT 117.28 94.96 117.76 95.44 ;
+        RECT 25.76 100.4 26.24 100.88 ;
+        RECT 91.52 100.4 92 100.88 ;
+        RECT 25.76 105.84 26.24 106.32 ;
+        RECT 91.52 105.84 92 106.32 ;
+      LAYER met5 ;
+        RECT 0 22.2 3.2 25.4 ;
+        RECT 114.56 22.2 117.76 25.4 ;
+        RECT 0 63 3.2 66.2 ;
+        RECT 114.56 63 117.76 66.2 ;
+      LAYER met4 ;
+        RECT 36.5 0 37.1 0.6 ;
+        RECT 65.94 0 66.54 0.6 ;
+        RECT 106.42 10.88 107.02 11.48 ;
+        RECT 106.42 97.32 107.02 97.92 ;
+        RECT 36.5 108.2 37.1 108.8 ;
+        RECT 65.94 108.2 66.54 108.8 ;
+    END
+  END VDD
+  PIN VSS
+    DIRECTION INPUT ;
+    USE GROUND ;
+    PORT
+      LAYER met1 ;
+        RECT 25.76 0 45.4 0.24 ;
+        RECT 46.6 0 92 0.24 ;
+        RECT 25.76 5.2 26.24 5.68 ;
+        RECT 91.52 5.2 92 5.68 ;
+        RECT 0 10.64 45.4 11.12 ;
+        RECT 46.6 10.64 95.08 11.12 ;
+        RECT 96.28 10.88 117.76 11.12 ;
+        RECT 0 16.08 0.48 16.56 ;
+        RECT 117.28 16.08 117.76 16.56 ;
+        RECT 0 21.52 0.48 22 ;
+        RECT 117.28 21.52 117.76 22 ;
+        RECT 0 26.96 0.48 27.44 ;
+        RECT 117.28 26.96 117.76 27.44 ;
+        RECT 0 32.4 0.48 32.88 ;
+        RECT 117.28 32.4 117.76 32.88 ;
+        RECT 0 37.84 0.48 38.32 ;
+        RECT 117.28 37.84 117.76 38.32 ;
+        RECT 0 43.28 0.48 43.76 ;
+        RECT 117.28 43.28 117.76 43.76 ;
+        RECT 0 48.72 0.48 49.2 ;
+        RECT 117.28 48.72 117.76 49.2 ;
+        RECT 0 54.16 0.48 54.64 ;
+        RECT 117.28 54.16 117.76 54.64 ;
+        RECT 0 59.6 0.48 60.08 ;
+        RECT 117.28 59.6 117.76 60.08 ;
+        RECT 0 65.04 0.48 65.52 ;
+        RECT 117.28 65.04 117.76 65.52 ;
+        RECT 0 70.48 0.48 70.96 ;
+        RECT 117.28 70.48 117.76 70.96 ;
+        RECT 0 75.92 0.48 76.4 ;
+        RECT 117.28 75.92 117.76 76.4 ;
+        RECT 0 81.36 0.48 81.84 ;
+        RECT 117.28 81.36 117.76 81.84 ;
+        RECT 0 86.8 0.48 87.28 ;
+        RECT 117.28 86.8 117.76 87.28 ;
+        RECT 0 92.24 0.48 92.72 ;
+        RECT 117.28 92.24 117.76 92.72 ;
+        RECT 96.28 97.68 117.76 97.92 ;
+        RECT 0 97.68 45.4 98.16 ;
+        RECT 46.6 97.68 95.08 98.16 ;
+        RECT 25.76 103.12 26.24 103.6 ;
+        RECT 91.52 103.12 92 103.6 ;
+        RECT 25.76 108.56 45.4 108.8 ;
+        RECT 46.6 108.56 92 108.8 ;
+      LAYER met5 ;
+        RECT 0 42.6 3.2 45.8 ;
+        RECT 114.56 42.6 117.76 45.8 ;
+        RECT 0 83.4 3.2 86.6 ;
+        RECT 114.56 83.4 117.76 86.6 ;
+      LAYER met4 ;
+        RECT 51.22 0 51.82 0.6 ;
+        RECT 80.66 0 81.26 0.6 ;
+        RECT 10.74 10.88 11.34 11.48 ;
+        RECT 10.74 97.32 11.34 97.92 ;
+        RECT 51.22 108.2 51.82 108.8 ;
+        RECT 80.66 108.2 81.26 108.8 ;
+    END
+  END VSS
+  OBS
+    LAYER met4 ;
+      POLYGON 91.69 36.53 91.69 11.385 91.705 11.385 91.705 11.055 91.375 11.055 91.375 11.385 91.39 11.385 91.39 36.53 ;
+      POLYGON 91.6 108.4 91.6 97.52 106.02 97.52 106.02 96.92 107.42 96.92 107.42 97.52 117.36 97.52 117.36 11.28 107.42 11.28 107.42 11.88 106.02 11.88 106.02 11.28 91.6 11.28 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 75.53 0.4 75.53 1.2 74.43 1.2 74.43 0.4 72.77 0.4 72.77 1.2 71.67 1.2 71.67 0.4 70.93 0.4 70.93 1.2 69.83 1.2 69.83 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 53.45 0.4 53.45 1.2 52.35 1.2 52.35 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 26.16 0.4 26.16 11.28 11.74 11.28 11.74 11.88 10.34 11.88 10.34 11.28 9.29 11.28 9.29 12.08 8.19 12.08 8.19 11.28 7.45 11.28 7.45 12.08 6.35 12.08 6.35 11.28 0.4 11.28 0.4 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 26.16 97.52 26.16 108.4 36.1 108.4 36.1 107.8 37.5 107.8 37.5 108.4 50.82 108.4 50.82 107.8 52.22 107.8 52.22 108.4 52.35 108.4 52.35 107.6 53.45 107.6 53.45 108.4 54.19 108.4 54.19 107.6 55.29 107.6 55.29 108.4 56.03 108.4 56.03 107.6 57.13 107.6 57.13 108.4 57.87 108.4 57.87 107.6 58.97 107.6 58.97 108.4 59.71 108.4 59.71 107.6 60.81 107.6 60.81 108.4 61.55 108.4 61.55 107.6 62.65 107.6 62.65 108.4 63.39 108.4 63.39 107.6 64.49 107.6 64.49 108.4 65.54 108.4 65.54 107.8 66.94 107.8 66.94 108.4 67.07 108.4 67.07 107.6 68.17 107.6 68.17 108.4 68.91 108.4 68.91 107.6 70.01 107.6 70.01 108.4 71.67 108.4 71.67 107.6 72.77 107.6 72.77 108.4 73.51 108.4 73.51 107.6 74.61 107.6 74.61 108.4 80.26 108.4 80.26 107.8 81.66 107.8 81.66 108.4 ;
+    LAYER met2 ;
+      RECT 80.82 108.615 81.1 108.985 ;
+      RECT 51.38 108.615 51.66 108.985 ;
+      RECT 10.9 97.735 11.18 98.105 ;
+      RECT 10.9 10.695 11.18 11.065 ;
+      RECT 80.82 -0.185 81.1 0.185 ;
+      RECT 51.38 -0.185 51.66 0.185 ;
+      POLYGON 91.72 108.52 91.72 97.64 117.48 97.64 117.48 11.16 113.28 11.16 113.28 11.645 112.58 11.645 112.58 11.16 111.9 11.16 111.9 11.645 111.2 11.645 111.2 11.16 109.14 11.16 109.14 11.645 108.44 11.645 108.44 11.16 108.22 11.16 108.22 11.645 107.52 11.645 107.52 11.16 107.3 11.16 107.3 11.645 106.6 11.645 106.6 11.16 106.38 11.16 106.38 11.645 105.68 11.645 105.68 11.16 105.46 11.16 105.46 11.645 104.76 11.645 104.76 11.16 104.54 11.16 104.54 11.645 103.84 11.645 103.84 11.16 91.72 11.16 91.72 0.28 89.82 0.28 89.82 0.765 89.12 0.765 89.12 0.28 88.9 0.28 88.9 0.765 88.2 0.765 88.2 0.28 87.98 0.28 87.98 0.765 87.28 0.765 87.28 0.28 86.6 0.28 86.6 0.765 85.9 0.765 85.9 0.28 85.68 0.28 85.68 0.765 84.98 0.765 84.98 0.28 84.76 0.28 84.76 0.765 84.06 0.765 84.06 0.28 83.84 0.28 83.84 0.765 83.14 0.765 83.14 0.28 82.92 0.28 82.92 0.765 82.22 0.765 82.22 0.28 82 0.28 82 0.765 81.3 0.765 81.3 0.28 80.62 0.28 80.62 0.765 79.92 0.765 79.92 0.28 79.7 0.28 79.7 0.765 79 0.765 79 0.28 78.78 0.28 78.78 0.765 78.08 0.765 78.08 0.28 77.4 0.28 77.4 0.765 76.7 0.765 76.7 0.28 76.48 0.28 76.48 0.765 75.78 0.765 75.78 0.28 75.56 0.28 75.56 0.765 74.86 0.765 74.86 0.28 74.64 0.28 74.64 0.765 73.94 0.765 73.94 0.28 73.72 0.28 73.72 0.765 73.02 0.765 73.02 0.28 72.8 0.28 72.8 0.765 72.1 0.765 72.1 0.28 71.42 0.28 71.42 0.765 70.72 0.765 70.72 0.28 70.5 0.28 70.5 0.765 69.8 0.765 69.8 0.28 69.58 0.28 69.58 0.765 68.88 0.765 68.88 0.28 68.2 0.28 68.2 0.765 67.5 0.765 67.5 0.28 67.28 0.28 67.28 0.765 66.58 0.765 66.58 0.28 66.36 0.28 66.36 0.765 65.66 0.765 65.66 0.28 65.44 0.28 65.44 0.765 64.74 0.765 64.74 0.28 64.52 0.28 64.52 0.765 63.82 0.765 63.82 0.28 63.6 0.28 63.6 0.765 62.9 0.765 62.9 0.28 62.68 0.28 62.68 0.765 61.98 0.765 61.98 0.28 61.76 0.28 61.76 0.765 61.06 0.765 61.06 0.28 60.84 0.28 60.84 0.765 60.14 0.765 60.14 0.28 59.92 0.28 59.92 0.765 59.22 0.765 59.22 0.28 59 0.28 59 0.765 58.3 0.765 58.3 0.28 58.08 0.28 58.08 0.765 57.38 0.765 57.38 0.28 57.16 0.28 57.16 0.765 56.46 0.765 56.46 0.28 56.24 0.28 56.24 0.765 55.54 0.765 55.54 0.28 55.32 0.28 55.32 0.765 54.62 0.765 54.62 0.28 54.4 0.28 54.4 0.765 53.7 0.765 53.7 0.28 53.48 0.28 53.48 0.765 52.78 0.765 52.78 0.28 52.56 0.28 52.56 0.765 51.86 0.765 51.86 0.28 40.6 0.28 40.6 0.765 39.9 0.765 39.9 0.28 39.68 0.28 39.68 0.765 38.98 0.765 38.98 0.28 38.76 0.28 38.76 0.765 38.06 0.765 38.06 0.28 37.84 0.28 37.84 0.765 37.14 0.765 37.14 0.28 36.92 0.28 36.92 0.765 36.22 0.765 36.22 0.28 36 0.28 36 0.765 35.3 0.765 35.3 0.28 35.08 0.28 35.08 0.765 34.38 0.765 34.38 0.28 33.24 0.28 33.24 0.765 32.54 0.765 32.54 0.28 28.64 0.28 28.64 0.765 27.94 0.765 27.94 0.28 26.04 0.28 26.04 11.16 15.76 11.16 15.76 11.645 15.06 11.645 15.06 11.16 14.84 11.16 14.84 11.645 14.14 11.645 14.14 11.16 13.92 11.16 13.92 11.645 13.22 11.645 13.22 11.16 13 11.16 13 11.645 12.3 11.645 12.3 11.16 12.08 11.16 12.08 11.645 11.38 11.645 11.38 11.16 10.7 11.16 10.7 11.645 10 11.645 10 11.16 9.32 11.16 9.32 11.645 8.62 11.645 8.62 11.16 8.4 11.16 8.4 11.645 7.7 11.645 7.7 11.16 7.48 11.16 7.48 11.645 6.78 11.645 6.78 11.16 6.56 11.16 6.56 11.645 5.86 11.645 5.86 11.16 5.64 11.16 5.64 11.645 4.94 11.645 4.94 11.16 4.72 11.16 4.72 11.645 4.02 11.645 4.02 11.16 3.34 11.16 3.34 11.645 2.64 11.645 2.64 11.16 0.28 11.16 0.28 97.64 4.02 97.64 4.02 97.155 4.72 97.155 4.72 97.64 6.78 97.64 6.78 97.155 7.48 97.155 7.48 97.64 8.16 97.64 8.16 97.155 8.86 97.155 8.86 97.64 9.08 97.64 9.08 97.155 9.78 97.155 9.78 97.64 10 97.64 10 97.155 10.7 97.155 10.7 97.64 11.38 97.64 11.38 97.155 12.08 97.155 12.08 97.64 12.3 97.64 12.3 97.155 13 97.155 13 97.64 13.22 97.64 13.22 97.155 13.92 97.155 13.92 97.64 26.04 97.64 26.04 108.52 38.06 108.52 38.06 108.035 38.76 108.035 38.76 108.52 38.98 108.52 38.98 108.035 39.68 108.035 39.68 108.52 50.48 108.52 50.48 108.035 51.18 108.035 51.18 108.52 51.86 108.52 51.86 108.035 52.56 108.035 52.56 108.52 52.78 108.52 52.78 108.035 53.48 108.035 53.48 108.52 54.16 108.52 54.16 108.035 54.86 108.035 54.86 108.52 55.08 108.52 55.08 108.035 55.78 108.035 55.78 108.52 56.46 108.52 56.46 108.035 57.16 108.035 57.16 108.52 57.38 108.52 57.38 108.035 58.08 108.035 58.08 108.52 58.3 108.52 58.3 108.035 59 108.035 59 108.52 59.22 108.52 59.22 108.035 59.92 108.035 59.92 108.52 60.14 108.52 60.14 108.035 60.84 108.035 60.84 108.52 61.06 108.52 61.06 108.035 61.76 108.035 61.76 108.52 61.98 108.52 61.98 108.035 62.68 108.035 62.68 108.52 62.9 108.52 62.9 108.035 63.6 108.035 63.6 108.52 63.82 108.52 63.82 108.035 64.52 108.035 64.52 108.52 64.74 108.52 64.74 108.035 65.44 108.035 65.44 108.52 66.12 108.52 66.12 108.035 66.82 108.035 66.82 108.52 67.04 108.52 67.04 108.035 67.74 108.035 67.74 108.52 67.96 108.52 67.96 108.035 68.66 108.035 68.66 108.52 68.88 108.52 68.88 108.035 69.58 108.035 69.58 108.52 69.8 108.52 69.8 108.035 70.5 108.035 70.5 108.52 70.72 108.52 70.72 108.035 71.42 108.035 71.42 108.52 72.1 108.52 72.1 108.035 72.8 108.035 72.8 108.52 73.48 108.52 73.48 108.035 74.18 108.035 74.18 108.52 74.4 108.52 74.4 108.035 75.1 108.035 75.1 108.52 75.32 108.52 75.32 108.035 76.02 108.035 76.02 108.52 76.24 108.52 76.24 108.035 76.94 108.035 76.94 108.52 77.16 108.52 77.16 108.035 77.86 108.035 77.86 108.52 78.08 108.52 78.08 108.035 78.78 108.035 78.78 108.52 79 108.52 79 108.035 79.7 108.035 79.7 108.52 79.92 108.52 79.92 108.035 80.62 108.035 80.62 108.52 81.3 108.52 81.3 108.035 82 108.035 82 108.52 82.22 108.52 82.22 108.035 82.92 108.035 82.92 108.52 83.14 108.52 83.14 108.035 83.84 108.035 83.84 108.52 84.06 108.52 84.06 108.035 84.76 108.035 84.76 108.52 84.98 108.52 84.98 108.035 85.68 108.035 85.68 108.52 85.9 108.52 85.9 108.035 86.6 108.035 86.6 108.52 86.82 108.52 86.82 108.035 87.52 108.035 87.52 108.52 87.74 108.52 87.74 108.035 88.44 108.035 88.44 108.52 88.66 108.52 88.66 108.035 89.36 108.035 89.36 108.52 ;
+    LAYER met3 ;
+      POLYGON 81.125 108.965 81.125 108.96 81.34 108.96 81.34 108.64 81.125 108.64 81.125 108.635 80.795 108.635 80.795 108.64 80.58 108.64 80.58 108.96 80.795 108.96 80.795 108.965 ;
+      POLYGON 51.685 108.965 51.685 108.96 51.9 108.96 51.9 108.64 51.685 108.64 51.685 108.635 51.355 108.635 51.355 108.64 51.14 108.64 51.14 108.96 51.355 108.96 51.355 108.965 ;
+      POLYGON 11.205 98.085 11.205 98.08 11.42 98.08 11.42 97.76 11.205 97.76 11.205 97.755 10.875 97.755 10.875 97.76 10.66 97.76 10.66 98.08 10.875 98.08 10.875 98.085 ;
+      POLYGON 26.37 12.05 26.37 11.37 34.88 11.37 34.88 11.07 26.07 11.07 26.07 12.05 ;
+      POLYGON 91.73 11.38 91.73 11.06 91.35 11.06 91.35 11.07 89.32 11.07 89.32 11.37 91.35 11.37 91.35 11.38 ;
+      POLYGON 11.205 11.045 11.205 11.04 11.42 11.04 11.42 10.72 11.205 10.72 11.205 10.715 10.875 10.715 10.875 10.72 10.66 10.72 10.66 11.04 10.875 11.04 10.875 11.045 ;
+      POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ;
+      POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ;
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+      RECT 10.965 97.845 11.115 97.995 ;
+      RECT 75.595 97.335 75.745 97.485 ;
+      RECT 71.455 97.335 71.605 97.485 ;
+      RECT 61.795 97.335 61.945 97.485 ;
+      RECT 26.835 97.335 26.985 97.485 ;
+      RECT 25.915 97.335 26.065 97.485 ;
+      RECT 78.815 11.315 78.965 11.465 ;
+      RECT 75.135 11.315 75.285 11.465 ;
+      RECT 64.555 11.315 64.705 11.465 ;
+      RECT 52.135 11.315 52.285 11.465 ;
+      RECT 50.755 11.315 50.905 11.465 ;
+      RECT 40.175 11.315 40.325 11.465 ;
+      RECT 33.735 11.315 33.885 11.465 ;
+      RECT 30.515 11.315 30.665 11.465 ;
+      RECT 80.885 10.805 81.035 10.955 ;
+      RECT 51.445 10.805 51.595 10.955 ;
+      RECT 10.965 10.805 11.115 10.955 ;
+      RECT 43.855 10.295 44.005 10.445 ;
+      RECT 37.415 10.295 37.565 10.445 ;
+      RECT 34.655 10.295 34.805 10.445 ;
+      RECT 33.735 10.295 33.885 10.445 ;
+      RECT 80.885 -0.075 81.035 0.075 ;
+      RECT 51.445 -0.075 51.595 0.075 ;
+    LAYER via2 ;
+      RECT 80.86 108.7 81.06 108.9 ;
+      RECT 51.42 108.7 51.62 108.9 ;
+      RECT 10.94 97.82 11.14 98.02 ;
+      RECT 1.05 72.32 1.25 72.52 ;
+      RECT 116.51 44.44 116.71 44.64 ;
+      RECT 10.94 10.78 11.14 10.98 ;
+      RECT 80.86 -0.1 81.06 0.1 ;
+      RECT 51.42 -0.1 51.62 0.1 ;
+    LAYER via3 ;
+      RECT 80.86 108.7 81.06 108.9 ;
+      RECT 51.42 108.7 51.62 108.9 ;
+      RECT 10.94 97.82 11.14 98.02 ;
+      RECT 91.44 11.12 91.64 11.32 ;
+      RECT 10.94 10.78 11.14 10.98 ;
+      RECT 80.86 -0.1 81.06 0.1 ;
+      RECT 51.42 -0.1 51.62 0.1 ;
+    LAYER OVERLAP ;
+      POLYGON 25.76 0 25.76 10.88 0 10.88 0 97.92 25.76 97.92 25.76 108.8 92 108.8 92 97.92 117.76 97.92 117.76 10.88 92 10.88 92 0 ;
+  END
+END sb_1__1_
+
+END LIBRARY
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef
new file mode 100644
index 0000000..dc65317
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef
@@ -0,0 +1,1862 @@
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+
+UNITS
+  DATABASE MICRONS 1000 ;
+END UNITS
+
+MANUFACTURINGGRID 0.005 ;
+
+LAYER li1
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.17 ;
+END li1
+
+LAYER mcon
+  TYPE CUT ;
+END mcon
+
+LAYER met1
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.34 ;
+  WIDTH 0.14 ;
+END met1
+
+LAYER via
+  TYPE CUT ;
+END via
+
+LAYER met2
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.14 ;
+END met2
+
+LAYER via2
+  TYPE CUT ;
+END via2
+
+LAYER met3
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.68 ;
+  WIDTH 0.3 ;
+END met3
+
+LAYER via3
+  TYPE CUT ;
+END via3
+
+LAYER met4
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.92 ;
+  WIDTH 0.3 ;
+END met4
+
+LAYER via4
+  TYPE CUT ;
+END via4
+
+LAYER met5
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 3.4 ;
+  WIDTH 1.6 ;
+END met5
+
+LAYER nwell
+  TYPE MASTERSLICE ;
+END nwell
+
+LAYER pwell
+  TYPE MASTERSLICE ;
+END pwell
+
+LAYER OVERLAP
+  TYPE OVERLAP ;
+END OVERLAP
+
+VIA L1M1_PR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR
+
+VIA L1M1_PR_R
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_R
+
+VIA L1M1_PR_M
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_M
+
+VIA L1M1_PR_MR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR_MR
+
+VIA L1M1_PR_C
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.145 0.145 0.145 ;
+END L1M1_PR_C
+
+VIA M1M2_PR
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR
+
+VIA M1M2_PR_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_Enc
+
+VIA M1M2_PR_R
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_R
+
+VIA M1M2_PR_R_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_R_Enc
+
+VIA M1M2_PR_M
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIA M1M2_PR_M_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_M_Enc
+
+VIA M1M2_PR_MR
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIA M1M2_PR_MR_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_MR_Enc
+
+VIA M1M2_PR_C
+  LAYER met1 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIA M2M3_PR
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIA M2M3_PR_R
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIA M2M3_PR_M
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIA M2M3_PR_MR
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIA M2M3_PR_C
+  LAYER met2 ;
+    RECT -0.185 -0.185 0.185 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIA M3M4_PR
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIA M3M4_PR_R
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIA M3M4_PR_M
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIA M3M4_PR_MR
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIA M3M4_PR_C
+  LAYER met3 ;
+    RECT -0.19 -0.19 0.19 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIA M4M5_PR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIA M4M5_PR_R
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIA M4M5_PR_M
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIA M4M5_PR_MR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIA M4M5_PR_C
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+  CLASS CORE ;
+  SYMMETRY Y ;
+  SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+  CLASS CORE ;
+  SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+MACRO sb_1__2_
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 117.76 BY 97.92 ;
+  SYMMETRY X Y ;
+  PIN chanx_right_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 90.63 117.76 90.93 ;
+    END
+  END chanx_right_in[0]
+  PIN chanx_right_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 74.99 117.76 75.29 ;
+    END
+  END chanx_right_in[1]
+  PIN chanx_right_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 65.47 117.76 65.77 ;
+    END
+  END chanx_right_in[2]
+  PIN chanx_right_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 76.35 117.76 76.65 ;
+    END
+  END chanx_right_in[3]
+  PIN chanx_right_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 32.15 117.76 32.45 ;
+    END
+  END chanx_right_in[4]
+  PIN chanx_right_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 60.03 117.76 60.33 ;
+    END
+  END chanx_right_in[5]
+  PIN chanx_right_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 51.19 117.76 51.49 ;
+    END
+  END chanx_right_in[6]
+  PIN chanx_right_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 45.07 117.76 45.37 ;
+    END
+  END chanx_right_in[7]
+  PIN chanx_right_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 64.11 117.76 64.41 ;
+    END
+  END chanx_right_in[8]
+  PIN chanx_right_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 29.43 117.76 29.73 ;
+    END
+  END chanx_right_in[9]
+  PIN chanx_right_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 69.55 117.76 69.85 ;
+    END
+  END chanx_right_in[10]
+  PIN chanx_right_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 73.63 117.76 73.93 ;
+    END
+  END chanx_right_in[11]
+  PIN chanx_right_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 35.55 117.76 35.85 ;
+    END
+  END chanx_right_in[12]
+  PIN chanx_right_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 19.23 117.76 19.53 ;
+    END
+  END chanx_right_in[13]
+  PIN chanx_right_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 36.91 117.76 37.21 ;
+    END
+  END chanx_right_in[14]
+  PIN chanx_right_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 40.99 117.76 41.29 ;
+    END
+  END chanx_right_in[15]
+  PIN chanx_right_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 57.31 117.76 57.61 ;
+    END
+  END chanx_right_in[16]
+  PIN chanx_right_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 70.91 117.76 71.21 ;
+    END
+  END chanx_right_in[17]
+  PIN chanx_right_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 49.83 117.76 50.13 ;
+    END
+  END chanx_right_in[18]
+  PIN chanx_right_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 68.19 117.76 68.49 ;
+    END
+  END chanx_right_in[19]
+  PIN right_top_grid_pin_1_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 43.71 117.76 44.01 ;
+    END
+  END right_top_grid_pin_1_[0]
+  PIN right_bottom_grid_pin_34_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 105.04 10.88 105.18 11.365 ;
+    END
+  END right_bottom_grid_pin_34_[0]
+  PIN right_bottom_grid_pin_35_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 111.48 10.88 111.62 11.365 ;
+    END
+  END right_bottom_grid_pin_35_[0]
+  PIN right_bottom_grid_pin_36_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 107.8 10.88 107.94 11.365 ;
+    END
+  END right_bottom_grid_pin_36_[0]
+  PIN right_bottom_grid_pin_37_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 112.86 10.88 113 11.365 ;
+    END
+  END right_bottom_grid_pin_37_[0]
+  PIN right_bottom_grid_pin_38_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 106.88 10.88 107.02 11.365 ;
+    END
+  END right_bottom_grid_pin_38_[0]
+  PIN right_bottom_grid_pin_39_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 104.12 10.88 104.26 11.365 ;
+    END
+  END right_bottom_grid_pin_39_[0]
+  PIN right_bottom_grid_pin_40_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 105.96 10.88 106.1 11.365 ;
+    END
+  END right_bottom_grid_pin_40_[0]
+  PIN right_bottom_grid_pin_41_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 108.72 10.88 108.86 11.365 ;
+    END
+  END right_bottom_grid_pin_41_[0]
+  PIN chany_bottom_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 89.4 0 89.54 0.485 ;
+    END
+  END chany_bottom_in[0]
+  PIN chany_bottom_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 52.75 0 53.05 0.8 ;
+    END
+  END chany_bottom_in[1]
+  PIN chany_bottom_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 84.34 0 84.48 0.485 ;
+    END
+  END chany_bottom_in[2]
+  PIN chany_bottom_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 80.2 0 80.34 0.485 ;
+    END
+  END chany_bottom_in[3]
+  PIN chany_bottom_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 81.58 0 81.72 0.485 ;
+    END
+  END chany_bottom_in[4]
+  PIN chany_bottom_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 39.26 0 39.4 0.485 ;
+    END
+  END chany_bottom_in[5]
+  PIN chany_bottom_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 74.83 0 75.13 0.8 ;
+    END
+  END chany_bottom_in[6]
+  PIN chany_bottom_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 34.66 0 34.8 0.485 ;
+    END
+  END chany_bottom_in[7]
+  PIN chany_bottom_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 79.28 0 79.42 0.485 ;
+    END
+  END chany_bottom_in[8]
+  PIN chany_bottom_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 66.86 0 67 0.485 ;
+    END
+  END chany_bottom_in[9]
+  PIN chany_bottom_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 76.98 0 77.12 0.485 ;
+    END
+  END chany_bottom_in[10]
+  PIN chany_bottom_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 75.14 0 75.28 0.485 ;
+    END
+  END chany_bottom_in[11]
+  PIN chany_bottom_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 86.18 0 86.32 0.485 ;
+    END
+  END chany_bottom_in[12]
+  PIN chany_bottom_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 40.18 0 40.32 0.485 ;
+    END
+  END chany_bottom_in[13]
+  PIN chany_bottom_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 32.82 0 32.96 0.485 ;
+    END
+  END chany_bottom_in[14]
+  PIN chany_bottom_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 36.5 0 36.64 0.485 ;
+    END
+  END chany_bottom_in[15]
+  PIN chany_bottom_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 82.5 0 82.64 0.485 ;
+    END
+  END chany_bottom_in[16]
+  PIN chany_bottom_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 57.66 0 57.8 0.485 ;
+    END
+  END chany_bottom_in[17]
+  PIN chany_bottom_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 62.26 0 62.4 0.485 ;
+    END
+  END chany_bottom_in[18]
+  PIN chany_bottom_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 55.82 0 55.96 0.485 ;
+    END
+  END chany_bottom_in[19]
+  PIN bottom_left_grid_pin_42_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 14.42 10.88 14.56 11.365 ;
+    END
+  END bottom_left_grid_pin_42_[0]
+  PIN bottom_left_grid_pin_43_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 15.34 10.88 15.48 11.365 ;
+    END
+  END bottom_left_grid_pin_43_[0]
+  PIN bottom_left_grid_pin_44_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 2.92 10.88 3.06 11.365 ;
+    END
+  END bottom_left_grid_pin_44_[0]
+  PIN bottom_left_grid_pin_45_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 10.28 10.88 10.42 11.365 ;
+    END
+  END bottom_left_grid_pin_45_[0]
+  PIN bottom_left_grid_pin_46_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 5.22 10.88 5.36 11.365 ;
+    END
+  END bottom_left_grid_pin_46_[0]
+  PIN bottom_left_grid_pin_47_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 4.3 10.88 4.44 11.365 ;
+    END
+  END bottom_left_grid_pin_47_[0]
+  PIN bottom_left_grid_pin_48_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.5 10.88 13.64 11.365 ;
+    END
+  END bottom_left_grid_pin_48_[0]
+  PIN bottom_left_grid_pin_49_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.06 10.88 7.2 11.365 ;
+    END
+  END bottom_left_grid_pin_49_[0]
+  PIN chanx_left_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 66.83 0.8 67.13 ;
+    END
+  END chanx_left_in[0]
+  PIN chanx_left_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 52.55 0.8 52.85 ;
+    END
+  END chanx_left_in[1]
+  PIN chanx_left_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 60.71 0.8 61.01 ;
+    END
+  END chanx_left_in[2]
+  PIN chanx_left_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 45.75 0.8 46.05 ;
+    END
+  END chanx_left_in[3]
+  PIN chanx_left_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 48.47 0.8 48.77 ;
+    END
+  END chanx_left_in[4]
+  PIN chanx_left_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 56.63 0.8 56.93 ;
+    END
+  END chanx_left_in[5]
+  PIN chanx_left_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 68.19 0.8 68.49 ;
+    END
+  END chanx_left_in[6]
+  PIN chanx_left_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 65.47 0.8 65.77 ;
+    END
+  END chanx_left_in[7]
+  PIN chanx_left_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 49.83 0.8 50.13 ;
+    END
+  END chanx_left_in[8]
+  PIN chanx_left_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 59.35 0.8 59.65 ;
+    END
+  END chanx_left_in[9]
+  PIN chanx_left_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 64.11 0.8 64.41 ;
+    END
+  END chanx_left_in[10]
+  PIN chanx_left_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 47.11 0.8 47.41 ;
+    END
+  END chanx_left_in[11]
+  PIN chanx_left_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 55.27 0.8 55.57 ;
+    END
+  END chanx_left_in[12]
+  PIN chanx_left_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 23.31 0.8 23.61 ;
+    END
+  END chanx_left_in[13]
+  PIN chanx_left_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 57.99 0.8 58.29 ;
+    END
+  END chanx_left_in[14]
+  PIN chanx_left_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 40.31 0.8 40.61 ;
+    END
+  END chanx_left_in[15]
+  PIN chanx_left_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 37.59 0.8 37.89 ;
+    END
+  END chanx_left_in[16]
+  PIN chanx_left_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 27.39 0.8 27.69 ;
+    END
+  END chanx_left_in[17]
+  PIN chanx_left_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 74.31 0.8 74.61 ;
+    END
+  END chanx_left_in[18]
+  PIN chanx_left_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 32.83 0.8 33.13 ;
+    END
+  END chanx_left_in[19]
+  PIN left_top_grid_pin_1_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 20.59 0.8 20.89 ;
+    END
+  END left_top_grid_pin_1_[0]
+  PIN left_bottom_grid_pin_34_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 6.75 10.88 7.05 11.68 ;
+    END
+  END left_bottom_grid_pin_34_[0]
+  PIN left_bottom_grid_pin_35_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 8.59 10.88 8.89 11.68 ;
+    END
+  END left_bottom_grid_pin_35_[0]
+  PIN left_bottom_grid_pin_36_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 8.9 10.88 9.04 11.365 ;
+    END
+  END left_bottom_grid_pin_36_[0]
+  PIN left_bottom_grid_pin_37_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.98 10.88 8.12 11.365 ;
+    END
+  END left_bottom_grid_pin_37_[0]
+  PIN left_bottom_grid_pin_38_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 11.66 10.88 11.8 11.365 ;
+    END
+  END left_bottom_grid_pin_38_[0]
+  PIN left_bottom_grid_pin_39_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 12.58 10.88 12.72 11.365 ;
+    END
+  END left_bottom_grid_pin_39_[0]
+  PIN left_bottom_grid_pin_40_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 28.22 0 28.36 0.485 ;
+    END
+  END left_bottom_grid_pin_40_[0]
+  PIN left_bottom_grid_pin_41_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 6.14 10.88 6.28 11.365 ;
+    END
+  END left_bottom_grid_pin_41_[0]
+  PIN ccff_head[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 61.39 117.76 61.69 ;
+    END
+  END ccff_head[0]
+  PIN chanx_right_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 17.87 117.76 18.17 ;
+    END
+  END chanx_right_out[0]
+  PIN chanx_right_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 46.43 117.76 46.73 ;
+    END
+  END chanx_right_out[1]
+  PIN chanx_right_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 39.63 117.76 39.93 ;
+    END
+  END chanx_right_out[2]
+  PIN chanx_right_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 25.35 117.76 25.65 ;
+    END
+  END chanx_right_out[3]
+  PIN chanx_right_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 47.79 117.76 48.09 ;
+    END
+  END chanx_right_out[4]
+  PIN chanx_right_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 28.07 117.76 28.37 ;
+    END
+  END chanx_right_out[5]
+  PIN chanx_right_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 58.67 117.76 58.97 ;
+    END
+  END chanx_right_out[6]
+  PIN chanx_right_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 23.99 117.76 24.29 ;
+    END
+  END chanx_right_out[7]
+  PIN chanx_right_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 42.35 117.76 42.65 ;
+    END
+  END chanx_right_out[8]
+  PIN chanx_right_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 30.79 117.76 31.09 ;
+    END
+  END chanx_right_out[9]
+  PIN chanx_right_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 53.23 117.76 53.53 ;
+    END
+  END chanx_right_out[10]
+  PIN chanx_right_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 26.71 117.76 27.01 ;
+    END
+  END chanx_right_out[11]
+  PIN chanx_right_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 72.27 117.76 72.57 ;
+    END
+  END chanx_right_out[12]
+  PIN chanx_right_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 20.59 117.76 20.89 ;
+    END
+  END chanx_right_out[13]
+  PIN chanx_right_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 55.95 117.76 56.25 ;
+    END
+  END chanx_right_out[14]
+  PIN chanx_right_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 33.51 117.76 33.81 ;
+    END
+  END chanx_right_out[15]
+  PIN chanx_right_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 66.83 117.76 67.13 ;
+    END
+  END chanx_right_out[16]
+  PIN chanx_right_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 38.27 117.76 38.57 ;
+    END
+  END chanx_right_out[17]
+  PIN chanx_right_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 54.59 117.76 54.89 ;
+    END
+  END chanx_right_out[18]
+  PIN chanx_right_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 22.63 117.76 22.93 ;
+    END
+  END chanx_right_out[19]
+  PIN chany_bottom_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 65.94 0 66.08 0.485 ;
+    END
+  END chany_bottom_out[0]
+  PIN chany_bottom_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 85.26 0 85.4 0.485 ;
+    END
+  END chany_bottom_out[1]
+  PIN chany_bottom_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 35.58 0 35.72 0.485 ;
+    END
+  END chany_bottom_out[2]
+  PIN chany_bottom_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 83.42 0 83.56 0.485 ;
+    END
+  END chany_bottom_out[3]
+  PIN chany_bottom_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 38.34 0 38.48 0.485 ;
+    END
+  END chany_bottom_out[4]
+  PIN chany_bottom_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 73.3 0 73.44 0.485 ;
+    END
+  END chany_bottom_out[5]
+  PIN chany_bottom_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 76.06 0 76.2 0.485 ;
+    END
+  END chany_bottom_out[6]
+  PIN chany_bottom_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 37.42 0 37.56 0.485 ;
+    END
+  END chany_bottom_out[7]
+  PIN chany_bottom_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 60.42 0 60.56 0.485 ;
+    END
+  END chany_bottom_out[8]
+  PIN chany_bottom_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 64.1 0 64.24 0.485 ;
+    END
+  END chany_bottom_out[9]
+  PIN chany_bottom_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 67.78 0 67.92 0.485 ;
+    END
+  END chany_bottom_out[10]
+  PIN chany_bottom_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 74.22 0 74.36 0.485 ;
+    END
+  END chany_bottom_out[11]
+  PIN chany_bottom_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.5 0 59.64 0.485 ;
+    END
+  END chany_bottom_out[12]
+  PIN chany_bottom_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 54.9 0 55.04 0.485 ;
+    END
+  END chany_bottom_out[13]
+  PIN chany_bottom_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.98 0 54.12 0.485 ;
+    END
+  END chany_bottom_out[14]
+  PIN chany_bottom_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 65.02 0 65.16 0.485 ;
+    END
+  END chany_bottom_out[15]
+  PIN chany_bottom_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.58 0 58.72 0.485 ;
+    END
+  END chany_bottom_out[16]
+  PIN chany_bottom_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.18 0 63.32 0.485 ;
+    END
+  END chany_bottom_out[17]
+  PIN chany_bottom_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.14 0 52.28 0.485 ;
+    END
+  END chany_bottom_out[18]
+  PIN chany_bottom_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.06 0 53.2 0.485 ;
+    END
+  END chany_bottom_out[19]
+  PIN chanx_left_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 72.95 0.8 73.25 ;
+    END
+  END chanx_left_out[0]
+  PIN chanx_left_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 71.59 0.8 71.89 ;
+    END
+  END chanx_left_out[1]
+  PIN chanx_left_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 90.63 0.8 90.93 ;
+    END
+  END chanx_left_out[2]
+  PIN chanx_left_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 69.55 0.8 69.85 ;
+    END
+  END chanx_left_out[3]
+  PIN chanx_left_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 41.67 0.8 41.97 ;
+    END
+  END chanx_left_out[4]
+  PIN chanx_left_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 29.43 0.8 29.73 ;
+    END
+  END chanx_left_out[5]
+  PIN chanx_left_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 51.19 0.8 51.49 ;
+    END
+  END chanx_left_out[6]
+  PIN chanx_left_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 26.03 0.8 26.33 ;
+    END
+  END chanx_left_out[7]
+  PIN chanx_left_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 31.47 0.8 31.77 ;
+    END
+  END chanx_left_out[8]
+  PIN chanx_left_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 34.19 0.8 34.49 ;
+    END
+  END chanx_left_out[9]
+  PIN chanx_left_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 44.39 0.8 44.69 ;
+    END
+  END chanx_left_out[10]
+  PIN chanx_left_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 21.95 0.8 22.25 ;
+    END
+  END chanx_left_out[11]
+  PIN chanx_left_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 38.95 0.8 39.25 ;
+    END
+  END chanx_left_out[12]
+  PIN chanx_left_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 15.83 0.8 16.13 ;
+    END
+  END chanx_left_out[13]
+  PIN chanx_left_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 53.91 0.8 54.21 ;
+    END
+  END chanx_left_out[14]
+  PIN chanx_left_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 24.67 0.8 24.97 ;
+    END
+  END chanx_left_out[15]
+  PIN chanx_left_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 17.19 0.8 17.49 ;
+    END
+  END chanx_left_out[16]
+  PIN chanx_left_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 18.55 0.8 18.85 ;
+    END
+  END chanx_left_out[17]
+  PIN chanx_left_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 62.75 0.8 63.05 ;
+    END
+  END chanx_left_out[18]
+  PIN chanx_left_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 35.55 0.8 35.85 ;
+    END
+  END chanx_left_out[19]
+  PIN ccff_tail[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 43.03 0.8 43.33 ;
+    END
+  END ccff_tail[0]
+  PIN SC_IN_BOT
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 14.47 0.8 14.77 ;
+    END
+  END SC_IN_BOT
+  PIN SC_OUT_BOT
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 116.96 14.47 117.76 14.77 ;
+    END
+  END SC_OUT_BOT
+  PIN prog_clk_0_S_in
+    DIRECTION INPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met2 ;
+        RECT 33.74 0 33.88 0.485 ;
+    END
+  END prog_clk_0_S_in
+  PIN VDD
+    DIRECTION INPUT ;
+    USE POWER ;
+    PORT
+      LAYER met1 ;
+        RECT 25.76 2.48 26.24 2.96 ;
+        RECT 91.52 2.48 92 2.96 ;
+        RECT 25.76 7.92 26.24 8.4 ;
+        RECT 91.52 7.92 92 8.4 ;
+        RECT 0 13.36 0.48 13.84 ;
+        RECT 117.28 13.36 117.76 13.84 ;
+        RECT 0 18.8 0.48 19.28 ;
+        RECT 117.28 18.8 117.76 19.28 ;
+        RECT 0 24.24 0.48 24.72 ;
+        RECT 117.28 24.24 117.76 24.72 ;
+        RECT 0 29.68 0.48 30.16 ;
+        RECT 117.28 29.68 117.76 30.16 ;
+        RECT 0 35.12 0.48 35.6 ;
+        RECT 117.28 35.12 117.76 35.6 ;
+        RECT 0 40.56 0.48 41.04 ;
+        RECT 117.28 40.56 117.76 41.04 ;
+        RECT 0 46 0.48 46.48 ;
+        RECT 117.28 46 117.76 46.48 ;
+        RECT 0 51.44 0.48 51.92 ;
+        RECT 117.28 51.44 117.76 51.92 ;
+        RECT 0 56.88 0.48 57.36 ;
+        RECT 117.28 56.88 117.76 57.36 ;
+        RECT 0 62.32 0.48 62.8 ;
+        RECT 117.28 62.32 117.76 62.8 ;
+        RECT 0 67.76 0.48 68.24 ;
+        RECT 117.28 67.76 117.76 68.24 ;
+        RECT 0 73.2 0.48 73.68 ;
+        RECT 117.28 73.2 117.76 73.68 ;
+        RECT 0 78.64 0.48 79.12 ;
+        RECT 117.28 78.64 117.76 79.12 ;
+        RECT 0 84.08 0.48 84.56 ;
+        RECT 117.28 84.08 117.76 84.56 ;
+        RECT 0 89.52 0.48 90 ;
+        RECT 117.28 89.52 117.76 90 ;
+        RECT 0 94.96 0.48 95.44 ;
+        RECT 117.28 94.96 117.76 95.44 ;
+      LAYER met5 ;
+        RECT 0 22.2 3.2 25.4 ;
+        RECT 114.56 22.2 117.76 25.4 ;
+        RECT 0 63 3.2 66.2 ;
+        RECT 114.56 63 117.76 66.2 ;
+      LAYER met4 ;
+        RECT 36.5 0 37.1 0.6 ;
+        RECT 65.94 0 66.54 0.6 ;
+        RECT 106.42 10.88 107.02 11.48 ;
+        RECT 36.5 97.32 37.1 97.92 ;
+        RECT 65.94 97.32 66.54 97.92 ;
+        RECT 106.42 97.32 107.02 97.92 ;
+    END
+  END VDD
+  PIN VSS
+    DIRECTION INPUT ;
+    USE GROUND ;
+    PORT
+      LAYER met1 ;
+        RECT 25.76 0 45.4 0.24 ;
+        RECT 46.6 0 92 0.24 ;
+        RECT 25.76 5.2 26.24 5.68 ;
+        RECT 91.52 5.2 92 5.68 ;
+        RECT 0 10.64 45.4 11.12 ;
+        RECT 46.6 10.64 95.08 11.12 ;
+        RECT 96.28 10.88 117.76 11.12 ;
+        RECT 0 16.08 0.48 16.56 ;
+        RECT 117.28 16.08 117.76 16.56 ;
+        RECT 0 21.52 0.48 22 ;
+        RECT 117.28 21.52 117.76 22 ;
+        RECT 0 26.96 0.48 27.44 ;
+        RECT 117.28 26.96 117.76 27.44 ;
+        RECT 0 32.4 0.48 32.88 ;
+        RECT 117.28 32.4 117.76 32.88 ;
+        RECT 0 37.84 0.48 38.32 ;
+        RECT 117.28 37.84 117.76 38.32 ;
+        RECT 0 43.28 0.48 43.76 ;
+        RECT 117.28 43.28 117.76 43.76 ;
+        RECT 0 48.72 0.48 49.2 ;
+        RECT 117.28 48.72 117.76 49.2 ;
+        RECT 0 54.16 0.48 54.64 ;
+        RECT 117.28 54.16 117.76 54.64 ;
+        RECT 0 59.6 0.48 60.08 ;
+        RECT 117.28 59.6 117.76 60.08 ;
+        RECT 0 65.04 0.48 65.52 ;
+        RECT 117.28 65.04 117.76 65.52 ;
+        RECT 0 70.48 0.48 70.96 ;
+        RECT 117.28 70.48 117.76 70.96 ;
+        RECT 0 75.92 0.48 76.4 ;
+        RECT 117.28 75.92 117.76 76.4 ;
+        RECT 0 81.36 0.48 81.84 ;
+        RECT 117.28 81.36 117.76 81.84 ;
+        RECT 0 86.8 0.48 87.28 ;
+        RECT 117.28 86.8 117.76 87.28 ;
+        RECT 0 92.24 0.48 92.72 ;
+        RECT 117.28 92.24 117.76 92.72 ;
+        RECT 0 97.68 45.4 97.92 ;
+        RECT 96.28 97.68 117.76 97.92 ;
+      LAYER met5 ;
+        RECT 0 42.6 3.2 45.8 ;
+        RECT 114.56 42.6 117.76 45.8 ;
+        RECT 0 83.4 3.2 86.6 ;
+        RECT 114.56 83.4 117.76 86.6 ;
+      LAYER met4 ;
+        RECT 51.22 0 51.82 0.6 ;
+        RECT 80.66 0 81.26 0.6 ;
+        RECT 10.74 10.88 11.34 11.48 ;
+        RECT 10.74 97.32 11.34 97.92 ;
+        RECT 51.22 97.32 51.82 97.92 ;
+        RECT 80.66 97.32 81.26 97.92 ;
+    END
+  END VSS
+  OBS
+    LAYER met3 ;
+      POLYGON 81.125 98.085 81.125 98.08 81.34 98.08 81.34 97.76 81.125 97.76 81.125 97.755 80.795 97.755 80.795 97.76 80.58 97.76 80.58 98.08 80.795 98.08 80.795 98.085 ;
+      POLYGON 51.685 98.085 51.685 98.08 51.9 98.08 51.9 97.76 51.685 97.76 51.685 97.755 51.355 97.755 51.355 97.76 51.14 97.76 51.14 98.08 51.355 98.08 51.355 98.085 ;
+      POLYGON 11.205 98.085 11.205 98.08 11.42 98.08 11.42 97.76 11.205 97.76 11.205 97.755 10.875 97.755 10.875 97.76 10.66 97.76 10.66 98.08 10.875 98.08 10.875 98.085 ;
+      POLYGON 108.94 12.73 108.94 11.07 90.47 11.07 90.47 11.37 108.64 11.37 108.64 12.73 ;
+      POLYGON 11.205 11.045 11.205 11.04 11.42 11.04 11.42 10.72 11.205 10.72 11.205 10.715 10.875 10.715 10.875 10.72 10.66 10.72 10.66 11.04 10.875 11.04 10.875 11.045 ;
+      POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ;
+      POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ;
+      POLYGON 117.36 97.52 117.36 91.33 116.56 91.33 116.56 90.23 117.36 90.23 117.36 77.05 116.56 77.05 116.56 75.95 117.36 75.95 117.36 75.69 116.56 75.69 116.56 74.59 117.36 74.59 117.36 74.33 116.56 74.33 116.56 73.23 117.36 73.23 117.36 72.97 116.56 72.97 116.56 71.87 117.36 71.87 117.36 71.61 116.56 71.61 116.56 70.51 117.36 70.51 117.36 70.25 116.56 70.25 116.56 69.15 117.36 69.15 117.36 68.89 116.56 68.89 116.56 67.79 117.36 67.79 117.36 67.53 116.56 67.53 116.56 66.43 117.36 66.43 117.36 66.17 116.56 66.17 116.56 65.07 117.36 65.07 117.36 64.81 116.56 64.81 116.56 63.71 117.36 63.71 117.36 62.09 116.56 62.09 116.56 60.99 117.36 60.99 117.36 60.73 116.56 60.73 116.56 59.63 117.36 59.63 117.36 59.37 116.56 59.37 116.56 58.27 117.36 58.27 117.36 58.01 116.56 58.01 116.56 56.91 117.36 56.91 117.36 56.65 116.56 56.65 116.56 55.55 117.36 55.55 117.36 55.29 116.56 55.29 116.56 54.19 117.36 54.19 117.36 53.93 116.56 53.93 116.56 52.83 117.36 52.83 117.36 51.89 116.56 51.89 116.56 50.79 117.36 50.79 117.36 50.53 116.56 50.53 116.56 49.43 117.36 49.43 117.36 48.49 116.56 48.49 116.56 47.39 117.36 47.39 117.36 47.13 116.56 47.13 116.56 46.03 117.36 46.03 117.36 45.77 116.56 45.77 116.56 44.67 117.36 44.67 117.36 44.41 116.56 44.41 116.56 43.31 117.36 43.31 117.36 43.05 116.56 43.05 116.56 41.95 117.36 41.95 117.36 41.69 116.56 41.69 116.56 40.59 117.36 40.59 117.36 40.33 116.56 40.33 116.56 39.23 117.36 39.23 117.36 38.97 116.56 38.97 116.56 37.87 117.36 37.87 117.36 37.61 116.56 37.61 116.56 36.51 117.36 36.51 117.36 36.25 116.56 36.25 116.56 35.15 117.36 35.15 117.36 34.21 116.56 34.21 116.56 33.11 117.36 33.11 117.36 32.85 116.56 32.85 116.56 31.75 117.36 31.75 117.36 31.49 116.56 31.49 116.56 30.39 117.36 30.39 117.36 30.13 116.56 30.13 116.56 29.03 117.36 29.03 117.36 28.77 116.56 28.77 116.56 27.67 117.36 27.67 117.36 27.41 116.56 27.41 116.56 26.31 117.36 26.31 117.36 26.05 116.56 26.05 116.56 24.95 117.36 24.95 117.36 24.69 116.56 24.69 116.56 23.59 117.36 23.59 117.36 23.33 116.56 23.33 116.56 22.23 117.36 22.23 117.36 21.29 116.56 21.29 116.56 20.19 117.36 20.19 117.36 19.93 116.56 19.93 116.56 18.83 117.36 18.83 117.36 18.57 116.56 18.57 116.56 17.47 117.36 17.47 117.36 15.17 116.56 15.17 116.56 14.07 117.36 14.07 117.36 11.28 91.6 11.28 91.6 0.4 26.16 0.4 26.16 11.28 0.4 11.28 0.4 14.07 1.2 14.07 1.2 15.17 0.4 15.17 0.4 15.43 1.2 15.43 1.2 16.53 0.4 16.53 0.4 16.79 1.2 16.79 1.2 17.89 0.4 17.89 0.4 18.15 1.2 18.15 1.2 19.25 0.4 19.25 0.4 20.19 1.2 20.19 1.2 21.29 0.4 21.29 0.4 21.55 1.2 21.55 1.2 22.65 0.4 22.65 0.4 22.91 1.2 22.91 1.2 24.01 0.4 24.01 0.4 24.27 1.2 24.27 1.2 25.37 0.4 25.37 0.4 25.63 1.2 25.63 1.2 26.73 0.4 26.73 0.4 26.99 1.2 26.99 1.2 28.09 0.4 28.09 0.4 29.03 1.2 29.03 1.2 30.13 0.4 30.13 0.4 31.07 1.2 31.07 1.2 32.17 0.4 32.17 0.4 32.43 1.2 32.43 1.2 33.53 0.4 33.53 0.4 33.79 1.2 33.79 1.2 34.89 0.4 34.89 0.4 35.15 1.2 35.15 1.2 36.25 0.4 36.25 0.4 37.19 1.2 37.19 1.2 38.29 0.4 38.29 0.4 38.55 1.2 38.55 1.2 39.65 0.4 39.65 0.4 39.91 1.2 39.91 1.2 41.01 0.4 41.01 0.4 41.27 1.2 41.27 1.2 42.37 0.4 42.37 0.4 42.63 1.2 42.63 1.2 43.73 0.4 43.73 0.4 43.99 1.2 43.99 1.2 45.09 0.4 45.09 0.4 45.35 1.2 45.35 1.2 46.45 0.4 46.45 0.4 46.71 1.2 46.71 1.2 47.81 0.4 47.81 0.4 48.07 1.2 48.07 1.2 49.17 0.4 49.17 0.4 49.43 1.2 49.43 1.2 50.53 0.4 50.53 0.4 50.79 1.2 50.79 1.2 51.89 0.4 51.89 0.4 52.15 1.2 52.15 1.2 53.25 0.4 53.25 0.4 53.51 1.2 53.51 1.2 54.61 0.4 54.61 0.4 54.87 1.2 54.87 1.2 55.97 0.4 55.97 0.4 56.23 1.2 56.23 1.2 57.33 0.4 57.33 0.4 57.59 1.2 57.59 1.2 58.69 0.4 58.69 0.4 58.95 1.2 58.95 1.2 60.05 0.4 60.05 0.4 60.31 1.2 60.31 1.2 61.41 0.4 61.41 0.4 62.35 1.2 62.35 1.2 63.45 0.4 63.45 0.4 63.71 1.2 63.71 1.2 64.81 0.4 64.81 0.4 65.07 1.2 65.07 1.2 66.17 0.4 66.17 0.4 66.43 1.2 66.43 1.2 67.53 0.4 67.53 0.4 67.79 1.2 67.79 1.2 68.89 0.4 68.89 0.4 69.15 1.2 69.15 1.2 70.25 0.4 70.25 0.4 71.19 1.2 71.19 1.2 72.29 0.4 72.29 0.4 72.55 1.2 72.55 1.2 73.65 0.4 73.65 0.4 73.91 1.2 73.91 1.2 75.01 0.4 75.01 0.4 90.23 1.2 90.23 1.2 91.33 0.4 91.33 0.4 97.52 ;
+    LAYER met2 ;
+      RECT 80.82 97.735 81.1 98.105 ;
+      RECT 51.38 97.735 51.66 98.105 ;
+      RECT 10.9 97.735 11.18 98.105 ;
+      RECT 10.9 10.695 11.18 11.065 ;
+      RECT 80.82 -0.185 81.1 0.185 ;
+      RECT 51.38 -0.185 51.66 0.185 ;
+      POLYGON 117.48 97.64 117.48 11.16 113.28 11.16 113.28 11.645 112.58 11.645 112.58 11.16 111.9 11.16 111.9 11.645 111.2 11.645 111.2 11.16 109.14 11.16 109.14 11.645 108.44 11.645 108.44 11.16 108.22 11.16 108.22 11.645 107.52 11.645 107.52 11.16 107.3 11.16 107.3 11.645 106.6 11.645 106.6 11.16 106.38 11.16 106.38 11.645 105.68 11.645 105.68 11.16 105.46 11.16 105.46 11.645 104.76 11.645 104.76 11.16 104.54 11.16 104.54 11.645 103.84 11.645 103.84 11.16 91.72 11.16 91.72 0.28 89.82 0.28 89.82 0.765 89.12 0.765 89.12 0.28 86.6 0.28 86.6 0.765 85.9 0.765 85.9 0.28 85.68 0.28 85.68 0.765 84.98 0.765 84.98 0.28 84.76 0.28 84.76 0.765 84.06 0.765 84.06 0.28 83.84 0.28 83.84 0.765 83.14 0.765 83.14 0.28 82.92 0.28 82.92 0.765 82.22 0.765 82.22 0.28 82 0.28 82 0.765 81.3 0.765 81.3 0.28 80.62 0.28 80.62 0.765 79.92 0.765 79.92 0.28 79.7 0.28 79.7 0.765 79 0.765 79 0.28 77.4 0.28 77.4 0.765 76.7 0.765 76.7 0.28 76.48 0.28 76.48 0.765 75.78 0.765 75.78 0.28 75.56 0.28 75.56 0.765 74.86 0.765 74.86 0.28 74.64 0.28 74.64 0.765 73.94 0.765 73.94 0.28 73.72 0.28 73.72 0.765 73.02 0.765 73.02 0.28 68.2 0.28 68.2 0.765 67.5 0.765 67.5 0.28 67.28 0.28 67.28 0.765 66.58 0.765 66.58 0.28 66.36 0.28 66.36 0.765 65.66 0.765 65.66 0.28 65.44 0.28 65.44 0.765 64.74 0.765 64.74 0.28 64.52 0.28 64.52 0.765 63.82 0.765 63.82 0.28 63.6 0.28 63.6 0.765 62.9 0.765 62.9 0.28 62.68 0.28 62.68 0.765 61.98 0.765 61.98 0.28 60.84 0.28 60.84 0.765 60.14 0.765 60.14 0.28 59.92 0.28 59.92 0.765 59.22 0.765 59.22 0.28 59 0.28 59 0.765 58.3 0.765 58.3 0.28 58.08 0.28 58.08 0.765 57.38 0.765 57.38 0.28 56.24 0.28 56.24 0.765 55.54 0.765 55.54 0.28 55.32 0.28 55.32 0.765 54.62 0.765 54.62 0.28 54.4 0.28 54.4 0.765 53.7 0.765 53.7 0.28 53.48 0.28 53.48 0.765 52.78 0.765 52.78 0.28 52.56 0.28 52.56 0.765 51.86 0.765 51.86 0.28 40.6 0.28 40.6 0.765 39.9 0.765 39.9 0.28 39.68 0.28 39.68 0.765 38.98 0.765 38.98 0.28 38.76 0.28 38.76 0.765 38.06 0.765 38.06 0.28 37.84 0.28 37.84 0.765 37.14 0.765 37.14 0.28 36.92 0.28 36.92 0.765 36.22 0.765 36.22 0.28 36 0.28 36 0.765 35.3 0.765 35.3 0.28 35.08 0.28 35.08 0.765 34.38 0.765 34.38 0.28 34.16 0.28 34.16 0.765 33.46 0.765 33.46 0.28 33.24 0.28 33.24 0.765 32.54 0.765 32.54 0.28 28.64 0.28 28.64 0.765 27.94 0.765 27.94 0.28 26.04 0.28 26.04 11.16 15.76 11.16 15.76 11.645 15.06 11.645 15.06 11.16 14.84 11.16 14.84 11.645 14.14 11.645 14.14 11.16 13.92 11.16 13.92 11.645 13.22 11.645 13.22 11.16 13 11.16 13 11.645 12.3 11.645 12.3 11.16 12.08 11.16 12.08 11.645 11.38 11.645 11.38 11.16 10.7 11.16 10.7 11.645 10 11.645 10 11.16 9.32 11.16 9.32 11.645 8.62 11.645 8.62 11.16 8.4 11.16 8.4 11.645 7.7 11.645 7.7 11.16 7.48 11.16 7.48 11.645 6.78 11.645 6.78 11.16 6.56 11.16 6.56 11.645 5.86 11.645 5.86 11.16 5.64 11.16 5.64 11.645 4.94 11.645 4.94 11.16 4.72 11.16 4.72 11.645 4.02 11.645 4.02 11.16 3.34 11.16 3.34 11.645 2.64 11.645 2.64 11.16 0.28 11.16 0.28 97.64 ;
+    LAYER met4 ;
+      POLYGON 117.36 97.52 117.36 11.28 107.42 11.28 107.42 11.88 106.02 11.88 106.02 11.28 91.6 11.28 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 75.53 0.4 75.53 1.2 74.43 1.2 74.43 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 53.45 0.4 53.45 1.2 52.35 1.2 52.35 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 26.16 0.4 26.16 11.28 11.74 11.28 11.74 11.88 10.34 11.88 10.34 11.28 9.29 11.28 9.29 12.08 8.19 12.08 8.19 11.28 7.45 11.28 7.45 12.08 6.35 12.08 6.35 11.28 0.4 11.28 0.4 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 36.1 97.52 36.1 96.92 37.5 96.92 37.5 97.52 50.82 97.52 50.82 96.92 52.22 96.92 52.22 97.52 65.54 97.52 65.54 96.92 66.94 96.92 66.94 97.52 80.26 97.52 80.26 96.92 81.66 96.92 81.66 97.52 106.02 97.52 106.02 96.92 107.42 96.92 107.42 97.52 ;
+    LAYER met5 ;
+      POLYGON 116.16 96.32 116.16 88.2 112.96 88.2 112.96 81.8 116.16 81.8 116.16 67.8 112.96 67.8 112.96 61.4 116.16 61.4 116.16 47.4 112.96 47.4 112.96 41 116.16 41 116.16 27 112.96 27 112.96 20.6 116.16 20.6 116.16 12.48 90.4 12.48 90.4 1.6 27.36 1.6 27.36 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 ;
+    LAYER met1 ;
+      RECT 45.68 97.68 96 98.16 ;
+      POLYGON 14.56 12.48 14.56 11.46 28.59 11.46 28.59 11.52 28.91 11.52 28.91 11.26 28.59 11.26 28.59 11.32 14.42 11.32 14.42 12.48 ;
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+END sb_1__2_
+
+END LIBRARY
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef
new file mode 100644
index 0000000..fe760eb
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef
@@ -0,0 +1,1415 @@
+VERSION 5.7 ;
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+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIA M2M3_PR_C
+  LAYER met2 ;
+    RECT -0.185 -0.185 0.185 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIA M3M4_PR
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIA M3M4_PR_R
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIA M3M4_PR_M
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIA M3M4_PR_MR
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIA M3M4_PR_C
+  LAYER met3 ;
+    RECT -0.19 -0.19 0.19 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIA M4M5_PR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIA M4M5_PR_R
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIA M4M5_PR_M
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIA M4M5_PR_MR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIA M4M5_PR_C
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+  CLASS CORE ;
+  SYMMETRY Y ;
+  SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+  CLASS CORE ;
+  SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+MACRO sb_2__0_
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 92 BY 97.92 ;
+  SYMMETRY X Y ;
+  PIN chany_top_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 56.74 97.435 56.88 97.92 ;
+    END
+  END chany_top_in[0]
+  PIN chany_top_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.04 97.435 59.18 97.92 ;
+    END
+  END chany_top_in[1]
+  PIN chany_top_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 65.02 97.435 65.16 97.92 ;
+    END
+  END chany_top_in[2]
+  PIN chany_top_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 70.08 97.435 70.22 97.92 ;
+    END
+  END chany_top_in[3]
+  PIN chany_top_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.18 97.435 63.32 97.92 ;
+    END
+  END chany_top_in[4]
+  PIN chany_top_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 67.78 97.435 67.92 97.92 ;
+    END
+  END chany_top_in[5]
+  PIN chany_top_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.14 97.435 52.28 97.92 ;
+    END
+  END chany_top_in[6]
+  PIN chany_top_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.06 97.435 53.2 97.92 ;
+    END
+  END chany_top_in[7]
+  PIN chany_top_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 45.7 97.435 45.84 97.92 ;
+    END
+  END chany_top_in[8]
+  PIN chany_top_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 65.94 97.435 66.08 97.92 ;
+    END
+  END chany_top_in[9]
+  PIN chany_top_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 64.1 97.435 64.24 97.92 ;
+    END
+  END chany_top_in[10]
+  PIN chany_top_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 74.68 97.435 74.82 97.92 ;
+    END
+  END chany_top_in[11]
+  PIN chany_top_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 62.26 97.435 62.4 97.92 ;
+    END
+  END chany_top_in[12]
+  PIN chany_top_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 72.84 97.435 72.98 97.92 ;
+    END
+  END chany_top_in[13]
+  PIN chany_top_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.98 97.435 54.12 97.92 ;
+    END
+  END chany_top_in[14]
+  PIN chany_top_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.12 97.435 58.26 97.92 ;
+    END
+  END chany_top_in[15]
+  PIN chany_top_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 48.46 97.435 48.6 97.92 ;
+    END
+  END chany_top_in[16]
+  PIN chany_top_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 73.76 97.435 73.9 97.92 ;
+    END
+  END chany_top_in[17]
+  PIN chany_top_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 44.78 97.435 44.92 97.92 ;
+    END
+  END chany_top_in[18]
+  PIN chany_top_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 69.16 97.435 69.3 97.92 ;
+    END
+  END chany_top_in[19]
+  PIN top_left_grid_pin_42_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.5 86.555 13.64 87.04 ;
+    END
+  END top_left_grid_pin_42_[0]
+  PIN top_left_grid_pin_43_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 11.66 86.555 11.8 87.04 ;
+    END
+  END top_left_grid_pin_43_[0]
+  PIN top_left_grid_pin_44_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 8.44 86.555 8.58 87.04 ;
+    END
+  END top_left_grid_pin_44_[0]
+  PIN top_left_grid_pin_45_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 12.58 86.555 12.72 87.04 ;
+    END
+  END top_left_grid_pin_45_[0]
+  PIN top_left_grid_pin_46_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 10.28 86.555 10.42 87.04 ;
+    END
+  END top_left_grid_pin_46_[0]
+  PIN top_left_grid_pin_47_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 4.3 86.555 4.44 87.04 ;
+    END
+  END top_left_grid_pin_47_[0]
+  PIN top_left_grid_pin_48_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 9.36 86.555 9.5 87.04 ;
+    END
+  END top_left_grid_pin_48_[0]
+  PIN top_left_grid_pin_49_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.06 86.555 7.2 87.04 ;
+    END
+  END top_left_grid_pin_49_[0]
+  PIN top_right_grid_pin_1_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 31.44 97.435 31.58 97.92 ;
+    END
+  END top_right_grid_pin_1_[0]
+  PIN chanx_left_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 36.91 0.8 37.21 ;
+    END
+  END chanx_left_in[0]
+  PIN chanx_left_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 21.27 0.8 21.57 ;
+    END
+  END chanx_left_in[1]
+  PIN chanx_left_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 63.43 0.8 63.73 ;
+    END
+  END chanx_left_in[2]
+  PIN chanx_left_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 47.11 0.8 47.41 ;
+    END
+  END chanx_left_in[3]
+  PIN chanx_left_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 45.75 0.8 46.05 ;
+    END
+  END chanx_left_in[4]
+  PIN chanx_left_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 49.83 0.8 50.13 ;
+    END
+  END chanx_left_in[5]
+  PIN chanx_left_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 60.71 0.8 61.01 ;
+    END
+  END chanx_left_in[6]
+  PIN chanx_left_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 55.95 0.8 56.25 ;
+    END
+  END chanx_left_in[7]
+  PIN chanx_left_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 64.79 0.8 65.09 ;
+    END
+  END chanx_left_in[8]
+  PIN chanx_left_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 51.19 0.8 51.49 ;
+    END
+  END chanx_left_in[9]
+  PIN chanx_left_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 29.43 0.8 29.73 ;
+    END
+  END chanx_left_in[10]
+  PIN chanx_left_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 15.83 0.8 16.13 ;
+    END
+  END chanx_left_in[11]
+  PIN chanx_left_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 68.19 0.8 68.49 ;
+    END
+  END chanx_left_in[12]
+  PIN chanx_left_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 48.47 0.8 48.77 ;
+    END
+  END chanx_left_in[13]
+  PIN chanx_left_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 38.27 0.8 38.57 ;
+    END
+  END chanx_left_in[14]
+  PIN chanx_left_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 57.31 0.8 57.61 ;
+    END
+  END chanx_left_in[15]
+  PIN chanx_left_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 62.07 0.8 62.37 ;
+    END
+  END chanx_left_in[16]
+  PIN chanx_left_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 73.63 0.8 73.93 ;
+    END
+  END chanx_left_in[17]
+  PIN chanx_left_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 59.35 0.8 59.65 ;
+    END
+  END chanx_left_in[18]
+  PIN chanx_left_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 78.39 0.8 78.69 ;
+    END
+  END chanx_left_in[19]
+  PIN left_bottom_grid_pin_1_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 26.71 0.8 27.01 ;
+    END
+  END left_bottom_grid_pin_1_[0]
+  PIN left_bottom_grid_pin_3_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 25.35 0.8 25.65 ;
+    END
+  END left_bottom_grid_pin_3_[0]
+  PIN left_bottom_grid_pin_5_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 14.47 0.8 14.77 ;
+    END
+  END left_bottom_grid_pin_5_[0]
+  PIN left_bottom_grid_pin_7_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 32.83 0.8 33.13 ;
+    END
+  END left_bottom_grid_pin_7_[0]
+  PIN left_bottom_grid_pin_9_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 13.11 0.8 13.41 ;
+    END
+  END left_bottom_grid_pin_9_[0]
+  PIN left_bottom_grid_pin_11_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 23.99 0.8 24.29 ;
+    END
+  END left_bottom_grid_pin_11_[0]
+  PIN left_bottom_grid_pin_13_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 22.63 0.8 22.93 ;
+    END
+  END left_bottom_grid_pin_13_[0]
+  PIN left_bottom_grid_pin_15_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 11.75 0.8 12.05 ;
+    END
+  END left_bottom_grid_pin_15_[0]
+  PIN left_bottom_grid_pin_17_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 19.91 0.8 20.21 ;
+    END
+  END left_bottom_grid_pin_17_[0]
+  PIN ccff_head[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 30.52 97.435 30.66 97.92 ;
+    END
+  END ccff_head[0]
+  PIN chany_top_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 76.52 97.435 76.66 97.92 ;
+    END
+  END chany_top_out[0]
+  PIN chany_top_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 43.86 97.435 44 97.92 ;
+    END
+  END chany_top_out[1]
+  PIN chany_top_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 75.6 97.435 75.74 97.92 ;
+    END
+  END chany_top_out[2]
+  PIN chany_top_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 77.44 97.435 77.58 97.92 ;
+    END
+  END chany_top_out[3]
+  PIN chany_top_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.96 97.435 60.1 97.92 ;
+    END
+  END chany_top_out[4]
+  PIN chany_top_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 46.62 97.435 46.76 97.92 ;
+    END
+  END chany_top_out[5]
+  PIN chany_top_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 54.9 97.435 55.04 97.92 ;
+    END
+  END chany_top_out[6]
+  PIN chany_top_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 78.36 97.435 78.5 97.92 ;
+    END
+  END chany_top_out[7]
+  PIN chany_top_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 66.86 97.435 67 97.92 ;
+    END
+  END chany_top_out[8]
+  PIN chany_top_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 55.82 97.435 55.96 97.92 ;
+    END
+  END chany_top_out[9]
+  PIN chany_top_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 47.54 97.435 47.68 97.92 ;
+    END
+  END chany_top_out[10]
+  PIN chany_top_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.34 97.435 61.48 97.92 ;
+    END
+  END chany_top_out[11]
+  PIN chany_top_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 38.34 97.435 38.48 97.92 ;
+    END
+  END chany_top_out[12]
+  PIN chany_top_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 79.28 97.435 79.42 97.92 ;
+    END
+  END chany_top_out[13]
+  PIN chany_top_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 50.76 97.435 50.9 97.92 ;
+    END
+  END chany_top_out[14]
+  PIN chany_top_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 49.84 97.435 49.98 97.92 ;
+    END
+  END chany_top_out[15]
+  PIN chany_top_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 32.36 97.435 32.5 97.92 ;
+    END
+  END chany_top_out[16]
+  PIN chany_top_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 71.92 97.435 72.06 97.92 ;
+    END
+  END chany_top_out[17]
+  PIN chany_top_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 33.28 97.435 33.42 97.92 ;
+    END
+  END chany_top_out[18]
+  PIN chany_top_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 71 97.435 71.14 97.92 ;
+    END
+  END chany_top_out[19]
+  PIN chanx_left_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 53.23 0.8 53.53 ;
+    END
+  END chanx_left_out[0]
+  PIN chanx_left_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 74.99 0.8 75.29 ;
+    END
+  END chanx_left_out[1]
+  PIN chanx_left_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 54.59 0.8 54.89 ;
+    END
+  END chanx_left_out[2]
+  PIN chanx_left_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 44.39 0.8 44.69 ;
+    END
+  END chanx_left_out[3]
+  PIN chanx_left_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 77.03 0.8 77.33 ;
+    END
+  END chanx_left_out[4]
+  PIN chanx_left_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 31.47 0.8 31.77 ;
+    END
+  END chanx_left_out[5]
+  PIN chanx_left_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 69.55 0.8 69.85 ;
+    END
+  END chanx_left_out[6]
+  PIN chanx_left_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 18.55 0.8 18.85 ;
+    END
+  END chanx_left_out[7]
+  PIN chanx_left_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 34.19 0.8 34.49 ;
+    END
+  END chanx_left_out[8]
+  PIN chanx_left_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 66.83 0.8 67.13 ;
+    END
+  END chanx_left_out[9]
+  PIN chanx_left_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 43.03 0.8 43.33 ;
+    END
+  END chanx_left_out[10]
+  PIN chanx_left_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 39.63 0.8 39.93 ;
+    END
+  END chanx_left_out[11]
+  PIN chanx_left_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 35.55 0.8 35.85 ;
+    END
+  END chanx_left_out[12]
+  PIN chanx_left_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 72.27 0.8 72.57 ;
+    END
+  END chanx_left_out[13]
+  PIN chanx_left_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 79.75 0.8 80.05 ;
+    END
+  END chanx_left_out[14]
+  PIN chanx_left_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 83.15 0.8 83.45 ;
+    END
+  END chanx_left_out[15]
+  PIN chanx_left_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 17.19 0.8 17.49 ;
+    END
+  END chanx_left_out[16]
+  PIN chanx_left_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 28.07 0.8 28.37 ;
+    END
+  END chanx_left_out[17]
+  PIN chanx_left_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 41.67 0.8 41.97 ;
+    END
+  END chanx_left_out[18]
+  PIN chanx_left_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 70.91 0.8 71.21 ;
+    END
+  END chanx_left_out[19]
+  PIN ccff_tail[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 81.11 0.8 81.41 ;
+    END
+  END ccff_tail[0]
+  PIN prog_clk_0_N_in
+    DIRECTION INPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met2 ;
+        RECT 37.42 97.435 37.56 97.92 ;
+    END
+  END prog_clk_0_N_in
+  PIN VDD
+    DIRECTION INPUT ;
+    USE POWER ;
+    PORT
+      LAYER met5 ;
+        RECT 0 11.32 3.2 14.52 ;
+        RECT 88.8 11.32 92 14.52 ;
+        RECT 0 52.12 3.2 55.32 ;
+        RECT 88.8 52.12 92 55.32 ;
+      LAYER met4 ;
+        RECT 36.5 0 37.1 0.6 ;
+        RECT 65.94 0 66.54 0.6 ;
+        RECT 36.5 97.32 37.1 97.92 ;
+        RECT 65.94 97.32 66.54 97.92 ;
+      LAYER met1 ;
+        RECT 0 2.48 0.48 2.96 ;
+        RECT 91.52 2.48 92 2.96 ;
+        RECT 0 7.92 0.48 8.4 ;
+        RECT 91.52 7.92 92 8.4 ;
+        RECT 0 13.36 0.48 13.84 ;
+        RECT 91.52 13.36 92 13.84 ;
+        RECT 0 18.8 0.48 19.28 ;
+        RECT 91.52 18.8 92 19.28 ;
+        RECT 0 24.24 0.48 24.72 ;
+        RECT 91.52 24.24 92 24.72 ;
+        RECT 0 29.68 0.48 30.16 ;
+        RECT 91.52 29.68 92 30.16 ;
+        RECT 0 35.12 0.48 35.6 ;
+        RECT 91.52 35.12 92 35.6 ;
+        RECT 0 40.56 0.48 41.04 ;
+        RECT 91.52 40.56 92 41.04 ;
+        RECT 0 46 0.48 46.48 ;
+        RECT 91.52 46 92 46.48 ;
+        RECT 0 51.44 0.48 51.92 ;
+        RECT 91.52 51.44 92 51.92 ;
+        RECT 0 56.88 0.48 57.36 ;
+        RECT 91.52 56.88 92 57.36 ;
+        RECT 0 62.32 0.48 62.8 ;
+        RECT 91.52 62.32 92 62.8 ;
+        RECT 0 67.76 0.48 68.24 ;
+        RECT 91.52 67.76 92 68.24 ;
+        RECT 0 73.2 0.48 73.68 ;
+        RECT 91.52 73.2 92 73.68 ;
+        RECT 0 78.64 0.48 79.12 ;
+        RECT 91.52 78.64 92 79.12 ;
+        RECT 0 84.08 0.48 84.56 ;
+        RECT 91.52 84.08 92 84.56 ;
+        RECT 25.76 89.52 26.24 90 ;
+        RECT 91.52 89.52 92 90 ;
+        RECT 25.76 94.96 26.24 95.44 ;
+        RECT 91.52 94.96 92 95.44 ;
+    END
+  END VDD
+  PIN VSS
+    DIRECTION INPUT ;
+    USE GROUND ;
+    PORT
+      LAYER met4 ;
+        RECT 10.74 0 11.34 0.6 ;
+        RECT 51.22 0 51.82 0.6 ;
+        RECT 80.66 0 81.26 0.6 ;
+        RECT 10.74 86.44 11.34 87.04 ;
+        RECT 51.22 97.32 51.82 97.92 ;
+        RECT 80.66 97.32 81.26 97.92 ;
+      LAYER met5 ;
+        RECT 0 31.72 3.2 34.92 ;
+        RECT 88.8 31.72 92 34.92 ;
+        RECT 0 72.52 3.2 75.72 ;
+        RECT 88.8 72.52 92 75.72 ;
+      LAYER met1 ;
+        RECT 0 0 45.4 0.24 ;
+        RECT 46.6 0 92 0.24 ;
+        RECT 0 5.2 0.48 5.68 ;
+        RECT 91.52 5.2 92 5.68 ;
+        RECT 0 10.64 0.48 11.12 ;
+        RECT 91.52 10.64 92 11.12 ;
+        RECT 0 16.08 0.48 16.56 ;
+        RECT 91.52 16.08 92 16.56 ;
+        RECT 0 21.52 0.48 22 ;
+        RECT 91.52 21.52 92 22 ;
+        RECT 0 26.96 0.48 27.44 ;
+        RECT 91.52 26.96 92 27.44 ;
+        RECT 0 32.4 0.48 32.88 ;
+        RECT 91.52 32.4 92 32.88 ;
+        RECT 0 37.84 0.48 38.32 ;
+        RECT 91.52 37.84 92 38.32 ;
+        RECT 0 43.28 0.48 43.76 ;
+        RECT 91.52 43.28 92 43.76 ;
+        RECT 0 48.72 0.48 49.2 ;
+        RECT 91.52 48.72 92 49.2 ;
+        RECT 0 54.16 0.48 54.64 ;
+        RECT 91.52 54.16 92 54.64 ;
+        RECT 0 59.6 0.48 60.08 ;
+        RECT 91.52 59.6 92 60.08 ;
+        RECT 0 65.04 0.48 65.52 ;
+        RECT 91.52 65.04 92 65.52 ;
+        RECT 0 70.48 0.48 70.96 ;
+        RECT 91.52 70.48 92 70.96 ;
+        RECT 0 75.92 0.48 76.4 ;
+        RECT 91.52 75.92 92 76.4 ;
+        RECT 0 81.36 0.48 81.84 ;
+        RECT 91.52 81.36 92 81.84 ;
+        RECT 0 86.8 45.4 87.28 ;
+        RECT 91.52 86.8 92 87.28 ;
+        RECT 25.76 92.24 26.24 92.72 ;
+        RECT 91.52 92.24 92 92.72 ;
+        RECT 25.76 97.68 45.4 97.92 ;
+        RECT 46.6 97.68 92 97.92 ;
+    END
+  END VSS
+  OBS
+    LAYER met2 ;
+      RECT 80.82 97.735 81.1 98.105 ;
+      RECT 51.38 97.735 51.66 98.105 ;
+      RECT 10.9 86.855 11.18 87.225 ;
+      RECT 80.82 -0.185 81.1 0.185 ;
+      RECT 51.38 -0.185 51.66 0.185 ;
+      RECT 10.9 -0.185 11.18 0.185 ;
+      POLYGON 91.72 97.64 91.72 0.28 0.28 0.28 0.28 86.76 4.02 86.76 4.02 86.275 4.72 86.275 4.72 86.76 6.78 86.76 6.78 86.275 7.48 86.275 7.48 86.76 8.16 86.76 8.16 86.275 8.86 86.275 8.86 86.76 9.08 86.76 9.08 86.275 9.78 86.275 9.78 86.76 10 86.76 10 86.275 10.7 86.275 10.7 86.76 11.38 86.76 11.38 86.275 12.08 86.275 12.08 86.76 12.3 86.76 12.3 86.275 13 86.275 13 86.76 13.22 86.76 13.22 86.275 13.92 86.275 13.92 86.76 26.04 86.76 26.04 97.64 30.24 97.64 30.24 97.155 30.94 97.155 30.94 97.64 31.16 97.64 31.16 97.155 31.86 97.155 31.86 97.64 32.08 97.64 32.08 97.155 32.78 97.155 32.78 97.64 33 97.64 33 97.155 33.7 97.155 33.7 97.64 37.14 97.64 37.14 97.155 37.84 97.155 37.84 97.64 38.06 97.64 38.06 97.155 38.76 97.155 38.76 97.64 43.58 97.64 43.58 97.155 44.28 97.155 44.28 97.64 44.5 97.64 44.5 97.155 45.2 97.155 45.2 97.64 45.42 97.64 45.42 97.155 46.12 97.155 46.12 97.64 46.34 97.64 46.34 97.155 47.04 97.155 47.04 97.64 47.26 97.64 47.26 97.155 47.96 97.155 47.96 97.64 48.18 97.64 48.18 97.155 48.88 97.155 48.88 97.64 49.56 97.64 49.56 97.155 50.26 97.155 50.26 97.64 50.48 97.64 50.48 97.155 51.18 97.155 51.18 97.64 51.86 97.64 51.86 97.155 52.56 97.155 52.56 97.64 52.78 97.64 52.78 97.155 53.48 97.155 53.48 97.64 53.7 97.64 53.7 97.155 54.4 97.155 54.4 97.64 54.62 97.64 54.62 97.155 55.32 97.155 55.32 97.64 55.54 97.64 55.54 97.155 56.24 97.155 56.24 97.64 56.46 97.64 56.46 97.155 57.16 97.155 57.16 97.64 57.84 97.64 57.84 97.155 58.54 97.155 58.54 97.64 58.76 97.64 58.76 97.155 59.46 97.155 59.46 97.64 59.68 97.64 59.68 97.155 60.38 97.155 60.38 97.64 61.06 97.64 61.06 97.155 61.76 97.155 61.76 97.64 61.98 97.64 61.98 97.155 62.68 97.155 62.68 97.64 62.9 97.64 62.9 97.155 63.6 97.155 63.6 97.64 63.82 97.64 63.82 97.155 64.52 97.155 64.52 97.64 64.74 97.64 64.74 97.155 65.44 97.155 65.44 97.64 65.66 97.64 65.66 97.155 66.36 97.155 66.36 97.64 66.58 97.64 66.58 97.155 67.28 97.155 67.28 97.64 67.5 97.64 67.5 97.155 68.2 97.155 68.2 97.64 68.88 97.64 68.88 97.155 69.58 97.155 69.58 97.64 69.8 97.64 69.8 97.155 70.5 97.155 70.5 97.64 70.72 97.64 70.72 97.155 71.42 97.155 71.42 97.64 71.64 97.64 71.64 97.155 72.34 97.155 72.34 97.64 72.56 97.64 72.56 97.155 73.26 97.155 73.26 97.64 73.48 97.64 73.48 97.155 74.18 97.155 74.18 97.64 74.4 97.64 74.4 97.155 75.1 97.155 75.1 97.64 75.32 97.64 75.32 97.155 76.02 97.155 76.02 97.64 76.24 97.64 76.24 97.155 76.94 97.155 76.94 97.64 77.16 97.64 77.16 97.155 77.86 97.155 77.86 97.64 78.08 97.64 78.08 97.155 78.78 97.155 78.78 97.64 79 97.64 79 97.155 79.7 97.155 79.7 97.64 ;
+    LAYER met3 ;
+      POLYGON 81.125 98.085 81.125 98.08 81.34 98.08 81.34 97.76 81.125 97.76 81.125 97.755 80.795 97.755 80.795 97.76 80.58 97.76 80.58 98.08 80.795 98.08 80.795 98.085 ;
+      POLYGON 51.685 98.085 51.685 98.08 51.9 98.08 51.9 97.76 51.685 97.76 51.685 97.755 51.355 97.755 51.355 97.76 51.14 97.76 51.14 98.08 51.355 98.08 51.355 98.085 ;
+      POLYGON 11.205 87.205 11.205 87.2 11.42 87.2 11.42 86.88 11.205 86.88 11.205 86.875 10.875 86.875 10.875 86.88 10.66 86.88 10.66 87.2 10.875 87.2 10.875 87.205 ;
+      POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ;
+      POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ;
+      POLYGON 11.205 0.165 11.205 0.16 11.42 0.16 11.42 -0.16 11.205 -0.16 11.205 -0.165 10.875 -0.165 10.875 -0.16 10.66 -0.16 10.66 0.16 10.875 0.16 10.875 0.165 ;
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+    LAYER met1 ;
+      RECT 45.68 97.68 46.32 98.16 ;
+      RECT 41.01 87.42 41.33 87.68 ;
+      POLYGON 32.59 86.66 32.59 86.4 32.27 86.4 32.27 86.46 32.115 86.46 32.115 86.415 31.825 86.415 31.825 86.645 32.115 86.645 32.115 86.6 32.27 86.6 32.27 86.66 ;
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+END LIBRARY
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef
new file mode 100644
index 0000000..2232c97
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef
@@ -0,0 +1,1839 @@
+VERSION 5.7 ;
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+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+  CLASS CORE ;
+  SYMMETRY Y ;
+  SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+  CLASS CORE ;
+  SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+MACRO sb_2__1_
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 92 BY 108.8 ;
+  SYMMETRY X Y ;
+  PIN chany_top_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 56.74 108.315 56.88 108.8 ;
+    END
+  END chany_top_in[0]
+  PIN chany_top_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.04 108.315 59.18 108.8 ;
+    END
+  END chany_top_in[1]
+  PIN chany_top_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 65.02 108.315 65.16 108.8 ;
+    END
+  END chany_top_in[2]
+  PIN chany_top_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 70.08 108.315 70.22 108.8 ;
+    END
+  END chany_top_in[3]
+  PIN chany_top_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.18 108.315 63.32 108.8 ;
+    END
+  END chany_top_in[4]
+  PIN chany_top_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 67.78 108.315 67.92 108.8 ;
+    END
+  END chany_top_in[5]
+  PIN chany_top_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.14 108.315 52.28 108.8 ;
+    END
+  END chany_top_in[6]
+  PIN chany_top_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.06 108.315 53.2 108.8 ;
+    END
+  END chany_top_in[7]
+  PIN chany_top_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 45.7 108.315 45.84 108.8 ;
+    END
+  END chany_top_in[8]
+  PIN chany_top_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 65.94 108.315 66.08 108.8 ;
+    END
+  END chany_top_in[9]
+  PIN chany_top_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 64.1 108.315 64.24 108.8 ;
+    END
+  END chany_top_in[10]
+  PIN chany_top_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 74.68 108.315 74.82 108.8 ;
+    END
+  END chany_top_in[11]
+  PIN chany_top_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 62.26 108.315 62.4 108.8 ;
+    END
+  END chany_top_in[12]
+  PIN chany_top_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 72.84 108.315 72.98 108.8 ;
+    END
+  END chany_top_in[13]
+  PIN chany_top_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.98 108.315 54.12 108.8 ;
+    END
+  END chany_top_in[14]
+  PIN chany_top_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.12 108.315 58.26 108.8 ;
+    END
+  END chany_top_in[15]
+  PIN chany_top_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 48.46 108.315 48.6 108.8 ;
+    END
+  END chany_top_in[16]
+  PIN chany_top_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 73.76 108.315 73.9 108.8 ;
+    END
+  END chany_top_in[17]
+  PIN chany_top_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 44.78 108.315 44.92 108.8 ;
+    END
+  END chany_top_in[18]
+  PIN chany_top_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 69.16 108.315 69.3 108.8 ;
+    END
+  END chany_top_in[19]
+  PIN top_left_grid_pin_42_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.5 97.435 13.64 97.92 ;
+    END
+  END top_left_grid_pin_42_[0]
+  PIN top_left_grid_pin_43_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 11.66 97.435 11.8 97.92 ;
+    END
+  END top_left_grid_pin_43_[0]
+  PIN top_left_grid_pin_44_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 8.44 97.435 8.58 97.92 ;
+    END
+  END top_left_grid_pin_44_[0]
+  PIN top_left_grid_pin_45_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 12.58 97.435 12.72 97.92 ;
+    END
+  END top_left_grid_pin_45_[0]
+  PIN top_left_grid_pin_46_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 10.28 97.435 10.42 97.92 ;
+    END
+  END top_left_grid_pin_46_[0]
+  PIN top_left_grid_pin_47_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 4.3 97.435 4.44 97.92 ;
+    END
+  END top_left_grid_pin_47_[0]
+  PIN top_left_grid_pin_48_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 9.36 97.435 9.5 97.92 ;
+    END
+  END top_left_grid_pin_48_[0]
+  PIN top_left_grid_pin_49_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.06 97.435 7.2 97.92 ;
+    END
+  END top_left_grid_pin_49_[0]
+  PIN top_right_grid_pin_1_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 31.44 108.315 31.58 108.8 ;
+    END
+  END top_right_grid_pin_1_[0]
+  PIN chany_bottom_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 70.08 0 70.22 0.485 ;
+    END
+  END chany_bottom_in[0]
+  PIN chany_bottom_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 81.58 0 81.72 0.485 ;
+    END
+  END chany_bottom_in[1]
+  PIN chany_bottom_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 57.2 0 57.34 0.485 ;
+    END
+  END chany_bottom_in[2]
+  PIN chany_bottom_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 80.2 0 80.34 0.485 ;
+    END
+  END chany_bottom_in[3]
+  PIN chany_bottom_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 64.56 0 64.7 0.485 ;
+    END
+  END chany_bottom_in[4]
+  PIN chany_bottom_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 76.52 0 76.66 0.485 ;
+    END
+  END chany_bottom_in[5]
+  PIN chany_bottom_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 55.36 0 55.5 0.485 ;
+    END
+  END chany_bottom_in[6]
+  PIN chany_bottom_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 73.76 0 73.9 0.485 ;
+    END
+  END chany_bottom_in[7]
+  PIN chany_bottom_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.64 0 63.78 0.485 ;
+    END
+  END chany_bottom_in[8]
+  PIN chany_bottom_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 69.16 0 69.3 0.485 ;
+    END
+  END chany_bottom_in[9]
+  PIN chany_bottom_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.14 0 52.28 0.485 ;
+    END
+  END chany_bottom_in[10]
+  PIN chany_bottom_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 71 0 71.14 0.485 ;
+    END
+  END chany_bottom_in[11]
+  PIN chany_bottom_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 75.6 0 75.74 0.485 ;
+    END
+  END chany_bottom_in[12]
+  PIN chany_bottom_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 78.36 0 78.5 0.485 ;
+    END
+  END chany_bottom_in[13]
+  PIN chany_bottom_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 54.44 0 54.58 0.485 ;
+    END
+  END chany_bottom_in[14]
+  PIN chany_bottom_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 66.4 0 66.54 0.485 ;
+    END
+  END chany_bottom_in[15]
+  PIN chany_bottom_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 47.08 0 47.22 0.485 ;
+    END
+  END chany_bottom_in[16]
+  PIN chany_bottom_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 77.44 0 77.58 0.485 ;
+    END
+  END chany_bottom_in[17]
+  PIN chany_bottom_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.06 0 53.2 0.485 ;
+    END
+  END chany_bottom_in[18]
+  PIN chany_bottom_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 79.28 0 79.42 0.485 ;
+    END
+  END chany_bottom_in[19]
+  PIN bottom_right_grid_pin_1_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 32.36 0 32.5 0.485 ;
+    END
+  END bottom_right_grid_pin_1_[0]
+  PIN bottom_left_grid_pin_42_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 14.42 10.88 14.56 11.365 ;
+    END
+  END bottom_left_grid_pin_42_[0]
+  PIN bottom_left_grid_pin_43_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 15.34 10.88 15.48 11.365 ;
+    END
+  END bottom_left_grid_pin_43_[0]
+  PIN bottom_left_grid_pin_44_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 2.92 10.88 3.06 11.365 ;
+    END
+  END bottom_left_grid_pin_44_[0]
+  PIN bottom_left_grid_pin_45_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 10.28 10.88 10.42 11.365 ;
+    END
+  END bottom_left_grid_pin_45_[0]
+  PIN bottom_left_grid_pin_46_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 5.22 10.88 5.36 11.365 ;
+    END
+  END bottom_left_grid_pin_46_[0]
+  PIN bottom_left_grid_pin_47_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 4.3 10.88 4.44 11.365 ;
+    END
+  END bottom_left_grid_pin_47_[0]
+  PIN bottom_left_grid_pin_48_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.5 10.88 13.64 11.365 ;
+    END
+  END bottom_left_grid_pin_48_[0]
+  PIN bottom_left_grid_pin_49_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.06 10.88 7.2 11.365 ;
+    END
+  END bottom_left_grid_pin_49_[0]
+  PIN chanx_left_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 59.35 0.8 59.65 ;
+    END
+  END chanx_left_in[0]
+  PIN chanx_left_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 53.91 0.8 54.21 ;
+    END
+  END chanx_left_in[1]
+  PIN chanx_left_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 62.07 0.8 62.37 ;
+    END
+  END chanx_left_in[2]
+  PIN chanx_left_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 56.63 0.8 56.93 ;
+    END
+  END chanx_left_in[3]
+  PIN chanx_left_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 22.63 0.8 22.93 ;
+    END
+  END chanx_left_in[4]
+  PIN chanx_left_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 47.11 0.8 47.41 ;
+    END
+  END chanx_left_in[5]
+  PIN chanx_left_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 43.03 0.8 43.33 ;
+    END
+  END chanx_left_in[6]
+  PIN chanx_left_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 48.47 0.8 48.77 ;
+    END
+  END chanx_left_in[7]
+  PIN chanx_left_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 66.83 0.8 67.13 ;
+    END
+  END chanx_left_in[8]
+  PIN chanx_left_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 72.27 0.8 72.57 ;
+    END
+  END chanx_left_in[9]
+  PIN chanx_left_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 41.67 0.8 41.97 ;
+    END
+  END chanx_left_in[10]
+  PIN chanx_left_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 57.99 0.8 58.29 ;
+    END
+  END chanx_left_in[11]
+  PIN chanx_left_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 60.71 0.8 61.01 ;
+    END
+  END chanx_left_in[12]
+  PIN chanx_left_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 87.91 0.8 88.21 ;
+    END
+  END chanx_left_in[13]
+  PIN chanx_left_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 45.75 0.8 46.05 ;
+    END
+  END chanx_left_in[14]
+  PIN chanx_left_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 69.55 0.8 69.85 ;
+    END
+  END chanx_left_in[15]
+  PIN chanx_left_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 63.43 0.8 63.73 ;
+    END
+  END chanx_left_in[16]
+  PIN chanx_left_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 70.91 0.8 71.21 ;
+    END
+  END chanx_left_in[17]
+  PIN chanx_left_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 85.19 0.8 85.49 ;
+    END
+  END chanx_left_in[18]
+  PIN chanx_left_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 68.19 0.8 68.49 ;
+    END
+  END chanx_left_in[19]
+  PIN left_bottom_grid_pin_34_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 6.75 10.88 7.05 11.68 ;
+    END
+  END left_bottom_grid_pin_34_[0]
+  PIN left_bottom_grid_pin_35_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 8.59 10.88 8.89 11.68 ;
+    END
+  END left_bottom_grid_pin_35_[0]
+  PIN left_bottom_grid_pin_36_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 8.9 10.88 9.04 11.365 ;
+    END
+  END left_bottom_grid_pin_36_[0]
+  PIN left_bottom_grid_pin_37_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.98 10.88 8.12 11.365 ;
+    END
+  END left_bottom_grid_pin_37_[0]
+  PIN left_bottom_grid_pin_38_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 11.66 10.88 11.8 11.365 ;
+    END
+  END left_bottom_grid_pin_38_[0]
+  PIN left_bottom_grid_pin_39_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 12.58 10.88 12.72 11.365 ;
+    END
+  END left_bottom_grid_pin_39_[0]
+  PIN left_bottom_grid_pin_40_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 18.56 10.88 18.7 11.365 ;
+    END
+  END left_bottom_grid_pin_40_[0]
+  PIN left_bottom_grid_pin_41_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 6.14 10.88 6.28 11.365 ;
+    END
+  END left_bottom_grid_pin_41_[0]
+  PIN ccff_head[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 30.52 108.315 30.66 108.8 ;
+    END
+  END ccff_head[0]
+  PIN chany_top_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 76.52 108.315 76.66 108.8 ;
+    END
+  END chany_top_out[0]
+  PIN chany_top_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 43.86 108.315 44 108.8 ;
+    END
+  END chany_top_out[1]
+  PIN chany_top_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 75.6 108.315 75.74 108.8 ;
+    END
+  END chany_top_out[2]
+  PIN chany_top_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 77.44 108.315 77.58 108.8 ;
+    END
+  END chany_top_out[3]
+  PIN chany_top_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.96 108.315 60.1 108.8 ;
+    END
+  END chany_top_out[4]
+  PIN chany_top_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 46.62 108.315 46.76 108.8 ;
+    END
+  END chany_top_out[5]
+  PIN chany_top_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 54.9 108.315 55.04 108.8 ;
+    END
+  END chany_top_out[6]
+  PIN chany_top_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 78.36 108.315 78.5 108.8 ;
+    END
+  END chany_top_out[7]
+  PIN chany_top_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 66.86 108.315 67 108.8 ;
+    END
+  END chany_top_out[8]
+  PIN chany_top_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 55.82 108.315 55.96 108.8 ;
+    END
+  END chany_top_out[9]
+  PIN chany_top_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 47.54 108.315 47.68 108.8 ;
+    END
+  END chany_top_out[10]
+  PIN chany_top_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.34 108.315 61.48 108.8 ;
+    END
+  END chany_top_out[11]
+  PIN chany_top_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 38.34 108.315 38.48 108.8 ;
+    END
+  END chany_top_out[12]
+  PIN chany_top_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 79.28 108.315 79.42 108.8 ;
+    END
+  END chany_top_out[13]
+  PIN chany_top_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 50.76 108.315 50.9 108.8 ;
+    END
+  END chany_top_out[14]
+  PIN chany_top_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 49.84 108.315 49.98 108.8 ;
+    END
+  END chany_top_out[15]
+  PIN chany_top_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 32.36 108.315 32.5 108.8 ;
+    END
+  END chany_top_out[16]
+  PIN chany_top_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 71.92 108.315 72.06 108.8 ;
+    END
+  END chany_top_out[17]
+  PIN chany_top_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 33.28 108.315 33.42 108.8 ;
+    END
+  END chany_top_out[18]
+  PIN chany_top_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 71 108.315 71.14 108.8 ;
+    END
+  END chany_top_out[19]
+  PIN chany_bottom_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 38.34 0 38.48 0.485 ;
+    END
+  END chany_bottom_out[0]
+  PIN chany_bottom_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 74.68 0 74.82 0.485 ;
+    END
+  END chany_bottom_out[1]
+  PIN chany_bottom_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 31.44 0 31.58 0.485 ;
+    END
+  END chany_bottom_out[2]
+  PIN chany_bottom_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 62.26 0 62.4 0.485 ;
+    END
+  END chany_bottom_out[3]
+  PIN chany_bottom_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 65.48 0 65.62 0.485 ;
+    END
+  END chany_bottom_out[4]
+  PIN chany_bottom_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 49.38 0 49.52 0.485 ;
+    END
+  END chany_bottom_out[5]
+  PIN chany_bottom_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 67.32 0 67.46 0.485 ;
+    END
+  END chany_bottom_out[6]
+  PIN chany_bottom_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 68.24 0 68.38 0.485 ;
+    END
+  END chany_bottom_out[7]
+  PIN chany_bottom_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.04 0 59.18 0.485 ;
+    END
+  END chany_bottom_out[8]
+  PIN chany_bottom_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 50.3 0 50.44 0.485 ;
+    END
+  END chany_bottom_out[9]
+  PIN chany_bottom_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 35.12 0 35.26 0.485 ;
+    END
+  END chany_bottom_out[10]
+  PIN chany_bottom_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.34 0 61.48 0.485 ;
+    END
+  END chany_bottom_out[11]
+  PIN chany_bottom_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.96 0 60.1 0.485 ;
+    END
+  END chany_bottom_out[12]
+  PIN chany_bottom_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 82.5 0 82.64 0.485 ;
+    END
+  END chany_bottom_out[13]
+  PIN chany_bottom_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 56.28 0 56.42 0.485 ;
+    END
+  END chany_bottom_out[14]
+  PIN chany_bottom_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.12 0 58.26 0.485 ;
+    END
+  END chany_bottom_out[15]
+  PIN chany_bottom_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 48 0 48.14 0.485 ;
+    END
+  END chany_bottom_out[16]
+  PIN chany_bottom_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 72.84 0 72.98 0.485 ;
+    END
+  END chany_bottom_out[17]
+  PIN chany_bottom_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 33.74 0 33.88 0.485 ;
+    END
+  END chany_bottom_out[18]
+  PIN chany_bottom_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 71.92 0 72.06 0.485 ;
+    END
+  END chany_bottom_out[19]
+  PIN chanx_left_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 23.99 0.8 24.29 ;
+    END
+  END chanx_left_out[0]
+  PIN chanx_left_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 64.79 0.8 65.09 ;
+    END
+  END chanx_left_out[1]
+  PIN chanx_left_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 34.87 0.8 35.17 ;
+    END
+  END chanx_left_out[2]
+  PIN chanx_left_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 55.27 0.8 55.57 ;
+    END
+  END chanx_left_out[3]
+  PIN chanx_left_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 15.83 0.8 16.13 ;
+    END
+  END chanx_left_out[4]
+  PIN chanx_left_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 44.39 0.8 44.69 ;
+    END
+  END chanx_left_out[5]
+  PIN chanx_left_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 33.51 0.8 33.81 ;
+    END
+  END chanx_left_out[6]
+  PIN chanx_left_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 25.35 0.8 25.65 ;
+    END
+  END chanx_left_out[7]
+  PIN chanx_left_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 30.79 0.8 31.09 ;
+    END
+  END chanx_left_out[8]
+  PIN chanx_left_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 49.83 0.8 50.13 ;
+    END
+  END chanx_left_out[9]
+  PIN chanx_left_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 36.23 0.8 36.53 ;
+    END
+  END chanx_left_out[10]
+  PIN chanx_left_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 52.55 0.8 52.85 ;
+    END
+  END chanx_left_out[11]
+  PIN chanx_left_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 17.19 0.8 17.49 ;
+    END
+  END chanx_left_out[12]
+  PIN chanx_left_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 86.55 0.8 86.85 ;
+    END
+  END chanx_left_out[13]
+  PIN chanx_left_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 37.59 0.8 37.89 ;
+    END
+  END chanx_left_out[14]
+  PIN chanx_left_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 28.07 0.8 28.37 ;
+    END
+  END chanx_left_out[15]
+  PIN chanx_left_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 14.47 0.8 14.77 ;
+    END
+  END chanx_left_out[16]
+  PIN chanx_left_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 51.19 0.8 51.49 ;
+    END
+  END chanx_left_out[17]
+  PIN chanx_left_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 32.15 0.8 32.45 ;
+    END
+  END chanx_left_out[18]
+  PIN chanx_left_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 26.71 0.8 27.01 ;
+    END
+  END chanx_left_out[19]
+  PIN ccff_tail[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 29.43 0.8 29.73 ;
+    END
+  END ccff_tail[0]
+  PIN prog_clk_0_N_in
+    DIRECTION INPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met2 ;
+        RECT 37.42 108.315 37.56 108.8 ;
+    END
+  END prog_clk_0_N_in
+  PIN VDD
+    DIRECTION INPUT ;
+    USE POWER ;
+    PORT
+      LAYER met1 ;
+        RECT 25.76 2.48 26.24 2.96 ;
+        RECT 91.52 2.48 92 2.96 ;
+        RECT 25.76 7.92 26.24 8.4 ;
+        RECT 91.52 7.92 92 8.4 ;
+        RECT 0 13.36 0.48 13.84 ;
+        RECT 91.52 13.36 92 13.84 ;
+        RECT 0 18.8 0.48 19.28 ;
+        RECT 91.52 18.8 92 19.28 ;
+        RECT 0 24.24 0.48 24.72 ;
+        RECT 91.52 24.24 92 24.72 ;
+        RECT 0 29.68 0.48 30.16 ;
+        RECT 91.52 29.68 92 30.16 ;
+        RECT 0 35.12 0.48 35.6 ;
+        RECT 91.52 35.12 92 35.6 ;
+        RECT 0 40.56 0.48 41.04 ;
+        RECT 91.52 40.56 92 41.04 ;
+        RECT 0 46 0.48 46.48 ;
+        RECT 91.52 46 92 46.48 ;
+        RECT 0 51.44 0.48 51.92 ;
+        RECT 91.52 51.44 92 51.92 ;
+        RECT 0 56.88 0.48 57.36 ;
+        RECT 91.52 56.88 92 57.36 ;
+        RECT 0 62.32 0.48 62.8 ;
+        RECT 91.52 62.32 92 62.8 ;
+        RECT 0 67.76 0.48 68.24 ;
+        RECT 91.52 67.76 92 68.24 ;
+        RECT 0 73.2 0.48 73.68 ;
+        RECT 91.52 73.2 92 73.68 ;
+        RECT 0 78.64 0.48 79.12 ;
+        RECT 91.52 78.64 92 79.12 ;
+        RECT 0 84.08 0.48 84.56 ;
+        RECT 91.52 84.08 92 84.56 ;
+        RECT 0 89.52 0.48 90 ;
+        RECT 91.52 89.52 92 90 ;
+        RECT 0 94.96 0.48 95.44 ;
+        RECT 91.52 94.96 92 95.44 ;
+        RECT 25.76 100.4 26.24 100.88 ;
+        RECT 91.52 100.4 92 100.88 ;
+        RECT 25.76 105.84 26.24 106.32 ;
+        RECT 91.52 105.84 92 106.32 ;
+      LAYER met5 ;
+        RECT 0 22.2 3.2 25.4 ;
+        RECT 88.8 22.2 92 25.4 ;
+        RECT 0 63 3.2 66.2 ;
+        RECT 88.8 63 92 66.2 ;
+      LAYER met4 ;
+        RECT 36.5 0 37.1 0.6 ;
+        RECT 65.94 0 66.54 0.6 ;
+        RECT 36.5 108.2 37.1 108.8 ;
+        RECT 65.94 108.2 66.54 108.8 ;
+    END
+  END VDD
+  PIN VSS
+    DIRECTION INPUT ;
+    USE GROUND ;
+    PORT
+      LAYER met1 ;
+        RECT 25.76 0 45.4 0.24 ;
+        RECT 46.6 0 92 0.24 ;
+        RECT 25.76 5.2 26.24 5.68 ;
+        RECT 91.52 5.2 92 5.68 ;
+        RECT 0 10.64 45.4 11.12 ;
+        RECT 91.52 10.64 92 11.12 ;
+        RECT 0 16.08 0.48 16.56 ;
+        RECT 91.52 16.08 92 16.56 ;
+        RECT 0 21.52 0.48 22 ;
+        RECT 91.52 21.52 92 22 ;
+        RECT 0 26.96 0.48 27.44 ;
+        RECT 91.52 26.96 92 27.44 ;
+        RECT 0 32.4 0.48 32.88 ;
+        RECT 91.52 32.4 92 32.88 ;
+        RECT 0 37.84 0.48 38.32 ;
+        RECT 91.52 37.84 92 38.32 ;
+        RECT 0 43.28 0.48 43.76 ;
+        RECT 91.52 43.28 92 43.76 ;
+        RECT 0 48.72 0.48 49.2 ;
+        RECT 91.52 48.72 92 49.2 ;
+        RECT 0 54.16 0.48 54.64 ;
+        RECT 91.52 54.16 92 54.64 ;
+        RECT 0 59.6 0.48 60.08 ;
+        RECT 91.52 59.6 92 60.08 ;
+        RECT 0 65.04 0.48 65.52 ;
+        RECT 91.52 65.04 92 65.52 ;
+        RECT 0 70.48 0.48 70.96 ;
+        RECT 91.52 70.48 92 70.96 ;
+        RECT 0 75.92 0.48 76.4 ;
+        RECT 91.52 75.92 92 76.4 ;
+        RECT 0 81.36 0.48 81.84 ;
+        RECT 91.52 81.36 92 81.84 ;
+        RECT 0 86.8 0.48 87.28 ;
+        RECT 91.52 86.8 92 87.28 ;
+        RECT 0 92.24 0.48 92.72 ;
+        RECT 91.52 92.24 92 92.72 ;
+        RECT 0 97.68 45.4 98.16 ;
+        RECT 91.52 97.68 92 98.16 ;
+        RECT 25.76 103.12 26.24 103.6 ;
+        RECT 91.52 103.12 92 103.6 ;
+        RECT 25.76 108.56 45.4 108.8 ;
+        RECT 46.6 108.56 92 108.8 ;
+      LAYER met5 ;
+        RECT 0 42.6 3.2 45.8 ;
+        RECT 88.8 42.6 92 45.8 ;
+        RECT 0 83.4 3.2 86.6 ;
+        RECT 88.8 83.4 92 86.6 ;
+      LAYER met4 ;
+        RECT 51.22 0 51.82 0.6 ;
+        RECT 80.66 0 81.26 0.6 ;
+        RECT 10.74 10.88 11.34 11.48 ;
+        RECT 10.74 97.32 11.34 97.92 ;
+        RECT 51.22 108.2 51.82 108.8 ;
+        RECT 80.66 108.2 81.26 108.8 ;
+    END
+  END VSS
+  OBS
+    LAYER met2 ;
+      RECT 80.82 108.615 81.1 108.985 ;
+      RECT 51.38 108.615 51.66 108.985 ;
+      RECT 10.9 97.735 11.18 98.105 ;
+      RECT 10.9 10.695 11.18 11.065 ;
+      RECT 80.82 -0.185 81.1 0.185 ;
+      RECT 51.38 -0.185 51.66 0.185 ;
+      POLYGON 91.72 108.52 91.72 0.28 82.92 0.28 82.92 0.765 82.22 0.765 82.22 0.28 82 0.28 82 0.765 81.3 0.765 81.3 0.28 80.62 0.28 80.62 0.765 79.92 0.765 79.92 0.28 79.7 0.28 79.7 0.765 79 0.765 79 0.28 78.78 0.28 78.78 0.765 78.08 0.765 78.08 0.28 77.86 0.28 77.86 0.765 77.16 0.765 77.16 0.28 76.94 0.28 76.94 0.765 76.24 0.765 76.24 0.28 76.02 0.28 76.02 0.765 75.32 0.765 75.32 0.28 75.1 0.28 75.1 0.765 74.4 0.765 74.4 0.28 74.18 0.28 74.18 0.765 73.48 0.765 73.48 0.28 73.26 0.28 73.26 0.765 72.56 0.765 72.56 0.28 72.34 0.28 72.34 0.765 71.64 0.765 71.64 0.28 71.42 0.28 71.42 0.765 70.72 0.765 70.72 0.28 70.5 0.28 70.5 0.765 69.8 0.765 69.8 0.28 69.58 0.28 69.58 0.765 68.88 0.765 68.88 0.28 68.66 0.28 68.66 0.765 67.96 0.765 67.96 0.28 67.74 0.28 67.74 0.765 67.04 0.765 67.04 0.28 66.82 0.28 66.82 0.765 66.12 0.765 66.12 0.28 65.9 0.28 65.9 0.765 65.2 0.765 65.2 0.28 64.98 0.28 64.98 0.765 64.28 0.765 64.28 0.28 64.06 0.28 64.06 0.765 63.36 0.765 63.36 0.28 62.68 0.28 62.68 0.765 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+      RECT 91.08 13.515 92 13.685 ;
+      RECT 0 13.515 3.68 13.685 ;
+      RECT 91.08 10.795 92 10.965 ;
+      RECT 0 10.795 27.6 10.965 ;
+      RECT 91.08 8.075 92 8.245 ;
+      RECT 25.76 8.075 29.44 8.245 ;
+      RECT 91.08 5.355 92 5.525 ;
+      RECT 25.76 5.355 29.44 5.525 ;
+      RECT 88.32 2.635 92 2.805 ;
+      RECT 25.76 2.635 29.44 2.805 ;
+      RECT 25.76 -0.085 92 0.085 ;
+      POLYGON 91.83 108.63 91.83 0.17 25.93 0.17 25.93 11.05 0.17 11.05 0.17 97.75 25.93 97.75 25.93 108.63 ;
+    LAYER mcon ;
+      RECT 35.565 98.345 35.735 98.515 ;
+      RECT 44.765 97.325 44.935 97.495 ;
+      RECT 44.825 11.305 44.995 11.475 ;
+      RECT 42.925 11.305 43.095 11.475 ;
+      RECT 40.685 11.305 40.855 11.475 ;
+      RECT 38.785 11.305 38.955 11.475 ;
+      RECT 36.085 11.305 36.255 11.475 ;
+      RECT 31.055 11.305 31.225 11.475 ;
+      RECT 30.965 10.285 31.135 10.455 ;
+      RECT 28.665 10.285 28.835 10.455 ;
+    LAYER via ;
+      RECT 80.885 108.725 81.035 108.875 ;
+      RECT 51.445 108.725 51.595 108.875 ;
+      RECT 42.475 98.355 42.625 98.505 ;
+      RECT 34.195 98.355 34.345 98.505 ;
+      RECT 10.965 97.845 11.115 97.995 ;
+      RECT 39.715 97.335 39.865 97.485 ;
+      RECT 29.595 97.335 29.745 97.485 ;
+      RECT 40.635 11.315 40.785 11.465 ;
+      RECT 37.875 11.315 38.025 11.465 ;
+      RECT 30.975 11.315 31.125 11.465 ;
+      RECT 10.965 10.805 11.115 10.955 ;
+      RECT 31.895 10.295 32.045 10.445 ;
+      RECT 28.675 10.295 28.825 10.445 ;
+      RECT 80.885 -0.075 81.035 0.075 ;
+      RECT 51.445 -0.075 51.595 0.075 ;
+    LAYER via2 ;
+      RECT 80.86 108.7 81.06 108.9 ;
+      RECT 51.42 108.7 51.62 108.9 ;
+      RECT 10.94 97.82 11.14 98.02 ;
+      RECT 10.94 10.78 11.14 10.98 ;
+      RECT 80.86 -0.1 81.06 0.1 ;
+      RECT 51.42 -0.1 51.62 0.1 ;
+    LAYER via3 ;
+      RECT 80.86 108.7 81.06 108.9 ;
+      RECT 51.42 108.7 51.62 108.9 ;
+      RECT 10.94 97.82 11.14 98.02 ;
+      RECT 10.94 10.78 11.14 10.98 ;
+      RECT 80.86 -0.1 81.06 0.1 ;
+      RECT 51.42 -0.1 51.62 0.1 ;
+    LAYER OVERLAP ;
+      POLYGON 25.76 0 25.76 10.88 0 10.88 0 97.92 25.76 97.92 25.76 108.8 92 108.8 92 0 ;
+  END
+END sb_2__1_
+
+END LIBRARY
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef
new file mode 100644
index 0000000..9f43a41
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef
@@ -0,0 +1,1426 @@
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+
+UNITS
+  DATABASE MICRONS 1000 ;
+END UNITS
+
+MANUFACTURINGGRID 0.005 ;
+
+LAYER li1
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.17 ;
+END li1
+
+LAYER mcon
+  TYPE CUT ;
+END mcon
+
+LAYER met1
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.34 ;
+  WIDTH 0.14 ;
+END met1
+
+LAYER via
+  TYPE CUT ;
+END via
+
+LAYER met2
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.14 ;
+END met2
+
+LAYER via2
+  TYPE CUT ;
+END via2
+
+LAYER met3
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.68 ;
+  WIDTH 0.3 ;
+END met3
+
+LAYER via3
+  TYPE CUT ;
+END via3
+
+LAYER met4
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.92 ;
+  WIDTH 0.3 ;
+END met4
+
+LAYER via4
+  TYPE CUT ;
+END via4
+
+LAYER met5
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 3.4 ;
+  WIDTH 1.6 ;
+END met5
+
+LAYER nwell
+  TYPE MASTERSLICE ;
+END nwell
+
+LAYER pwell
+  TYPE MASTERSLICE ;
+END pwell
+
+LAYER OVERLAP
+  TYPE OVERLAP ;
+END OVERLAP
+
+VIA L1M1_PR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR
+
+VIA L1M1_PR_R
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_R
+
+VIA L1M1_PR_M
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_M
+
+VIA L1M1_PR_MR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR_MR
+
+VIA L1M1_PR_C
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.145 0.145 0.145 ;
+END L1M1_PR_C
+
+VIA M1M2_PR
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR
+
+VIA M1M2_PR_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_Enc
+
+VIA M1M2_PR_R
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_R
+
+VIA M1M2_PR_R_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_R_Enc
+
+VIA M1M2_PR_M
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIA M1M2_PR_M_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_M_Enc
+
+VIA M1M2_PR_MR
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIA M1M2_PR_MR_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_MR_Enc
+
+VIA M1M2_PR_C
+  LAYER met1 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIA M2M3_PR
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIA M2M3_PR_R
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIA M2M3_PR_M
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIA M2M3_PR_MR
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIA M2M3_PR_C
+  LAYER met2 ;
+    RECT -0.185 -0.185 0.185 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIA M3M4_PR
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIA M3M4_PR_R
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIA M3M4_PR_M
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIA M3M4_PR_MR
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIA M3M4_PR_C
+  LAYER met3 ;
+    RECT -0.19 -0.19 0.19 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIA M4M5_PR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIA M4M5_PR_R
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIA M4M5_PR_M
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIA M4M5_PR_MR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIA M4M5_PR_C
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+  CLASS CORE ;
+  SYMMETRY Y ;
+  SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+  CLASS CORE ;
+  SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+MACRO sb_2__2_
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 92 BY 97.92 ;
+  SYMMETRY X Y ;
+  PIN chany_bottom_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 70.08 0 70.22 0.485 ;
+    END
+  END chany_bottom_in[0]
+  PIN chany_bottom_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 81.58 0 81.72 0.485 ;
+    END
+  END chany_bottom_in[1]
+  PIN chany_bottom_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 57.2 0 57.34 0.485 ;
+    END
+  END chany_bottom_in[2]
+  PIN chany_bottom_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 80.2 0 80.34 0.485 ;
+    END
+  END chany_bottom_in[3]
+  PIN chany_bottom_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 64.56 0 64.7 0.485 ;
+    END
+  END chany_bottom_in[4]
+  PIN chany_bottom_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 76.52 0 76.66 0.485 ;
+    END
+  END chany_bottom_in[5]
+  PIN chany_bottom_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 55.36 0 55.5 0.485 ;
+    END
+  END chany_bottom_in[6]
+  PIN chany_bottom_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 73.76 0 73.9 0.485 ;
+    END
+  END chany_bottom_in[7]
+  PIN chany_bottom_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 63.64 0 63.78 0.485 ;
+    END
+  END chany_bottom_in[8]
+  PIN chany_bottom_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 69.16 0 69.3 0.485 ;
+    END
+  END chany_bottom_in[9]
+  PIN chany_bottom_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.14 0 52.28 0.485 ;
+    END
+  END chany_bottom_in[10]
+  PIN chany_bottom_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 71 0 71.14 0.485 ;
+    END
+  END chany_bottom_in[11]
+  PIN chany_bottom_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 75.6 0 75.74 0.485 ;
+    END
+  END chany_bottom_in[12]
+  PIN chany_bottom_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 78.36 0 78.5 0.485 ;
+    END
+  END chany_bottom_in[13]
+  PIN chany_bottom_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 54.44 0 54.58 0.485 ;
+    END
+  END chany_bottom_in[14]
+  PIN chany_bottom_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 66.4 0 66.54 0.485 ;
+    END
+  END chany_bottom_in[15]
+  PIN chany_bottom_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 47.08 0 47.22 0.485 ;
+    END
+  END chany_bottom_in[16]
+  PIN chany_bottom_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 77.44 0 77.58 0.485 ;
+    END
+  END chany_bottom_in[17]
+  PIN chany_bottom_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 53.06 0 53.2 0.485 ;
+    END
+  END chany_bottom_in[18]
+  PIN chany_bottom_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 79.28 0 79.42 0.485 ;
+    END
+  END chany_bottom_in[19]
+  PIN bottom_right_grid_pin_1_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 32.36 0 32.5 0.485 ;
+    END
+  END bottom_right_grid_pin_1_[0]
+  PIN bottom_left_grid_pin_42_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 14.42 10.88 14.56 11.365 ;
+    END
+  END bottom_left_grid_pin_42_[0]
+  PIN bottom_left_grid_pin_43_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 15.34 10.88 15.48 11.365 ;
+    END
+  END bottom_left_grid_pin_43_[0]
+  PIN bottom_left_grid_pin_44_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 2.92 10.88 3.06 11.365 ;
+    END
+  END bottom_left_grid_pin_44_[0]
+  PIN bottom_left_grid_pin_45_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 10.28 10.88 10.42 11.365 ;
+    END
+  END bottom_left_grid_pin_45_[0]
+  PIN bottom_left_grid_pin_46_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 5.22 10.88 5.36 11.365 ;
+    END
+  END bottom_left_grid_pin_46_[0]
+  PIN bottom_left_grid_pin_47_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 4.3 10.88 4.44 11.365 ;
+    END
+  END bottom_left_grid_pin_47_[0]
+  PIN bottom_left_grid_pin_48_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 13.5 10.88 13.64 11.365 ;
+    END
+  END bottom_left_grid_pin_48_[0]
+  PIN bottom_left_grid_pin_49_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.06 10.88 7.2 11.365 ;
+    END
+  END bottom_left_grid_pin_49_[0]
+  PIN chanx_left_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 66.83 0.8 67.13 ;
+    END
+  END chanx_left_in[0]
+  PIN chanx_left_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 52.55 0.8 52.85 ;
+    END
+  END chanx_left_in[1]
+  PIN chanx_left_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 60.71 0.8 61.01 ;
+    END
+  END chanx_left_in[2]
+  PIN chanx_left_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 45.75 0.8 46.05 ;
+    END
+  END chanx_left_in[3]
+  PIN chanx_left_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 48.47 0.8 48.77 ;
+    END
+  END chanx_left_in[4]
+  PIN chanx_left_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 56.63 0.8 56.93 ;
+    END
+  END chanx_left_in[5]
+  PIN chanx_left_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 68.19 0.8 68.49 ;
+    END
+  END chanx_left_in[6]
+  PIN chanx_left_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 65.47 0.8 65.77 ;
+    END
+  END chanx_left_in[7]
+  PIN chanx_left_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 49.83 0.8 50.13 ;
+    END
+  END chanx_left_in[8]
+  PIN chanx_left_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 59.35 0.8 59.65 ;
+    END
+  END chanx_left_in[9]
+  PIN chanx_left_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 64.11 0.8 64.41 ;
+    END
+  END chanx_left_in[10]
+  PIN chanx_left_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 47.11 0.8 47.41 ;
+    END
+  END chanx_left_in[11]
+  PIN chanx_left_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 55.27 0.8 55.57 ;
+    END
+  END chanx_left_in[12]
+  PIN chanx_left_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 23.31 0.8 23.61 ;
+    END
+  END chanx_left_in[13]
+  PIN chanx_left_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 57.99 0.8 58.29 ;
+    END
+  END chanx_left_in[14]
+  PIN chanx_left_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 40.31 0.8 40.61 ;
+    END
+  END chanx_left_in[15]
+  PIN chanx_left_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 37.59 0.8 37.89 ;
+    END
+  END chanx_left_in[16]
+  PIN chanx_left_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 27.39 0.8 27.69 ;
+    END
+  END chanx_left_in[17]
+  PIN chanx_left_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 74.31 0.8 74.61 ;
+    END
+  END chanx_left_in[18]
+  PIN chanx_left_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 32.83 0.8 33.13 ;
+    END
+  END chanx_left_in[19]
+  PIN left_top_grid_pin_1_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 20.59 0.8 20.89 ;
+    END
+  END left_top_grid_pin_1_[0]
+  PIN left_bottom_grid_pin_34_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 6.75 10.88 7.05 11.68 ;
+    END
+  END left_bottom_grid_pin_34_[0]
+  PIN left_bottom_grid_pin_35_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 8.59 10.88 8.89 11.68 ;
+    END
+  END left_bottom_grid_pin_35_[0]
+  PIN left_bottom_grid_pin_36_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 8.9 10.88 9.04 11.365 ;
+    END
+  END left_bottom_grid_pin_36_[0]
+  PIN left_bottom_grid_pin_37_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 7.98 10.88 8.12 11.365 ;
+    END
+  END left_bottom_grid_pin_37_[0]
+  PIN left_bottom_grid_pin_38_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 11.66 10.88 11.8 11.365 ;
+    END
+  END left_bottom_grid_pin_38_[0]
+  PIN left_bottom_grid_pin_39_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 12.58 10.88 12.72 11.365 ;
+    END
+  END left_bottom_grid_pin_39_[0]
+  PIN left_bottom_grid_pin_40_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 28.22 0 28.36 0.485 ;
+    END
+  END left_bottom_grid_pin_40_[0]
+  PIN left_bottom_grid_pin_41_[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 6.14 10.88 6.28 11.365 ;
+    END
+  END left_bottom_grid_pin_41_[0]
+  PIN ccff_head[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 91.2 94.03 92 94.33 ;
+    END
+  END ccff_head[0]
+  PIN chany_bottom_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 38.34 0 38.48 0.485 ;
+    END
+  END chany_bottom_out[0]
+  PIN chany_bottom_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 74.68 0 74.82 0.485 ;
+    END
+  END chany_bottom_out[1]
+  PIN chany_bottom_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 31.44 0 31.58 0.485 ;
+    END
+  END chany_bottom_out[2]
+  PIN chany_bottom_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 62.26 0 62.4 0.485 ;
+    END
+  END chany_bottom_out[3]
+  PIN chany_bottom_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 65.48 0 65.62 0.485 ;
+    END
+  END chany_bottom_out[4]
+  PIN chany_bottom_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 49.38 0 49.52 0.485 ;
+    END
+  END chany_bottom_out[5]
+  PIN chany_bottom_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 67.32 0 67.46 0.485 ;
+    END
+  END chany_bottom_out[6]
+  PIN chany_bottom_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 68.24 0 68.38 0.485 ;
+    END
+  END chany_bottom_out[7]
+  PIN chany_bottom_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.04 0 59.18 0.485 ;
+    END
+  END chany_bottom_out[8]
+  PIN chany_bottom_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 50.3 0 50.44 0.485 ;
+    END
+  END chany_bottom_out[9]
+  PIN chany_bottom_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 35.12 0 35.26 0.485 ;
+    END
+  END chany_bottom_out[10]
+  PIN chany_bottom_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 61.34 0 61.48 0.485 ;
+    END
+  END chany_bottom_out[11]
+  PIN chany_bottom_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 59.96 0 60.1 0.485 ;
+    END
+  END chany_bottom_out[12]
+  PIN chany_bottom_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 82.5 0 82.64 0.485 ;
+    END
+  END chany_bottom_out[13]
+  PIN chany_bottom_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 56.28 0 56.42 0.485 ;
+    END
+  END chany_bottom_out[14]
+  PIN chany_bottom_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 58.12 0 58.26 0.485 ;
+    END
+  END chany_bottom_out[15]
+  PIN chany_bottom_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 48 0 48.14 0.485 ;
+    END
+  END chany_bottom_out[16]
+  PIN chany_bottom_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 72.84 0 72.98 0.485 ;
+    END
+  END chany_bottom_out[17]
+  PIN chany_bottom_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 33.74 0 33.88 0.485 ;
+    END
+  END chany_bottom_out[18]
+  PIN chany_bottom_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 71.92 0 72.06 0.485 ;
+    END
+  END chany_bottom_out[19]
+  PIN chanx_left_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 72.95 0.8 73.25 ;
+    END
+  END chanx_left_out[0]
+  PIN chanx_left_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 71.59 0.8 71.89 ;
+    END
+  END chanx_left_out[1]
+  PIN chanx_left_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 90.63 0.8 90.93 ;
+    END
+  END chanx_left_out[2]
+  PIN chanx_left_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 69.55 0.8 69.85 ;
+    END
+  END chanx_left_out[3]
+  PIN chanx_left_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 41.67 0.8 41.97 ;
+    END
+  END chanx_left_out[4]
+  PIN chanx_left_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 29.43 0.8 29.73 ;
+    END
+  END chanx_left_out[5]
+  PIN chanx_left_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 51.19 0.8 51.49 ;
+    END
+  END chanx_left_out[6]
+  PIN chanx_left_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 26.03 0.8 26.33 ;
+    END
+  END chanx_left_out[7]
+  PIN chanx_left_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 31.47 0.8 31.77 ;
+    END
+  END chanx_left_out[8]
+  PIN chanx_left_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 34.19 0.8 34.49 ;
+    END
+  END chanx_left_out[9]
+  PIN chanx_left_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 44.39 0.8 44.69 ;
+    END
+  END chanx_left_out[10]
+  PIN chanx_left_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 21.95 0.8 22.25 ;
+    END
+  END chanx_left_out[11]
+  PIN chanx_left_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 38.95 0.8 39.25 ;
+    END
+  END chanx_left_out[12]
+  PIN chanx_left_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 15.83 0.8 16.13 ;
+    END
+  END chanx_left_out[13]
+  PIN chanx_left_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 53.91 0.8 54.21 ;
+    END
+  END chanx_left_out[14]
+  PIN chanx_left_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 24.67 0.8 24.97 ;
+    END
+  END chanx_left_out[15]
+  PIN chanx_left_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 17.19 0.8 17.49 ;
+    END
+  END chanx_left_out[16]
+  PIN chanx_left_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 18.55 0.8 18.85 ;
+    END
+  END chanx_left_out[17]
+  PIN chanx_left_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 62.75 0.8 63.05 ;
+    END
+  END chanx_left_out[18]
+  PIN chanx_left_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 35.55 0.8 35.85 ;
+    END
+  END chanx_left_out[19]
+  PIN ccff_tail[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 43.03 0.8 43.33 ;
+    END
+  END ccff_tail[0]
+  PIN SC_IN_BOT
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0 14.47 0.8 14.77 ;
+    END
+  END SC_IN_BOT
+  PIN SC_OUT_BOT
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 23.16 10.88 23.3 11.365 ;
+    END
+  END SC_OUT_BOT
+  PIN prog_clk_0_S_in
+    DIRECTION INPUT ;
+    USE CLOCK ;
+    PORT
+      LAYER met2 ;
+        RECT 39.26 0 39.4 0.485 ;
+    END
+  END prog_clk_0_S_in
+  PIN VDD
+    DIRECTION INPUT ;
+    USE POWER ;
+    PORT
+      LAYER met5 ;
+        RECT 0 22.2 3.2 25.4 ;
+        RECT 88.8 22.2 92 25.4 ;
+        RECT 0 63 3.2 66.2 ;
+        RECT 88.8 63 92 66.2 ;
+      LAYER met4 ;
+        RECT 36.5 0 37.1 0.6 ;
+        RECT 65.94 0 66.54 0.6 ;
+        RECT 36.5 97.32 37.1 97.92 ;
+        RECT 65.94 97.32 66.54 97.92 ;
+      LAYER met1 ;
+        RECT 25.76 2.48 26.24 2.96 ;
+        RECT 91.52 2.48 92 2.96 ;
+        RECT 25.76 7.92 26.24 8.4 ;
+        RECT 91.52 7.92 92 8.4 ;
+        RECT 0 13.36 0.48 13.84 ;
+        RECT 91.52 13.36 92 13.84 ;
+        RECT 0 18.8 0.48 19.28 ;
+        RECT 91.52 18.8 92 19.28 ;
+        RECT 0 24.24 0.48 24.72 ;
+        RECT 91.52 24.24 92 24.72 ;
+        RECT 0 29.68 0.48 30.16 ;
+        RECT 91.52 29.68 92 30.16 ;
+        RECT 0 35.12 0.48 35.6 ;
+        RECT 91.52 35.12 92 35.6 ;
+        RECT 0 40.56 0.48 41.04 ;
+        RECT 91.52 40.56 92 41.04 ;
+        RECT 0 46 0.48 46.48 ;
+        RECT 91.52 46 92 46.48 ;
+        RECT 0 51.44 0.48 51.92 ;
+        RECT 91.52 51.44 92 51.92 ;
+        RECT 0 56.88 0.48 57.36 ;
+        RECT 91.52 56.88 92 57.36 ;
+        RECT 0 62.32 0.48 62.8 ;
+        RECT 91.52 62.32 92 62.8 ;
+        RECT 0 67.76 0.48 68.24 ;
+        RECT 91.52 67.76 92 68.24 ;
+        RECT 0 73.2 0.48 73.68 ;
+        RECT 91.52 73.2 92 73.68 ;
+        RECT 0 78.64 0.48 79.12 ;
+        RECT 91.52 78.64 92 79.12 ;
+        RECT 0 84.08 0.48 84.56 ;
+        RECT 91.52 84.08 92 84.56 ;
+        RECT 0 89.52 0.48 90 ;
+        RECT 91.52 89.52 92 90 ;
+        RECT 0 94.96 0.48 95.44 ;
+        RECT 91.52 94.96 92 95.44 ;
+    END
+  END VDD
+  PIN VSS
+    DIRECTION INPUT ;
+    USE GROUND ;
+    PORT
+      LAYER met4 ;
+        RECT 51.22 0 51.82 0.6 ;
+        RECT 80.66 0 81.26 0.6 ;
+        RECT 10.74 10.88 11.34 11.48 ;
+        RECT 10.74 97.32 11.34 97.92 ;
+        RECT 51.22 97.32 51.82 97.92 ;
+        RECT 80.66 97.32 81.26 97.92 ;
+      LAYER met5 ;
+        RECT 0 42.6 3.2 45.8 ;
+        RECT 88.8 42.6 92 45.8 ;
+        RECT 0 83.4 3.2 86.6 ;
+        RECT 88.8 83.4 92 86.6 ;
+      LAYER met1 ;
+        RECT 25.76 0 45.4 0.24 ;
+        RECT 46.6 0 92 0.24 ;
+        RECT 25.76 5.2 26.24 5.68 ;
+        RECT 91.52 5.2 92 5.68 ;
+        RECT 0 10.64 45.4 11.12 ;
+        RECT 91.52 10.64 92 11.12 ;
+        RECT 0 16.08 0.48 16.56 ;
+        RECT 91.52 16.08 92 16.56 ;
+        RECT 0 21.52 0.48 22 ;
+        RECT 91.52 21.52 92 22 ;
+        RECT 0 26.96 0.48 27.44 ;
+        RECT 91.52 26.96 92 27.44 ;
+        RECT 0 32.4 0.48 32.88 ;
+        RECT 91.52 32.4 92 32.88 ;
+        RECT 0 37.84 0.48 38.32 ;
+        RECT 91.52 37.84 92 38.32 ;
+        RECT 0 43.28 0.48 43.76 ;
+        RECT 91.52 43.28 92 43.76 ;
+        RECT 0 48.72 0.48 49.2 ;
+        RECT 91.52 48.72 92 49.2 ;
+        RECT 0 54.16 0.48 54.64 ;
+        RECT 91.52 54.16 92 54.64 ;
+        RECT 0 59.6 0.48 60.08 ;
+        RECT 91.52 59.6 92 60.08 ;
+        RECT 0 65.04 0.48 65.52 ;
+        RECT 91.52 65.04 92 65.52 ;
+        RECT 0 70.48 0.48 70.96 ;
+        RECT 91.52 70.48 92 70.96 ;
+        RECT 0 75.92 0.48 76.4 ;
+        RECT 91.52 75.92 92 76.4 ;
+        RECT 0 81.36 0.48 81.84 ;
+        RECT 91.52 81.36 92 81.84 ;
+        RECT 0 86.8 0.48 87.28 ;
+        RECT 91.52 86.8 92 87.28 ;
+        RECT 0 92.24 0.48 92.72 ;
+        RECT 91.52 92.24 92 92.72 ;
+        RECT 0 97.68 45.4 97.92 ;
+        RECT 46.6 97.68 92 97.92 ;
+    END
+  END VSS
+  OBS
+    LAYER met2 ;
+      RECT 80.82 97.735 81.1 98.105 ;
+      RECT 51.38 97.735 51.66 98.105 ;
+      RECT 10.9 97.735 11.18 98.105 ;
+      RECT 10.9 10.695 11.18 11.065 ;
+      RECT 80.82 -0.185 81.1 0.185 ;
+      RECT 51.38 -0.185 51.66 0.185 ;
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diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v
new file mode 100644
index 0000000..f10c6db
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v
@@ -0,0 +1,2002 @@
+//
+//
+//
+//
+//
+//
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_124 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_124 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_119 ) , 
+    .X ( copt_net_118 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_124 ) , 
+    .X ( copt_net_119 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_118 ) , 
+    .X ( copt_net_120 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_122 ) , 
+    .X ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_123 ) , 
+    .X ( copt_net_122 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_120 ) , 
+    .X ( copt_net_123 ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_511_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_511_ ) , 
+    .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_88 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( BUF_net_88 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_511_ ) , 
+    .Y ( BUF_net_90 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_112 ( .A ( BUF_net_90 ) , .Y ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head , 
+    iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_7 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_85 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_85 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_85 ( .A ( BUF_net_87 ) , .Y ( BUF_net_85 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_510_ ) , 
+    .Y ( BUF_net_87 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_87 ) , .Y ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_7 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_7 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_7 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__7 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_6 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_509_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_82 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_82 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( BUF_net_82 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_509_ ) , 
+    .Y ( BUF_net_84 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_6 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_6 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_6 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__6 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_5 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_508_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_508_ ) , 
+    .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_508_ ) , 
+    .Y ( BUF_net_81 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_5 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_5 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_5 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__5 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_507_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_76 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_76 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_76 ( .A ( BUF_net_78 ) , .Y ( BUF_net_76 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( aps_rename_507_ ) , 
+    .Y ( BUF_net_78 ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_4 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_4 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__4 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_73 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_73 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_73 ( .A ( BUF_net_75 ) , .Y ( BUF_net_73 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_75 ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_3 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_3 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__3 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_184_0 ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+input  ZBUF_184_0 ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( ZBUF_184_0 ) , .Z ( SOC_OUT ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_184_0 ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input  ZBUF_184_0 ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .ZBUF_184_0 ( ZBUF_184_0 ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail , ZBUF_184_0 ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input  ZBUF_184_0 ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , 
+    .ZBUF_184_0 ( ZBUF_184_0 ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_70 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_70 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_70 ( .A ( BUF_net_72 ) , .Y ( BUF_net_70 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_72 ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_1 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_1 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__1 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( net_net_69 ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__buf_8 BUFT_RR_69 ( .A ( net_net_69 ) , .X ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_0 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_0 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__0 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__const1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__0__const1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_105 ) ) ;
+endmodule
+
+
+module cbx_1__0__const1_7 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__0__const1_7 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_103 ) ) ;
+endmodule
+
+
+module cbx_1__0__const1_6 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__0__const1_6 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__const1_5 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__0__const1_5 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_100 ) ) ;
+endmodule
+
+
+module cbx_1__0__const1_4 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__0__const1_4 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__const1_3 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__0__const1_3 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_97 ) ) ;
+endmodule
+
+
+module cbx_1__0__const1_2 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__0__const1_2 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_95 ) ) ;
+endmodule
+
+
+module cbx_1__0__const1_1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__0__const1_1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_93 ) ) ;
+endmodule
+
+
+module cbx_1__0__const1_0 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__0__const1_0 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0_ ( chanx_left_in , chanx_right_in , ccff_head , 
+    chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , 
+    bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , 
+    bottom_grid_pin_8_ , bottom_grid_pin_10_ , bottom_grid_pin_12_ , 
+    bottom_grid_pin_14_ , bottom_grid_pin_16_ , ccff_tail , IO_ISOL_N , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , top_width_0_height_0__pin_0_ , 
+    top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , 
+    top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , 
+    top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_12_ , 
+    top_width_0_height_0__pin_14_ , top_width_0_height_0__pin_16_ , 
+    top_width_0_height_0__pin_1_upper , top_width_0_height_0__pin_1_lower , 
+    top_width_0_height_0__pin_3_upper , top_width_0_height_0__pin_3_lower , 
+    top_width_0_height_0__pin_5_upper , top_width_0_height_0__pin_5_lower , 
+    top_width_0_height_0__pin_7_upper , top_width_0_height_0__pin_7_lower , 
+    top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , 
+    top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , 
+    top_width_0_height_0__pin_13_upper , top_width_0_height_0__pin_13_lower , 
+    top_width_0_height_0__pin_15_upper , top_width_0_height_0__pin_15_lower , 
+    top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower , 
+    SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , prog_clk_0_N_in , 
+    prog_clk_0_W_out ) ;
+input  [0:19] chanx_left_in ;
+input  [0:19] chanx_right_in ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_16_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] top_width_0_height_0__pin_0_ ;
+input  [0:0] top_width_0_height_0__pin_2_ ;
+input  [0:0] top_width_0_height_0__pin_4_ ;
+input  [0:0] top_width_0_height_0__pin_6_ ;
+input  [0:0] top_width_0_height_0__pin_8_ ;
+input  [0:0] top_width_0_height_0__pin_10_ ;
+input  [0:0] top_width_0_height_0__pin_12_ ;
+input  [0:0] top_width_0_height_0__pin_14_ ;
+input  [0:0] top_width_0_height_0__pin_16_ ;
+output [0:0] top_width_0_height_0__pin_1_upper ;
+output [0:0] top_width_0_height_0__pin_1_lower ;
+output [0:0] top_width_0_height_0__pin_3_upper ;
+output [0:0] top_width_0_height_0__pin_3_lower ;
+output [0:0] top_width_0_height_0__pin_5_upper ;
+output [0:0] top_width_0_height_0__pin_5_lower ;
+output [0:0] top_width_0_height_0__pin_7_upper ;
+output [0:0] top_width_0_height_0__pin_7_lower ;
+output [0:0] top_width_0_height_0__pin_9_upper ;
+output [0:0] top_width_0_height_0__pin_9_lower ;
+output [0:0] top_width_0_height_0__pin_11_upper ;
+output [0:0] top_width_0_height_0__pin_11_lower ;
+output [0:0] top_width_0_height_0__pin_13_upper ;
+output [0:0] top_width_0_height_0__pin_13_lower ;
+output [0:0] top_width_0_height_0__pin_15_upper ;
+output [0:0] top_width_0_height_0__pin_15_lower ;
+output [0:0] top_width_0_height_0__pin_17_upper ;
+output [0:0] top_width_0_height_0__pin_17_lower ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  SC_IN_BOT ;
+output SC_OUT_TOP ;
+input  prog_clk_0_N_in ;
+output prog_clk_0_W_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__0_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__1_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__2_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__3_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__4_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__5_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__6_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_115 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_115 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] , 
+        chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_116 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[9] , chanx_left_out[9] , chanx_right_out[15] , 
+        chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_116 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_115 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .io_outpad ( top_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( top_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) , 
+    .io_outpad ( top_width_0_height_0__pin_2_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_3_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) ,
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_512_ } ) ,
+    .io_outpad ( top_width_0_height_0__pin_4_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_5_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , 
+    .ZBUF_184_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ;
+cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) , 
+    .io_outpad ( top_width_0_height_0__pin_6_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_7_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) , 
+    .io_outpad ( top_width_0_height_0__pin_8_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_9_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) , 
+    .io_outpad ( top_width_0_height_0__pin_10_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_11_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) , 
+    .io_outpad ( top_width_0_height_0__pin_12_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_13_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) , 
+    .io_outpad ( top_width_0_height_0__pin_14_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_15_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) , 
+    .io_outpad ( top_width_0_height_0__pin_16_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_17_lower ) , 
+    .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , 
+    .X ( ctsbuf_net_1117 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , 
+    .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , 
+    .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) , 
+    .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) , 
+    .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[7] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[11] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[15] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[19] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( 
+    .A ( top_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 ( 
+    .A ( top_width_0_height_0__pin_3_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_3_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( 
+    .A ( top_width_0_height_0__pin_5_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_5_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_62__61 ( 
+    .A ( top_width_0_height_0__pin_7_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_7_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_63__62 ( 
+    .A ( top_width_0_height_0__pin_9_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_9_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_64__63 ( 
+    .A ( top_width_0_height_0__pin_11_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_11_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_65__64 ( 
+    .A ( top_width_0_height_0__pin_13_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_13_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_66__65 ( 
+    .A ( top_width_0_height_0__pin_15_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_15_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_67__66 ( 
+    .A ( top_width_0_height_0__pin_17_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_17_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , 
+    .HI ( optlc_net_114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , 
+    .HI ( optlc_net_115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , 
+    .HI ( optlc_net_116 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_184_inst_121 ( .A ( aps_rename_512_ ) , 
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ;
+sky130_fd_sc_hd__clkbuf_8 cts_buf_3521248 ( .A ( ctsbuf_net_1117 ) , 
+    .X ( prog_clk_0_W_out ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v
new file mode 100644
index 0000000..a216339
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v
@@ -0,0 +1,2320 @@
+//
+//
+//
+//
+//
+//
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+wire copt_net_124 ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_124 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_119 ) , 
+    .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_124 ) , 
+    .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_118 ) , 
+    .X ( copt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_122 ) , 
+    .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_123 ) , 
+    .X ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_120 ) , 
+    .X ( copt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_511_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_511_ ) , 
+    .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_88 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( BUF_net_88 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_511_ ) , 
+    .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_112 ( .A ( BUF_net_90 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head , 
+    iopad_inpad , ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_7 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_85 ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_85 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_85 ( .A ( BUF_net_87 ) , .Y ( BUF_net_85 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_510_ ) , 
+    .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_87 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_7 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__EMBEDDED_IO_HD_7 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_7 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__7 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_6 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_509_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_82 ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_82 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( BUF_net_82 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_509_ ) , 
+    .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_6 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__EMBEDDED_IO_HD_6 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_6 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__6 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_5 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_508_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_508_ ) , 
+    .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_508_ ) , 
+    .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_5 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__EMBEDDED_IO_HD_5 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_5 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__5 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_507_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_76 ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_76 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_76 ( .A ( BUF_net_78 ) , .Y ( BUF_net_76 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( aps_rename_507_ ) , 
+    .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__EMBEDDED_IO_HD_4 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_4 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__4 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_73 ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_73 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_73 ( .A ( BUF_net_75 ) , .Y ( BUF_net_73 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__EMBEDDED_IO_HD_3 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_3 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__3 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS , ZBUF_184_0 ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+input  ZBUF_184_0 ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( ZBUF_184_0 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS , 
+    ZBUF_184_0 ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+input  ZBUF_184_0 ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) , .ZBUF_184_0 ( ZBUF_184_0 ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail , VDD , VSS , ZBUF_184_0 ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+input  ZBUF_184_0 ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .ZBUF_184_0 ( ZBUF_184_0 ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_70 ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_70 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_70 ( .A ( BUF_net_72 ) , .Y ( BUF_net_70 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__EMBEDDED_IO_HD_1 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_1 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__1 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( net_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 BUFT_RR_69 ( .A ( net_net_69 ) , .X ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__EMBEDDED_IO_HD_0 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_0 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__0 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__0_ ( chanx_left_in , chanx_right_in , ccff_head , 
+    chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , 
+    bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , 
+    bottom_grid_pin_8_ , bottom_grid_pin_10_ , bottom_grid_pin_12_ , 
+    bottom_grid_pin_14_ , bottom_grid_pin_16_ , ccff_tail , IO_ISOL_N , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , top_width_0_height_0__pin_0_ , 
+    top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , 
+    top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , 
+    top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_12_ , 
+    top_width_0_height_0__pin_14_ , top_width_0_height_0__pin_16_ , 
+    top_width_0_height_0__pin_1_upper , top_width_0_height_0__pin_1_lower , 
+    top_width_0_height_0__pin_3_upper , top_width_0_height_0__pin_3_lower , 
+    top_width_0_height_0__pin_5_upper , top_width_0_height_0__pin_5_lower , 
+    top_width_0_height_0__pin_7_upper , top_width_0_height_0__pin_7_lower , 
+    top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , 
+    top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , 
+    top_width_0_height_0__pin_13_upper , top_width_0_height_0__pin_13_lower , 
+    top_width_0_height_0__pin_15_upper , top_width_0_height_0__pin_15_lower , 
+    top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower , 
+    SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , prog_clk_0_N_in , 
+    prog_clk_0_W_out , VDD , VSS ) ;
+input  [0:19] chanx_left_in ;
+input  [0:19] chanx_right_in ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_16_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] top_width_0_height_0__pin_0_ ;
+input  [0:0] top_width_0_height_0__pin_2_ ;
+input  [0:0] top_width_0_height_0__pin_4_ ;
+input  [0:0] top_width_0_height_0__pin_6_ ;
+input  [0:0] top_width_0_height_0__pin_8_ ;
+input  [0:0] top_width_0_height_0__pin_10_ ;
+input  [0:0] top_width_0_height_0__pin_12_ ;
+input  [0:0] top_width_0_height_0__pin_14_ ;
+input  [0:0] top_width_0_height_0__pin_16_ ;
+output [0:0] top_width_0_height_0__pin_1_upper ;
+output [0:0] top_width_0_height_0__pin_1_lower ;
+output [0:0] top_width_0_height_0__pin_3_upper ;
+output [0:0] top_width_0_height_0__pin_3_lower ;
+output [0:0] top_width_0_height_0__pin_5_upper ;
+output [0:0] top_width_0_height_0__pin_5_lower ;
+output [0:0] top_width_0_height_0__pin_7_upper ;
+output [0:0] top_width_0_height_0__pin_7_lower ;
+output [0:0] top_width_0_height_0__pin_9_upper ;
+output [0:0] top_width_0_height_0__pin_9_lower ;
+output [0:0] top_width_0_height_0__pin_11_upper ;
+output [0:0] top_width_0_height_0__pin_11_lower ;
+output [0:0] top_width_0_height_0__pin_13_upper ;
+output [0:0] top_width_0_height_0__pin_13_lower ;
+output [0:0] top_width_0_height_0__pin_15_upper ;
+output [0:0] top_width_0_height_0__pin_15_lower ;
+output [0:0] top_width_0_height_0__pin_17_upper ;
+output [0:0] top_width_0_height_0__pin_17_lower ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  SC_IN_BOT ;
+output SC_OUT_TOP ;
+input  prog_clk_0_N_in ;
+output prog_clk_0_W_out ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__0_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__1_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__2_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__3_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__4_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__5_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__6_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__7_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_115 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_115 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] , 
+        chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_116 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[9] , chanx_left_out[9] , chanx_right_out[15] , 
+        chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_116 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( bottom_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_115 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .io_outpad ( top_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( top_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) , 
+    .io_outpad ( top_width_0_height_0__pin_2_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_3_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) ,
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_512_ } ) ,
+    .io_outpad ( top_width_0_height_0__pin_4_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_5_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .ZBUF_184_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ;
+cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) , 
+    .io_outpad ( top_width_0_height_0__pin_6_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_7_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) , 
+    .io_outpad ( top_width_0_height_0__pin_8_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_9_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) , 
+    .io_outpad ( top_width_0_height_0__pin_10_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_11_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) , 
+    .io_outpad ( top_width_0_height_0__pin_12_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_13_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) , 
+    .io_outpad ( top_width_0_height_0__pin_14_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_15_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) , 
+    .io_outpad ( top_width_0_height_0__pin_16_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_17_lower ) , 
+    .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , 
+    .X ( ctsbuf_net_1117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , 
+    .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , 
+    .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , 
+    .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , 
+    .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , 
+    .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , 
+    .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , 
+    .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) , 
+    .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) , 
+    .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) , 
+    .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[7] ) , 
+    .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[11] ) , 
+    .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[15] ) , 
+    .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[19] ) , 
+    .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( 
+    .A ( top_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 ( 
+    .A ( top_width_0_height_0__pin_3_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_3_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( 
+    .A ( top_width_0_height_0__pin_5_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_5_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_62__61 ( 
+    .A ( top_width_0_height_0__pin_7_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_7_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_63__62 ( 
+    .A ( top_width_0_height_0__pin_9_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_9_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_64__63 ( 
+    .A ( top_width_0_height_0__pin_11_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_11_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_65__64 ( 
+    .A ( top_width_0_height_0__pin_13_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_13_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_66__65 ( 
+    .A ( top_width_0_height_0__pin_15_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_15_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_67__66 ( 
+    .A ( top_width_0_height_0__pin_17_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_17_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , 
+    .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , 
+    .HI ( optlc_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , 
+    .HI ( optlc_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_184_inst_121 ( .A ( aps_rename_512_ ) , 
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkbuf_8 cts_buf_3521248 ( .A ( ctsbuf_net_1117 ) , 
+    .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v
new file mode 100644
index 0000000..cfe07fe
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v
@@ -0,0 +1,1903 @@
+//
+//
+//
+//
+//
+//
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_124 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_124 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_119 ) , 
+    .X ( copt_net_118 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_124 ) , 
+    .X ( copt_net_119 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_118 ) , 
+    .X ( copt_net_120 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_122 ) , 
+    .X ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_123 ) , 
+    .X ( copt_net_122 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_120 ) , 
+    .X ( copt_net_123 ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_511_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_511_ ) , 
+    .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_88 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( BUF_net_88 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_511_ ) , 
+    .Y ( BUF_net_90 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_112 ( .A ( BUF_net_90 ) , .Y ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head , 
+    iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_7 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_85 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_85 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_85 ( .A ( BUF_net_87 ) , .Y ( BUF_net_85 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_510_ ) , 
+    .Y ( BUF_net_87 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_87 ) , .Y ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_7 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_7 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_7 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__7 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_6 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_509_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_82 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_82 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( BUF_net_82 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_509_ ) , 
+    .Y ( BUF_net_84 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_6 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_6 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_6 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__6 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_5 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_508_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_508_ ) , 
+    .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_508_ ) , 
+    .Y ( BUF_net_81 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_5 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_5 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_5 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__5 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_507_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_76 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_76 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_76 ( .A ( BUF_net_78 ) , .Y ( BUF_net_76 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( aps_rename_507_ ) , 
+    .Y ( BUF_net_78 ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_4 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_4 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__4 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_73 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_73 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_73 ( .A ( BUF_net_75 ) , .Y ( BUF_net_73 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_75 ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_3 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_3 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__3 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_184_0 ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+input  ZBUF_184_0 ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( ZBUF_184_0 ) , .Z ( SOC_OUT ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_184_0 ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input  ZBUF_184_0 ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .ZBUF_184_0 ( ZBUF_184_0 ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail , ZBUF_184_0 ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input  ZBUF_184_0 ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , 
+    .ZBUF_184_0 ( ZBUF_184_0 ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_70 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_70 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_70 ( .A ( BUF_net_72 ) , .Y ( BUF_net_70 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_72 ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_1 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_1 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__1 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( net_net_69 ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__buf_8 BUFT_RR_69 ( .A ( net_net_69 ) , .X ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( IO_ISOL_N , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_0 EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_0 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__0 ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_105 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_103 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_100 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_97 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_95 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_93 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0_ ( chanx_left_in , chanx_right_in , ccff_head , 
+    chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , 
+    bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , 
+    bottom_grid_pin_8_ , bottom_grid_pin_10_ , bottom_grid_pin_12_ , 
+    bottom_grid_pin_14_ , bottom_grid_pin_16_ , ccff_tail , IO_ISOL_N , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , top_width_0_height_0__pin_0_ , 
+    top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , 
+    top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , 
+    top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_12_ , 
+    top_width_0_height_0__pin_14_ , top_width_0_height_0__pin_16_ , 
+    top_width_0_height_0__pin_1_upper , top_width_0_height_0__pin_1_lower , 
+    top_width_0_height_0__pin_3_upper , top_width_0_height_0__pin_3_lower , 
+    top_width_0_height_0__pin_5_upper , top_width_0_height_0__pin_5_lower , 
+    top_width_0_height_0__pin_7_upper , top_width_0_height_0__pin_7_lower , 
+    top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , 
+    top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , 
+    top_width_0_height_0__pin_13_upper , top_width_0_height_0__pin_13_lower , 
+    top_width_0_height_0__pin_15_upper , top_width_0_height_0__pin_15_lower , 
+    top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower , 
+    SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , prog_clk_0_N_in , 
+    prog_clk_0_W_out ) ;
+input  [0:19] chanx_left_in ;
+input  [0:19] chanx_right_in ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_16_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] top_width_0_height_0__pin_0_ ;
+input  [0:0] top_width_0_height_0__pin_2_ ;
+input  [0:0] top_width_0_height_0__pin_4_ ;
+input  [0:0] top_width_0_height_0__pin_6_ ;
+input  [0:0] top_width_0_height_0__pin_8_ ;
+input  [0:0] top_width_0_height_0__pin_10_ ;
+input  [0:0] top_width_0_height_0__pin_12_ ;
+input  [0:0] top_width_0_height_0__pin_14_ ;
+input  [0:0] top_width_0_height_0__pin_16_ ;
+output [0:0] top_width_0_height_0__pin_1_upper ;
+output [0:0] top_width_0_height_0__pin_1_lower ;
+output [0:0] top_width_0_height_0__pin_3_upper ;
+output [0:0] top_width_0_height_0__pin_3_lower ;
+output [0:0] top_width_0_height_0__pin_5_upper ;
+output [0:0] top_width_0_height_0__pin_5_lower ;
+output [0:0] top_width_0_height_0__pin_7_upper ;
+output [0:0] top_width_0_height_0__pin_7_lower ;
+output [0:0] top_width_0_height_0__pin_9_upper ;
+output [0:0] top_width_0_height_0__pin_9_lower ;
+output [0:0] top_width_0_height_0__pin_11_upper ;
+output [0:0] top_width_0_height_0__pin_11_lower ;
+output [0:0] top_width_0_height_0__pin_13_upper ;
+output [0:0] top_width_0_height_0__pin_13_lower ;
+output [0:0] top_width_0_height_0__pin_15_upper ;
+output [0:0] top_width_0_height_0__pin_15_lower ;
+output [0:0] top_width_0_height_0__pin_17_upper ;
+output [0:0] top_width_0_height_0__pin_17_lower ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  SC_IN_BOT ;
+output SC_OUT_TOP ;
+input  prog_clk_0_N_in ;
+output prog_clk_0_W_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__0_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__1_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__2_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__3_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__4_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__5_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__6_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_115 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_115 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] , 
+        chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_116 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[9] , chanx_left_out[9] , chanx_right_out[15] , 
+        chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_116 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_115 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .io_outpad ( top_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( top_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) , 
+    .io_outpad ( top_width_0_height_0__pin_2_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_3_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) ,
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_512_ } ) ,
+    .io_outpad ( top_width_0_height_0__pin_4_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_5_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , 
+    .ZBUF_184_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ;
+cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) , 
+    .io_outpad ( top_width_0_height_0__pin_6_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_7_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) , 
+    .io_outpad ( top_width_0_height_0__pin_8_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_9_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) , 
+    .io_outpad ( top_width_0_height_0__pin_10_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_11_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) , 
+    .io_outpad ( top_width_0_height_0__pin_12_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_13_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) , 
+    .io_outpad ( top_width_0_height_0__pin_14_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_15_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) , 
+    .io_outpad ( top_width_0_height_0__pin_16_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_17_lower ) , 
+    .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , 
+    .X ( ctsbuf_net_1117 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , 
+    .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , 
+    .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) , 
+    .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) , 
+    .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[7] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[11] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[15] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[19] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( 
+    .A ( top_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 ( 
+    .A ( top_width_0_height_0__pin_3_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_3_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( 
+    .A ( top_width_0_height_0__pin_5_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_5_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_62__61 ( 
+    .A ( top_width_0_height_0__pin_7_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_7_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_63__62 ( 
+    .A ( top_width_0_height_0__pin_9_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_9_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_64__63 ( 
+    .A ( top_width_0_height_0__pin_11_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_11_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_65__64 ( 
+    .A ( top_width_0_height_0__pin_13_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_13_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_66__65 ( 
+    .A ( top_width_0_height_0__pin_15_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_15_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_67__66 ( 
+    .A ( top_width_0_height_0__pin_17_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_17_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , 
+    .HI ( optlc_net_114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , 
+    .HI ( optlc_net_115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , 
+    .HI ( optlc_net_116 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_184_inst_121 ( .A ( aps_rename_512_ ) , 
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ;
+sky130_fd_sc_hd__clkbuf_8 cts_buf_3521248 ( .A ( ctsbuf_net_1117 ) , 
+    .X ( prog_clk_0_W_out ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.top_only.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..42aaf98
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.top_only.pt.v
@@ -0,0 +1,443 @@
+//
+//
+//
+//
+//
+//
+module cbx_1__0_ ( chanx_left_in , chanx_right_in , ccff_head , 
+    chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , 
+    bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , 
+    bottom_grid_pin_8_ , bottom_grid_pin_10_ , bottom_grid_pin_12_ , 
+    bottom_grid_pin_14_ , bottom_grid_pin_16_ , ccff_tail , IO_ISOL_N , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , top_width_0_height_0__pin_0_ , 
+    top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , 
+    top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , 
+    top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_12_ , 
+    top_width_0_height_0__pin_14_ , top_width_0_height_0__pin_16_ , 
+    top_width_0_height_0__pin_1_upper , top_width_0_height_0__pin_1_lower , 
+    top_width_0_height_0__pin_3_upper , top_width_0_height_0__pin_3_lower , 
+    top_width_0_height_0__pin_5_upper , top_width_0_height_0__pin_5_lower , 
+    top_width_0_height_0__pin_7_upper , top_width_0_height_0__pin_7_lower , 
+    top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , 
+    top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , 
+    top_width_0_height_0__pin_13_upper , top_width_0_height_0__pin_13_lower , 
+    top_width_0_height_0__pin_15_upper , top_width_0_height_0__pin_15_lower , 
+    top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower , 
+    SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , prog_clk_0_N_in , 
+    prog_clk_0_W_out ) ;
+input  [0:19] chanx_left_in ;
+input  [0:19] chanx_right_in ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_16_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] top_width_0_height_0__pin_0_ ;
+input  [0:0] top_width_0_height_0__pin_2_ ;
+input  [0:0] top_width_0_height_0__pin_4_ ;
+input  [0:0] top_width_0_height_0__pin_6_ ;
+input  [0:0] top_width_0_height_0__pin_8_ ;
+input  [0:0] top_width_0_height_0__pin_10_ ;
+input  [0:0] top_width_0_height_0__pin_12_ ;
+input  [0:0] top_width_0_height_0__pin_14_ ;
+input  [0:0] top_width_0_height_0__pin_16_ ;
+output [0:0] top_width_0_height_0__pin_1_upper ;
+output [0:0] top_width_0_height_0__pin_1_lower ;
+output [0:0] top_width_0_height_0__pin_3_upper ;
+output [0:0] top_width_0_height_0__pin_3_lower ;
+output [0:0] top_width_0_height_0__pin_5_upper ;
+output [0:0] top_width_0_height_0__pin_5_lower ;
+output [0:0] top_width_0_height_0__pin_7_upper ;
+output [0:0] top_width_0_height_0__pin_7_lower ;
+output [0:0] top_width_0_height_0__pin_9_upper ;
+output [0:0] top_width_0_height_0__pin_9_lower ;
+output [0:0] top_width_0_height_0__pin_11_upper ;
+output [0:0] top_width_0_height_0__pin_11_lower ;
+output [0:0] top_width_0_height_0__pin_13_upper ;
+output [0:0] top_width_0_height_0__pin_13_lower ;
+output [0:0] top_width_0_height_0__pin_15_upper ;
+output [0:0] top_width_0_height_0__pin_15_lower ;
+output [0:0] top_width_0_height_0__pin_17_upper ;
+output [0:0] top_width_0_height_0__pin_17_lower ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  SC_IN_BOT ;
+output SC_OUT_TOP ;
+input  prog_clk_0_N_in ;
+output prog_clk_0_W_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__0_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__1_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__2_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__3_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__4_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__5_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__6_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_115 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_115 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] , 
+        chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_116 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[9] , chanx_left_out[9] , chanx_right_out[15] , 
+        chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_116 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_115 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .io_outpad ( top_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( top_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) , 
+    .io_outpad ( top_width_0_height_0__pin_2_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_3_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) ,
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_512_ } ) ,
+    .io_outpad ( top_width_0_height_0__pin_4_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_5_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , 
+    .ZBUF_184_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ;
+cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) , 
+    .io_outpad ( top_width_0_height_0__pin_6_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_7_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) , 
+    .io_outpad ( top_width_0_height_0__pin_8_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_9_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) , 
+    .io_outpad ( top_width_0_height_0__pin_10_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_11_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) , 
+    .io_outpad ( top_width_0_height_0__pin_12_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_13_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) , 
+    .io_outpad ( top_width_0_height_0__pin_14_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_15_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) , 
+    .io_outpad ( top_width_0_height_0__pin_16_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_17_lower ) , 
+    .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , 
+    .X ( ctsbuf_net_1117 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , 
+    .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , 
+    .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) , 
+    .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) , 
+    .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[7] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[11] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[15] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[19] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( 
+    .A ( top_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 ( 
+    .A ( top_width_0_height_0__pin_3_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_3_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( 
+    .A ( top_width_0_height_0__pin_5_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_5_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_62__61 ( 
+    .A ( top_width_0_height_0__pin_7_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_7_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_63__62 ( 
+    .A ( top_width_0_height_0__pin_9_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_9_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_64__63 ( 
+    .A ( top_width_0_height_0__pin_11_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_11_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_65__64 ( 
+    .A ( top_width_0_height_0__pin_13_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_13_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_66__65 ( 
+    .A ( top_width_0_height_0__pin_15_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_15_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_67__66 ( 
+    .A ( top_width_0_height_0__pin_17_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_17_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , 
+    .HI ( optlc_net_114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , 
+    .HI ( optlc_net_115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , 
+    .HI ( optlc_net_116 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_184_inst_121 ( .A ( aps_rename_512_ ) , 
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ;
+sky130_fd_sc_hd__clkbuf_8 cts_buf_3521248 ( .A ( ctsbuf_net_1117 ) , 
+    .X ( prog_clk_0_W_out ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v
new file mode 100644
index 0000000..4d1c581
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v
@@ -0,0 +1,1746 @@
+//
+//
+//
+//
+//
+//
+module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__const1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cbx_1__1__const1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__const1_14 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cbx_1__1__const1_14 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__const1_13 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cbx_1__1__const1_13 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__const1_12 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cbx_1__1__const1_12 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__const1_11 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cbx_1__1__const1_11 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__const1_10 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cbx_1__1__const1_10 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__const1_9 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cbx_1__1__const1_9 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__const1_8 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cbx_1__1__const1_8 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+wire copt_net_81 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_81 ) ) ;
+sky130_fd_sc_hd__buf_4 FTB_8__7 ( .A ( copt_net_83 ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_81 ) , 
+    .X ( copt_net_80 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , 
+    .X ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( mem_out[3] ) , 
+    .X ( copt_net_82 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_84 ) , 
+    .X ( copt_net_83 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_85 ) , 
+    .X ( copt_net_84 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1308 ( .A ( copt_net_82 ) , 
+    .X ( copt_net_85 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_79 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_74 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_74 ) , 
+    .X ( copt_net_75 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_75 ) , 
+    .X ( copt_net_76 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_76 ) , 
+    .X ( copt_net_77 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_77 ) , 
+    .X ( copt_net_78 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , 
+    .X ( copt_net_79 ) ) ;
+endmodule
+
+
+module cbx_1__1__const1_7 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__1__const1_7 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__const1_6 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__1__const1_6 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__const1_5 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__1__const1_5 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__const1_4 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__1__const1_4 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__const1_3 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__1__const1_3 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_59 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__const1_2 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__1__const1_2 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__const1_1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__1__const1_1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__const1_0 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__1__const1_0 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1_ ( chanx_left_in , chanx_right_in , ccff_head , 
+    chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , 
+    bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , 
+    bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , 
+    bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , 
+    bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , 
+    bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , 
+    ccff_tail , SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , 
+    REGIN_FEEDTHROUGH , REGOUT_FEEDTHROUGH , prog_clk_0_N_in , 
+    prog_clk_0_W_out , prog_clk_1_W_in , prog_clk_1_E_in , prog_clk_1_N_out , 
+    prog_clk_1_S_out , prog_clk_2_E_in , prog_clk_2_W_in , prog_clk_2_W_out , 
+    prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out , 
+    prog_clk_3_W_out , clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out , 
+    clk_2_E_in , clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in , 
+    clk_3_E_in , clk_3_E_out , clk_3_W_out ) ;
+input  [0:19] chanx_left_in ;
+input  [0:19] chanx_right_in ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_1_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_3_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_5_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_7_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_9_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_11_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_13_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_15_ ;
+output [0:0] ccff_tail ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  SC_IN_BOT ;
+output SC_OUT_TOP ;
+input  REGIN_FEEDTHROUGH ;
+output REGOUT_FEEDTHROUGH ;
+input  prog_clk_0_N_in ;
+output prog_clk_0_W_out ;
+input  prog_clk_1_W_in ;
+input  prog_clk_1_E_in ;
+output prog_clk_1_N_out ;
+output prog_clk_1_S_out ;
+input  prog_clk_2_E_in ;
+input  prog_clk_2_W_in ;
+output prog_clk_2_W_out ;
+output prog_clk_2_E_out ;
+input  prog_clk_3_W_in ;
+input  prog_clk_3_E_in ;
+output prog_clk_3_E_out ;
+output prog_clk_3_W_out ;
+input  clk_1_W_in ;
+input  clk_1_E_in ;
+output clk_1_N_out ;
+output clk_1_S_out ;
+input  clk_2_E_in ;
+input  clk_2_W_in ;
+output clk_2_W_out ;
+output clk_2_E_out ;
+input  clk_3_W_in ;
+input  clk_3_E_in ;
+output clk_3_E_out ;
+output clk_3_W_out ;
+
+wire ropt_net_94 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_1_W_in = prog_clk_1_E_in ;
+assign prog_clk_2_E_in = prog_clk_2_W_in ;
+assign prog_clk_3_W_in = prog_clk_3_E_in ;
+assign clk_1_W_in = clk_1_E_in ;
+assign clk_2_E_in = clk_2_W_in ;
+assign clk_3_W_in = clk_3_E_in ;
+
+cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] , 
+        chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_69 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_8 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[15] , 
+        chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_12 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ropt_net_100 } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[13] , chanx_left_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_69 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[17] , chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_69 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[13] , chanx_left_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_10 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_13 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[17] , chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_14 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , 
+    .X ( ctsbuf_net_173 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , 
+    .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , 
+    .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , 
+    .X ( prog_clk_2_W_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , 
+    .X ( prog_clk_2_E_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , 
+    .X ( prog_clk_3_E_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , 
+    .X ( prog_clk_3_W_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , 
+    .X ( clk_1_N_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , 
+    .X ( clk_1_S_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , 
+    .X ( clk_2_W_out ) ) ;
+sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_68 ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , 
+    .X ( clk_3_E_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , 
+    .X ( clk_3_W_out ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , 
+    .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_12 FTB_18__17 ( .A ( chanx_left_in[1] ) , 
+    .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[0] ) , 
+    .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[1] ) , 
+    .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[3] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[7] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[11] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[15] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[19] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( ropt_net_94 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( REGIN_FEEDTHROUGH ) , 
+    .X ( REGOUT_FEEDTHROUGH ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , 
+    .Y ( prog_clk_1_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_65 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , 
+    .Y ( prog_clk_1_S_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_67 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( clk_2_E_out ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , 
+    .HI ( optlc_net_69 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , 
+    .HI ( optlc_net_70 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , 
+    .HI ( optlc_net_71 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , 
+    .HI ( optlc_net_72 ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1318 ( .A ( ropt_net_94 ) , 
+    .X ( ropt_net_104 ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521204 ( .A ( ctsbuf_net_173 ) , 
+    .X ( prog_clk_0_W_out ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1325 ( .A ( ropt_net_100 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1329 ( .A ( ropt_net_104 ) , 
+    .X ( SC_OUT_TOP ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v
new file mode 100644
index 0000000..3b5d288
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v
@@ -0,0 +1,1853 @@
+//
+//
+//
+//
+//
+//
+module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+wire copt_net_81 ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_81 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_4 FTB_8__7 ( .A ( copt_net_83 ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_81 ) , 
+    .X ( copt_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , 
+    .X ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( mem_out[3] ) , 
+    .X ( copt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_84 ) , 
+    .X ( copt_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_85 ) , 
+    .X ( copt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1308 ( .A ( copt_net_82 ) , 
+    .X ( copt_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_79 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_74 ) , 
+    .X ( copt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_75 ) , 
+    .X ( copt_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_76 ) , 
+    .X ( copt_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_77 ) , 
+    .X ( copt_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , 
+    .X ( copt_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_59 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__1_ ( chanx_left_in , chanx_right_in , ccff_head , 
+    chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , 
+    bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , 
+    bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , 
+    bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , 
+    bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , 
+    bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , 
+    ccff_tail , SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , 
+    REGIN_FEEDTHROUGH , REGOUT_FEEDTHROUGH , prog_clk_0_N_in , 
+    prog_clk_0_W_out , prog_clk_1_W_in , prog_clk_1_E_in , prog_clk_1_N_out , 
+    prog_clk_1_S_out , prog_clk_2_E_in , prog_clk_2_W_in , prog_clk_2_W_out , 
+    prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out , 
+    prog_clk_3_W_out , clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out , 
+    clk_2_E_in , clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in , 
+    clk_3_E_in , clk_3_E_out , clk_3_W_out , VDD , VSS ) ;
+input  [0:19] chanx_left_in ;
+input  [0:19] chanx_right_in ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_1_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_3_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_5_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_7_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_9_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_11_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_13_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_15_ ;
+output [0:0] ccff_tail ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  SC_IN_BOT ;
+output SC_OUT_TOP ;
+input  REGIN_FEEDTHROUGH ;
+output REGOUT_FEEDTHROUGH ;
+input  prog_clk_0_N_in ;
+output prog_clk_0_W_out ;
+input  prog_clk_1_W_in ;
+input  prog_clk_1_E_in ;
+output prog_clk_1_N_out ;
+output prog_clk_1_S_out ;
+input  prog_clk_2_E_in ;
+input  prog_clk_2_W_in ;
+output prog_clk_2_W_out ;
+output prog_clk_2_E_out ;
+input  prog_clk_3_W_in ;
+input  prog_clk_3_E_in ;
+output prog_clk_3_E_out ;
+output prog_clk_3_W_out ;
+input  clk_1_W_in ;
+input  clk_1_E_in ;
+output clk_1_N_out ;
+output clk_1_S_out ;
+input  clk_2_E_in ;
+input  clk_2_W_in ;
+output clk_2_W_out ;
+output clk_2_E_out ;
+input  clk_3_W_in ;
+input  clk_3_E_in ;
+output clk_3_E_out ;
+output clk_3_W_out ;
+input  VDD ;
+input  VSS ;
+
+wire ropt_net_94 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
+
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_1_W_in = prog_clk_1_E_in ;
+assign prog_clk_2_E_in = prog_clk_2_W_in ;
+assign prog_clk_3_W_in = prog_clk_3_E_in ;
+assign clk_1_W_in = clk_1_E_in ;
+assign clk_2_E_in = clk_2_W_in ;
+assign clk_3_W_in = clk_3_E_in ;
+
+cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] , 
+        chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_69 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_8 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[15] , 
+        chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_12 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ropt_net_100 } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[13] , chanx_left_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_69 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[17] , chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_69 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[13] , chanx_left_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_10 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_13 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[17] , chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_14 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , 
+    .X ( ctsbuf_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , 
+    .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , 
+    .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , 
+    .X ( prog_clk_2_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , 
+    .X ( prog_clk_2_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , 
+    .X ( prog_clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , 
+    .X ( prog_clk_3_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , 
+    .X ( clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , 
+    .X ( clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , 
+    .X ( clk_2_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_68 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , 
+    .X ( clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , 
+    .X ( clk_3_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , 
+    .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_12 FTB_18__17 ( .A ( chanx_left_in[1] ) , 
+    .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) , 
+    .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) , 
+    .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) , 
+    .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) , 
+    .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) , 
+    .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[0] ) , 
+    .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[1] ) , 
+    .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[3] ) , 
+    .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[7] ) , 
+    .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[11] ) , 
+    .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[15] ) , 
+    .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[19] ) , 
+    .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( ropt_net_94 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( REGIN_FEEDTHROUGH ) , 
+    .X ( REGOUT_FEEDTHROUGH ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , 
+    .Y ( prog_clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , 
+    .Y ( prog_clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( clk_2_E_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , 
+    .HI ( optlc_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , 
+    .HI ( optlc_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , 
+    .HI ( optlc_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , 
+    .HI ( optlc_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1318 ( .A ( ropt_net_94 ) , 
+    .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521204 ( .A ( ctsbuf_net_173 ) , 
+    .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1325 ( .A ( ropt_net_100 ) , 
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1329 ( .A ( ropt_net_104 ) , 
+    .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v
new file mode 100644
index 0000000..29bb84d
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v
@@ -0,0 +1,1570 @@
+//
+//
+//
+//
+//
+//
+module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+wire copt_net_81 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_81 ) ) ;
+sky130_fd_sc_hd__buf_4 FTB_8__7 ( .A ( copt_net_83 ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_81 ) , 
+    .X ( copt_net_80 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , 
+    .X ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( mem_out[3] ) , 
+    .X ( copt_net_82 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_84 ) , 
+    .X ( copt_net_83 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_85 ) , 
+    .X ( copt_net_84 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1308 ( .A ( copt_net_82 ) , 
+    .X ( copt_net_85 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_79 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_74 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_74 ) , 
+    .X ( copt_net_75 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_75 ) , 
+    .X ( copt_net_76 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_76 ) , 
+    .X ( copt_net_77 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_77 ) , 
+    .X ( copt_net_78 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , 
+    .X ( copt_net_79 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_59 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1_ ( chanx_left_in , chanx_right_in , ccff_head , 
+    chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , 
+    bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , 
+    bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , 
+    bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , 
+    bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , 
+    bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , 
+    ccff_tail , SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , 
+    REGIN_FEEDTHROUGH , REGOUT_FEEDTHROUGH , prog_clk_0_N_in , 
+    prog_clk_0_W_out , prog_clk_1_W_in , prog_clk_1_E_in , prog_clk_1_N_out , 
+    prog_clk_1_S_out , prog_clk_2_E_in , prog_clk_2_W_in , prog_clk_2_W_out , 
+    prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out , 
+    prog_clk_3_W_out , clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out , 
+    clk_2_E_in , clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in , 
+    clk_3_E_in , clk_3_E_out , clk_3_W_out ) ;
+input  [0:19] chanx_left_in ;
+input  [0:19] chanx_right_in ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_1_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_3_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_5_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_7_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_9_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_11_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_13_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_15_ ;
+output [0:0] ccff_tail ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  SC_IN_BOT ;
+output SC_OUT_TOP ;
+input  REGIN_FEEDTHROUGH ;
+output REGOUT_FEEDTHROUGH ;
+input  prog_clk_0_N_in ;
+output prog_clk_0_W_out ;
+input  prog_clk_1_W_in ;
+input  prog_clk_1_E_in ;
+output prog_clk_1_N_out ;
+output prog_clk_1_S_out ;
+input  prog_clk_2_E_in ;
+input  prog_clk_2_W_in ;
+output prog_clk_2_W_out ;
+output prog_clk_2_E_out ;
+input  prog_clk_3_W_in ;
+input  prog_clk_3_E_in ;
+output prog_clk_3_E_out ;
+output prog_clk_3_W_out ;
+input  clk_1_W_in ;
+input  clk_1_E_in ;
+output clk_1_N_out ;
+output clk_1_S_out ;
+input  clk_2_E_in ;
+input  clk_2_W_in ;
+output clk_2_W_out ;
+output clk_2_E_out ;
+input  clk_3_W_in ;
+input  clk_3_E_in ;
+output clk_3_E_out ;
+output clk_3_W_out ;
+
+wire ropt_net_94 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_1_E_in = prog_clk_1_W_in ;
+assign prog_clk_2_W_in = prog_clk_2_E_in ;
+assign prog_clk_3_E_in = prog_clk_3_W_in ;
+assign clk_1_E_in = clk_1_W_in ;
+assign clk_2_W_in = clk_2_E_in ;
+assign clk_3_E_in = clk_3_W_in ;
+
+cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] , 
+        chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_69 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_8 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[15] , 
+        chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_12 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ropt_net_100 } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[13] , chanx_left_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_69 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[17] , chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_69 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[13] , chanx_left_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_10 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_13 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[17] , chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_14 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , 
+    .X ( ctsbuf_net_173 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , 
+    .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , 
+    .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , 
+    .X ( prog_clk_2_W_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , 
+    .X ( prog_clk_2_E_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , 
+    .X ( prog_clk_3_E_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , 
+    .X ( prog_clk_3_W_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , 
+    .X ( clk_1_N_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , 
+    .X ( clk_1_S_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , 
+    .X ( clk_2_W_out ) ) ;
+sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_68 ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , 
+    .X ( clk_3_E_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , 
+    .X ( clk_3_W_out ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , 
+    .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_12 FTB_18__17 ( .A ( chanx_left_in[1] ) , 
+    .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[0] ) , 
+    .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[1] ) , 
+    .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[3] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[7] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[11] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[15] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[19] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( ropt_net_94 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( REGIN_FEEDTHROUGH ) , 
+    .X ( REGOUT_FEEDTHROUGH ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , 
+    .Y ( prog_clk_1_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_65 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , 
+    .Y ( prog_clk_1_S_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_67 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( clk_2_E_out ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , 
+    .HI ( optlc_net_69 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , 
+    .HI ( optlc_net_70 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , 
+    .HI ( optlc_net_71 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , 
+    .HI ( optlc_net_72 ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1318 ( .A ( ropt_net_94 ) , 
+    .X ( ropt_net_104 ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521204 ( .A ( ctsbuf_net_173 ) , 
+    .X ( prog_clk_0_W_out ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1325 ( .A ( ropt_net_100 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1329 ( .A ( ropt_net_104 ) , 
+    .X ( SC_OUT_TOP ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.top_only.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..47a86f3
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.top_only.pt.v
@@ -0,0 +1,472 @@
+//
+//
+//
+//
+//
+//
+module cbx_1__1_ ( chanx_left_in , chanx_right_in , ccff_head , 
+    chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , 
+    bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , 
+    bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , 
+    bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , 
+    bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , 
+    bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , 
+    ccff_tail , SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , 
+    REGIN_FEEDTHROUGH , REGOUT_FEEDTHROUGH , prog_clk_0_N_in , 
+    prog_clk_0_W_out , prog_clk_1_W_in , prog_clk_1_E_in , prog_clk_1_N_out , 
+    prog_clk_1_S_out , prog_clk_2_E_in , prog_clk_2_W_in , prog_clk_2_W_out , 
+    prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out , 
+    prog_clk_3_W_out , clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out , 
+    clk_2_E_in , clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in , 
+    clk_3_E_in , clk_3_E_out , clk_3_W_out ) ;
+input  [0:19] chanx_left_in ;
+input  [0:19] chanx_right_in ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_1_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_3_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_5_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_7_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_9_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_11_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_13_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_15_ ;
+output [0:0] ccff_tail ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  SC_IN_BOT ;
+output SC_OUT_TOP ;
+input  REGIN_FEEDTHROUGH ;
+output REGOUT_FEEDTHROUGH ;
+input  prog_clk_0_N_in ;
+output prog_clk_0_W_out ;
+input  prog_clk_1_W_in ;
+input  prog_clk_1_E_in ;
+output prog_clk_1_N_out ;
+output prog_clk_1_S_out ;
+input  prog_clk_2_E_in ;
+input  prog_clk_2_W_in ;
+output prog_clk_2_W_out ;
+output prog_clk_2_E_out ;
+input  prog_clk_3_W_in ;
+input  prog_clk_3_E_in ;
+output prog_clk_3_E_out ;
+output prog_clk_3_W_out ;
+input  clk_1_W_in ;
+input  clk_1_E_in ;
+output clk_1_N_out ;
+output clk_1_S_out ;
+input  clk_2_E_in ;
+input  clk_2_W_in ;
+output clk_2_W_out ;
+output clk_2_E_out ;
+input  clk_3_W_in ;
+input  clk_3_E_in ;
+output clk_3_E_out ;
+output clk_3_W_out ;
+
+wire ropt_net_94 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_1_E_in = prog_clk_1_W_in ;
+assign prog_clk_2_W_in = prog_clk_2_E_in ;
+assign prog_clk_3_E_in = prog_clk_3_W_in ;
+assign clk_1_E_in = clk_1_W_in ;
+assign clk_2_W_in = clk_2_E_in ;
+assign clk_3_E_in = clk_3_W_in ;
+
+cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] , 
+        chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_69 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_8 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[15] , 
+        chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_12 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ropt_net_100 } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[13] , chanx_left_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_69 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[17] , chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_69 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[13] , chanx_left_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_10 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_13 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[17] , chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_14 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , 
+    .X ( ctsbuf_net_173 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , 
+    .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , 
+    .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , 
+    .X ( prog_clk_2_W_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , 
+    .X ( prog_clk_2_E_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , 
+    .X ( prog_clk_3_E_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , 
+    .X ( prog_clk_3_W_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , 
+    .X ( clk_1_N_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , 
+    .X ( clk_1_S_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , 
+    .X ( clk_2_W_out ) ) ;
+sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_68 ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , 
+    .X ( clk_3_E_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , 
+    .X ( clk_3_W_out ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , 
+    .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_12 FTB_18__17 ( .A ( chanx_left_in[1] ) , 
+    .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[0] ) , 
+    .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[1] ) , 
+    .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[3] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[7] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[11] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[15] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[19] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( ropt_net_94 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( REGIN_FEEDTHROUGH ) , 
+    .X ( REGOUT_FEEDTHROUGH ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , 
+    .Y ( prog_clk_1_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_65 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , 
+    .Y ( prog_clk_1_S_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_67 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( clk_2_E_out ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , 
+    .HI ( optlc_net_69 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , 
+    .HI ( optlc_net_70 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , 
+    .HI ( optlc_net_71 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , 
+    .HI ( optlc_net_72 ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1318 ( .A ( ropt_net_94 ) , 
+    .X ( ropt_net_104 ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521204 ( .A ( ctsbuf_net_173 ) , 
+    .X ( prog_clk_0_W_out ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1325 ( .A ( ropt_net_100 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1329 ( .A ( ropt_net_104 ) , 
+    .X ( SC_OUT_TOP ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v
new file mode 100644
index 0000000..a37cd5b
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v
@@ -0,0 +1,1879 @@
+//
+//
+//
+//
+//
+//
+module cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_86 ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_86 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_88 ) , 
+    .X ( copt_net_84 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_87 ) , 
+    .X ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_2 copt_h_inst_1310 ( .A ( copt_net_84 ) , 
+    .X ( copt_net_87 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_86 ) , 
+    .X ( copt_net_88 ) ) ;
+endmodule
+
+
+module cbx_1__2__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_61 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_61 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_61 ( .A ( BUF_net_63 ) , .Y ( BUF_net_61 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_63 ) ) ;
+endmodule
+
+
+module cbx_1__2__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head , 
+    iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__2__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__2__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__const1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cbx_1__2__const1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__const1_15 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cbx_1__2__const1_15 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__const1_14 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cbx_1__2__const1_14 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__const1_13 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cbx_1__2__const1_13 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__const1_12 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cbx_1__2__const1_12 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__const1_11 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cbx_1__2__const1_11 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__const1_10 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cbx_1__2__const1_10 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__const1_9 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cbx_1__2__const1_9 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_93 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_79 ) , 
+    .X ( copt_net_77 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_78 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , 
+    .X ( copt_net_79 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_77 ) , 
+    .X ( copt_net_80 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , 
+    .X ( copt_net_81 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_81 ) , 
+    .X ( copt_net_82 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1313 ( .A ( copt_net_82 ) , 
+    .X ( ropt_net_91 ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , 
+    .X ( ropt_net_92 ) ) ;
+sky130_fd_sc_hd__buf_2 ropt_h_inst_1315 ( .A ( ropt_net_92 ) , 
+    .X ( ropt_net_93 ) ) ;
+endmodule
+
+
+module cbx_1__2__const1_8 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__2__const1_8 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__const1_7 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__2__const1_7 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__const1_6 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__2__const1_6 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__const1_5 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__2__const1_5 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__const1_4 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__2__const1_4 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__const1_3 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__2__const1_3 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__const1_2 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__2__const1_2 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__const1_1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__2__const1_1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__const1_0 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cbx_1__2__const1_0 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2_ ( chanx_left_in , chanx_right_in , ccff_head , 
+    chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , 
+    bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , 
+    bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , 
+    bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , 
+    bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , 
+    bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , 
+    ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , 
+    bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT , 
+    SC_IN_BOT , SC_OUT_TOP , prog_clk_0_S_in , prog_clk_0_W_out ) ;
+input  [0:19] chanx_left_in ;
+input  [0:19] chanx_right_in ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] top_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_1_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_3_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_5_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_7_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_9_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_11_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_13_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_15_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] bottom_width_0_height_0__pin_0_ ;
+output [0:0] bottom_width_0_height_0__pin_1_upper ;
+output [0:0] bottom_width_0_height_0__pin_1_lower ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  SC_IN_BOT ;
+output SC_OUT_TOP ;
+input  prog_clk_0_S_in ;
+output prog_clk_0_W_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] , 
+        chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_4 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[9] , chanx_left_out[9] , chanx_right_out[15] , 
+        chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_7 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_11 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_12 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_2 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[15] , chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_5 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_6 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] , 
+        chanx_right_out[19] , chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_9 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[15] , chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_13 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_14 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] , 
+        chanx_right_out[19] , chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
+        SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( bottom_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( bottom_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , 
+    .X ( ctsbuf_net_176 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , 
+    .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , 
+    .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) , 
+    .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) , 
+    .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[7] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[11] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[15] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[19] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( 
+    .A ( bottom_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , 
+    .HI ( optlc_net_72 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , 
+    .HI ( optlc_net_73 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , 
+    .HI ( optlc_net_74 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , 
+    .HI ( optlc_net_75 ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_176 ) , 
+    .X ( prog_clk_0_W_out ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v
new file mode 100644
index 0000000..419d1f7
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v
@@ -0,0 +1,2016 @@
+//
+//
+//
+//
+//
+//
+module cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+wire copt_net_86 ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_86 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_88 ) , 
+    .X ( copt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_87 ) , 
+    .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_2 copt_h_inst_1310 ( .A ( copt_net_84 ) , 
+    .X ( copt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_86 ) , 
+    .X ( copt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_61 ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_61 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_61 ( .A ( BUF_net_63 ) , .Y ( BUF_net_61 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head , 
+    iopad_inpad , ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__2__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_93 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_79 ) , 
+    .X ( copt_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , 
+    .X ( copt_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_77 ) , 
+    .X ( copt_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , 
+    .X ( copt_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_81 ) , 
+    .X ( copt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1313 ( .A ( copt_net_82 ) , 
+    .X ( ropt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , 
+    .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_2 ropt_h_inst_1315 ( .A ( ropt_net_92 ) , 
+    .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cbx_1__2_ ( chanx_left_in , chanx_right_in , ccff_head , 
+    chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , 
+    bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , 
+    bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , 
+    bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , 
+    bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , 
+    bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , 
+    ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , 
+    bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT , 
+    SC_IN_BOT , SC_OUT_TOP , prog_clk_0_S_in , prog_clk_0_W_out , VDD , VSS ) ;
+input  [0:19] chanx_left_in ;
+input  [0:19] chanx_right_in ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] top_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_1_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_3_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_5_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_7_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_9_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_11_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_13_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_15_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] bottom_width_0_height_0__pin_0_ ;
+output [0:0] bottom_width_0_height_0__pin_1_upper ;
+output [0:0] bottom_width_0_height_0__pin_1_lower ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  SC_IN_BOT ;
+output SC_OUT_TOP ;
+input  prog_clk_0_S_in ;
+output prog_clk_0_W_out ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( top_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] , 
+        chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_4 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[9] , chanx_left_out[9] , chanx_right_out[15] , 
+        chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_7 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_11 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_12 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_2 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[15] , chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_5 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_6 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] , 
+        chanx_right_out[19] , chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_9 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[15] , chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_13 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_14 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] , 
+        chanx_right_out[19] , chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
+        SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( bottom_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( bottom_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , 
+    .X ( ctsbuf_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , 
+    .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , 
+    .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , 
+    .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , 
+    .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , 
+    .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , 
+    .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , 
+    .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) , 
+    .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) , 
+    .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) , 
+    .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[7] ) , 
+    .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[11] ) , 
+    .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[15] ) , 
+    .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[19] ) , 
+    .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( 
+    .A ( bottom_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( bottom_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , 
+    .HI ( optlc_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , 
+    .HI ( optlc_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , 
+    .HI ( optlc_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , 
+    .HI ( optlc_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_176 ) , 
+    .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v
new file mode 100644
index 0000000..d10e082
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v
@@ -0,0 +1,1692 @@
+//
+//
+//
+//
+//
+//
+module cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_86 ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_86 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_88 ) , 
+    .X ( copt_net_84 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_87 ) , 
+    .X ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_2 copt_h_inst_1310 ( .A ( copt_net_84 ) , 
+    .X ( copt_net_87 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_86 ) , 
+    .X ( copt_net_88 ) ) ;
+endmodule
+
+
+module cbx_1__2__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_61 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_61 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_61 ( .A ( BUF_net_63 ) , .Y ( BUF_net_61 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_63 ) ) ;
+endmodule
+
+
+module cbx_1__2__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head , 
+    iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__2__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__2__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_93 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_79 ) , 
+    .X ( copt_net_77 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_78 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , 
+    .X ( copt_net_79 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_77 ) , 
+    .X ( copt_net_80 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , 
+    .X ( copt_net_81 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_81 ) , 
+    .X ( copt_net_82 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1313 ( .A ( copt_net_82 ) , 
+    .X ( ropt_net_91 ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , 
+    .X ( ropt_net_92 ) ) ;
+sky130_fd_sc_hd__buf_2 ropt_h_inst_1315 ( .A ( ropt_net_92 ) , 
+    .X ( ropt_net_93 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2_ ( chanx_left_in , chanx_right_in , ccff_head , 
+    chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , 
+    bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , 
+    bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , 
+    bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , 
+    bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , 
+    bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , 
+    ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , 
+    bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT , 
+    SC_IN_BOT , SC_OUT_TOP , prog_clk_0_S_in , prog_clk_0_W_out ) ;
+input  [0:19] chanx_left_in ;
+input  [0:19] chanx_right_in ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] top_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_1_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_3_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_5_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_7_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_9_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_11_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_13_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_15_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] bottom_width_0_height_0__pin_0_ ;
+output [0:0] bottom_width_0_height_0__pin_1_upper ;
+output [0:0] bottom_width_0_height_0__pin_1_lower ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  SC_IN_BOT ;
+output SC_OUT_TOP ;
+input  prog_clk_0_S_in ;
+output prog_clk_0_W_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] , 
+        chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_4 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[9] , chanx_left_out[9] , chanx_right_out[15] , 
+        chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_7 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_11 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_12 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_2 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[15] , chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_5 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_6 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] , 
+        chanx_right_out[19] , chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_9 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[15] , chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_13 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_14 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] , 
+        chanx_right_out[19] , chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
+        SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( bottom_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( bottom_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , 
+    .X ( ctsbuf_net_176 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , 
+    .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , 
+    .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) , 
+    .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) , 
+    .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[7] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[11] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[15] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[19] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( 
+    .A ( bottom_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , 
+    .HI ( optlc_net_72 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , 
+    .HI ( optlc_net_73 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , 
+    .HI ( optlc_net_74 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , 
+    .HI ( optlc_net_75 ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_176 ) , 
+    .X ( prog_clk_0_W_out ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.top_only.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..16552ea
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.top_only.pt.v
@@ -0,0 +1,432 @@
+//
+//
+//
+//
+//
+//
+module cbx_1__2_ ( chanx_left_in , chanx_right_in , ccff_head , 
+    chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , 
+    bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , 
+    bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , 
+    bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , 
+    bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , 
+    bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , 
+    ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , 
+    bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT , 
+    SC_IN_BOT , SC_OUT_TOP , prog_clk_0_S_in , prog_clk_0_W_out ) ;
+input  [0:19] chanx_left_in ;
+input  [0:19] chanx_right_in ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] top_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_1_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_3_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_5_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_7_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_9_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_11_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_13_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_15_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] bottom_width_0_height_0__pin_0_ ;
+output [0:0] bottom_width_0_height_0__pin_1_upper ;
+output [0:0] bottom_width_0_height_0__pin_1_lower ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  SC_IN_BOT ;
+output SC_OUT_TOP ;
+input  prog_clk_0_S_in ;
+output prog_clk_0_W_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] , 
+        chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_4 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[9] , chanx_left_out[9] , chanx_right_out[15] , 
+        chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_7 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_11 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_12 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_2 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[15] , chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_5 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_6 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] , 
+        chanx_right_out[19] , chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_9 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[15] , chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_13 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_14 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] , 
+        chanx_right_out[19] , chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
+        SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( bottom_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( bottom_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , 
+    .X ( ctsbuf_net_176 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , 
+    .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , 
+    .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) , 
+    .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) , 
+    .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[7] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[11] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[15] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[19] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( 
+    .A ( bottom_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , 
+    .HI ( optlc_net_72 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , 
+    .HI ( optlc_net_73 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , 
+    .HI ( optlc_net_74 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , 
+    .HI ( optlc_net_75 ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_176 ) , 
+    .X ( prog_clk_0_W_out ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v
new file mode 100644
index 0000000..975243f
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v
@@ -0,0 +1,356 @@
+//
+//
+//
+//
+//
+//
+module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_55 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_55 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_59 ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_55 ) , 
+    .X ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( mem_out[0] ) , 
+    .X ( copt_net_56 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_60 ) , 
+    .X ( copt_net_57 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1190 ( .A ( copt_net_57 ) , 
+    .X ( copt_net_58 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1191 ( .A ( copt_net_58 ) , 
+    .X ( copt_net_59 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_56 ) , 
+    .X ( copt_net_60 ) ) ;
+endmodule
+
+
+module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_43 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_43 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_43 ( .A ( BUF_net_45 ) , .Y ( BUF_net_43 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_45 ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head , 
+    iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_54 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( copt_net_51 ) , 
+    .X ( copt_net_49 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_52 ) , 
+    .X ( copt_net_50 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_53 ) , 
+    .X ( copt_net_51 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_52 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_50 ) , 
+    .X ( copt_net_53 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_49 ) , 
+    .X ( copt_net_54 ) ) ;
+endmodule
+
+
+module cby_0__1__const1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_0__1__const1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_46 ( .A ( BUF_net_47 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_47 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_47 ) ) ;
+endmodule
+
+
+module cby_0__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , 
+    IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , 
+    right_width_0_height_0__pin_1_lower , prog_clk_0_E_in ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] left_grid_pin_0_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] right_width_0_height_0__pin_0_ ;
+output [0:0] right_width_0_height_0__pin_1_upper ;
+output [0:0] right_width_0_height_0__pin_1_lower ;
+input  prog_clk_0_E_in ;
+
+wire ropt_net_73 ;
+wire ropt_net_75 ;
+wire ropt_net_74 ;
+wire ropt_net_72 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_48 ) ) ;
+cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( right_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( right_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_6__5 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , 
+    .X ( ropt_net_73 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , 
+    .X ( ropt_net_75 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_15__14 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_top_in[3] ) , 
+    .X ( ropt_net_74 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_31__30 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[18] ) , 
+    .X ( ropt_net_72 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_43__42 ( 
+    .A ( right_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , 
+    .HI ( optlc_net_48 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1204 ( .A ( ropt_net_72 ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1205 ( .A ( ropt_net_73 ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1206 ( .A ( ropt_net_74 ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1207 ( .A ( ropt_net_75 ) , 
+    .X ( chany_top_out[8] ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v
new file mode 100644
index 0000000..93eaeb1
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v
@@ -0,0 +1,395 @@
+//
+//
+//
+//
+//
+//
+module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+wire copt_net_55 ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_55 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_59 ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_55 ) , 
+    .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( mem_out[0] ) , 
+    .X ( copt_net_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_60 ) , 
+    .X ( copt_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1190 ( .A ( copt_net_57 ) , 
+    .X ( copt_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1191 ( .A ( copt_net_58 ) , 
+    .X ( copt_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_56 ) , 
+    .X ( copt_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_43 ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_43 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_43 ( .A ( BUF_net_45 ) , .Y ( BUF_net_43 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_45 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head , 
+    iopad_inpad , ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
+
+cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+endmodule
+
+
+module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_54 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( copt_net_51 ) , 
+    .X ( copt_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_52 ) , 
+    .X ( copt_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_53 ) , 
+    .X ( copt_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_50 ) , 
+    .X ( copt_net_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_49 ) , 
+    .X ( copt_net_54 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_46 ( .A ( BUF_net_47 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_47 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_47 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_0__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , 
+    IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , 
+    right_width_0_height_0__pin_1_lower , prog_clk_0_E_in , VDD , VSS ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] left_grid_pin_0_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] right_width_0_height_0__pin_0_ ;
+output [0:0] right_width_0_height_0__pin_1_upper ;
+output [0:0] right_width_0_height_0__pin_1_lower ;
+input  prog_clk_0_E_in ;
+input  VDD ;
+input  VSS ;
+
+wire ropt_net_73 ;
+wire ropt_net_75 ;
+wire ropt_net_74 ;
+wire ropt_net_72 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+supply1 VDD ;
+supply0 VSS ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_48 ) ) ;
+cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( right_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( right_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_6__5 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , 
+    .X ( ropt_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , 
+    .X ( ropt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_15__14 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_top_in[3] ) , 
+    .X ( ropt_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_31__30 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[18] ) , 
+    .X ( ropt_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_43__42 ( 
+    .A ( right_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( right_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , 
+    .HI ( optlc_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1204 ( .A ( ropt_net_72 ) , 
+    .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1205 ( .A ( ropt_net_73 ) , 
+    .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1206 ( .A ( ropt_net_74 ) , 
+    .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1207 ( .A ( ropt_net_75 ) , 
+    .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v
new file mode 100644
index 0000000..0b8883f
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v
@@ -0,0 +1,345 @@
+//
+//
+//
+//
+//
+//
+module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_55 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_55 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_59 ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_55 ) , 
+    .X ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( mem_out[0] ) , 
+    .X ( copt_net_56 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_60 ) , 
+    .X ( copt_net_57 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1190 ( .A ( copt_net_57 ) , 
+    .X ( copt_net_58 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1191 ( .A ( copt_net_58 ) , 
+    .X ( copt_net_59 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_56 ) , 
+    .X ( copt_net_60 ) ) ;
+endmodule
+
+
+module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_43 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_43 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_43 ( .A ( BUF_net_45 ) , .Y ( BUF_net_43 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_45 ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head , 
+    iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_54 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( copt_net_51 ) , 
+    .X ( copt_net_49 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_52 ) , 
+    .X ( copt_net_50 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_53 ) , 
+    .X ( copt_net_51 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_52 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_50 ) , 
+    .X ( copt_net_53 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_49 ) , 
+    .X ( copt_net_54 ) ) ;
+endmodule
+
+
+module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_46 ( .A ( BUF_net_47 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_47 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_47 ) ) ;
+endmodule
+
+
+module cby_0__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , 
+    IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , 
+    right_width_0_height_0__pin_1_lower , prog_clk_0_E_in ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] left_grid_pin_0_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] right_width_0_height_0__pin_0_ ;
+output [0:0] right_width_0_height_0__pin_1_upper ;
+output [0:0] right_width_0_height_0__pin_1_lower ;
+input  prog_clk_0_E_in ;
+
+wire ropt_net_73 ;
+wire ropt_net_75 ;
+wire ropt_net_74 ;
+wire ropt_net_72 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_48 ) ) ;
+cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( right_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( right_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_6__5 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , 
+    .X ( ropt_net_73 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , 
+    .X ( ropt_net_75 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_15__14 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_top_in[3] ) , 
+    .X ( ropt_net_74 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_31__30 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[18] ) , 
+    .X ( ropt_net_72 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_43__42 ( 
+    .A ( right_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , 
+    .HI ( optlc_net_48 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1204 ( .A ( ropt_net_72 ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1205 ( .A ( ropt_net_73 ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1206 ( .A ( ropt_net_74 ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1207 ( .A ( ropt_net_75 ) , 
+    .X ( chany_top_out[8] ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.top_only.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..3d69c25
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.top_only.pt.v
@@ -0,0 +1,158 @@
+//
+//
+//
+//
+//
+//
+module cby_0__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , 
+    IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , 
+    right_width_0_height_0__pin_1_lower , prog_clk_0_E_in ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] left_grid_pin_0_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] right_width_0_height_0__pin_0_ ;
+output [0:0] right_width_0_height_0__pin_1_upper ;
+output [0:0] right_width_0_height_0__pin_1_lower ;
+input  prog_clk_0_E_in ;
+
+wire ropt_net_73 ;
+wire ropt_net_75 ;
+wire ropt_net_74 ;
+wire ropt_net_72 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_48 ) ) ;
+cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( right_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( right_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_6__5 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , 
+    .X ( ropt_net_73 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , 
+    .X ( ropt_net_75 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_15__14 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_top_in[3] ) , 
+    .X ( ropt_net_74 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_31__30 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[18] ) , 
+    .X ( ropt_net_72 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_43__42 ( 
+    .A ( right_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , 
+    .HI ( optlc_net_48 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1204 ( .A ( ropt_net_72 ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1205 ( .A ( ropt_net_73 ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1206 ( .A ( ropt_net_74 ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1207 ( .A ( ropt_net_75 ) , 
+    .X ( chany_top_out[8] ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v
new file mode 100644
index 0000000..3a8570c
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v
@@ -0,0 +1,1740 @@
+//
+//
+//
+//
+//
+//
+module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__const1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cby_1__1__const1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__const1_14 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cby_1__1__const1_14 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__const1_13 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cby_1__1__const1_13 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__const1_12 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cby_1__1__const1_12 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__const1_11 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cby_1__1__const1_11 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__const1_10 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cby_1__1__const1_10 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__const1_9 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cby_1__1__const1_9 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__const1_8 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cby_1__1__const1_8 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_100 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_81 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_81 ) , 
+    .X ( copt_net_82 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1314 ( .A ( copt_net_82 ) , 
+    .X ( copt_net_83 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1315 ( .A ( copt_net_83 ) , 
+    .X ( copt_net_84 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( copt_net_84 ) , 
+    .X ( copt_net_85 ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1324 ( .A ( copt_net_85 ) , 
+    .X ( copt_net_86 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1334 ( .A ( ropt_net_97 ) , 
+    .X ( ropt_net_96 ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1335 ( .A ( ropt_net_98 ) , 
+    .X ( ropt_net_97 ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1336 ( .A ( copt_net_86 ) , 
+    .X ( ropt_net_98 ) ) ;
+sky130_fd_sc_hd__buf_2 ropt_h_inst_1339 ( .A ( ropt_net_96 ) , 
+    .X ( ropt_net_100 ) ) ;
+endmodule
+
+
+module cby_1__1__const1_7 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_1__1__const1_7 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_75 ) ) ;
+endmodule
+
+
+module cby_1__1__const1_6 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_1__1__const1_6 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__const1_5 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_1__1__const1_5 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__const1_4 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_1__1__const1_4 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__const1_3 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_1__1__const1_3 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__const1_2 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_1__1__const1_2 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__const1_1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_1__1__const1_1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__const1_0 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_1__1__const1_0 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , 
+    left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , 
+    left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , 
+    left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , 
+    left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , 
+    left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in , 
+    Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out , 
+    Test_en_E_out , prog_clk_0_W_in , prog_clk_0_S_out , prog_clk_0_N_out , 
+    prog_clk_2_N_in , prog_clk_2_S_in , prog_clk_2_S_out , prog_clk_2_N_out , 
+    prog_clk_3_S_in , prog_clk_3_N_in , prog_clk_3_N_out , prog_clk_3_S_out , 
+    clk_2_N_in , clk_2_S_in , clk_2_S_out , clk_2_N_out , clk_3_S_in , 
+    clk_3_N_in , clk_3_N_out , clk_3_S_out ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input  Test_en_S_in ;
+input  Test_en_E_in ;
+input  Test_en_W_in ;
+output Test_en_N_out ;
+output Test_en_W_out ;
+output Test_en_E_out ;
+input  prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+input  prog_clk_2_N_in ;
+input  prog_clk_2_S_in ;
+output prog_clk_2_S_out ;
+output prog_clk_2_N_out ;
+input  prog_clk_3_S_in ;
+input  prog_clk_3_N_in ;
+output prog_clk_3_N_out ;
+output prog_clk_3_S_out ;
+input  clk_2_N_in ;
+input  clk_2_S_in ;
+output clk_2_S_out ;
+output clk_2_N_out ;
+input  clk_3_S_in ;
+input  clk_3_N_in ;
+output clk_3_N_out ;
+output clk_3_S_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign Test_en_S_in = Test_en_E_in ;
+assign Test_en_W_in = Test_en_E_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_2_N_in = prog_clk_2_S_in ;
+assign prog_clk_3_S_in = prog_clk_3_N_in ;
+assign clk_2_N_in = clk_2_S_in ;
+assign clk_3_S_in = clk_3_N_in ;
+
+cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , 
+        chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[8] , chany_bottom_out[8] , chany_top_out[14] , 
+        chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[11] , chany_bottom_out[11] , chany_top_out[17] , 
+        chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , 
+        chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[11] , chany_bottom_out[11] , chany_top_out[15] , 
+        chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_12 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[15] , chany_bottom_out[15] , chany_top_out[19] , 
+        chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { copt_net_87 } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[13] , chany_bottom_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[17] , chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[13] , chany_bottom_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[17] , chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_14 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__buf_4 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( ropt_net_94 ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( net_net_67 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_179 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_280 ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , 
+    .X ( ropt_net_93 ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , 
+    .X ( ZBUF_6_f_1 ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , 
+    .X ( prog_clk_3_N_out ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , 
+    .X ( ropt_net_95 ) ) ;
+sky130_fd_sc_hd__buf_4 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , 
+    .X ( clk_2_S_out ) ) ;
+sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , .X ( ZBUF_6_f_0 ) ) ;
+sky130_fd_sc_hd__buf_4 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , 
+    .X ( ropt_net_99 ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , 
+    .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[3] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_66 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( net_net_67 ) , .X ( Test_en_E_out ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( clk_3_S_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_69 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , 
+    .HI ( optlc_net_76 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , 
+    .HI ( optlc_net_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , 
+    .HI ( optlc_net_78 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1303 ( .A ( ZBUF_6_f_0 ) , 
+    .X ( clk_2_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , 
+    .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , 
+    .X ( prog_clk_0_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1304 ( .A ( ZBUF_6_f_1 ) , 
+    .X ( prog_clk_2_N_out ) ) ;
+sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1325 ( .A ( copt_net_91 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1337 ( .A ( ropt_net_99 ) , 
+    .X ( clk_3_N_out ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_87 ) , 
+    .X ( copt_net_90 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_92 ) , 
+    .X ( copt_net_91 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_90 ) , 
+    .X ( copt_net_92 ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1331 ( .A ( ropt_net_93 ) , 
+    .X ( prog_clk_2_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1332 ( .A ( ropt_net_94 ) , 
+    .X ( Test_en_W_out ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1333 ( .A ( ropt_net_95 ) , 
+    .X ( prog_clk_3_S_out ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v
new file mode 100644
index 0000000..940d0a2
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v
@@ -0,0 +1,1847 @@
+//
+//
+//
+//
+//
+//
+module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_100 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_81 ) , 
+    .X ( copt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1314 ( .A ( copt_net_82 ) , 
+    .X ( copt_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1315 ( .A ( copt_net_83 ) , 
+    .X ( copt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( copt_net_84 ) , 
+    .X ( copt_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1324 ( .A ( copt_net_85 ) , 
+    .X ( copt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1334 ( .A ( ropt_net_97 ) , 
+    .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1335 ( .A ( ropt_net_98 ) , 
+    .X ( ropt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1336 ( .A ( copt_net_86 ) , 
+    .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_2 ropt_h_inst_1339 ( .A ( ropt_net_96 ) , 
+    .X ( ropt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_1__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , 
+    left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , 
+    left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , 
+    left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , 
+    left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , 
+    left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in , 
+    Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out , 
+    Test_en_E_out , prog_clk_0_W_in , prog_clk_0_S_out , prog_clk_0_N_out , 
+    prog_clk_2_N_in , prog_clk_2_S_in , prog_clk_2_S_out , prog_clk_2_N_out , 
+    prog_clk_3_S_in , prog_clk_3_N_in , prog_clk_3_N_out , prog_clk_3_S_out , 
+    clk_2_N_in , clk_2_S_in , clk_2_S_out , clk_2_N_out , clk_3_S_in , 
+    clk_3_N_in , clk_3_N_out , clk_3_S_out , VDD , VSS ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input  Test_en_S_in ;
+input  Test_en_E_in ;
+input  Test_en_W_in ;
+output Test_en_N_out ;
+output Test_en_W_out ;
+output Test_en_E_out ;
+input  prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+input  prog_clk_2_N_in ;
+input  prog_clk_2_S_in ;
+output prog_clk_2_S_out ;
+output prog_clk_2_N_out ;
+input  prog_clk_3_S_in ;
+input  prog_clk_3_N_in ;
+output prog_clk_3_N_out ;
+output prog_clk_3_S_out ;
+input  clk_2_N_in ;
+input  clk_2_S_in ;
+output clk_2_S_out ;
+output clk_2_N_out ;
+input  clk_3_S_in ;
+input  clk_3_N_in ;
+output clk_3_N_out ;
+output clk_3_S_out ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
+
+assign Test_en_S_in = Test_en_E_in ;
+assign Test_en_W_in = Test_en_E_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_2_N_in = prog_clk_2_S_in ;
+assign prog_clk_3_S_in = prog_clk_3_N_in ;
+assign clk_2_N_in = clk_2_S_in ;
+assign clk_3_S_in = clk_3_N_in ;
+
+cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_78 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , 
+        chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[8] , chany_bottom_out[8] , chany_top_out[14] , 
+        chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[11] , chany_bottom_out[11] , chany_top_out[17] , 
+        chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , 
+        chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[11] , chany_bottom_out[11] , chany_top_out[15] , 
+        chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_12 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[15] , chany_bottom_out[15] , chany_top_out[19] , 
+        chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { copt_net_87 } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[13] , chany_bottom_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_78 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[17] , chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[13] , chany_bottom_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_78 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[17] , chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_14 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_4 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( net_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , 
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_280 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , 
+    .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , 
+    .X ( ZBUF_6_f_1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , 
+    .X ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , 
+    .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_4 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , 
+    .X ( clk_2_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , .X ( ZBUF_6_f_0 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_4 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , 
+    .X ( ropt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , 
+    .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) , 
+    .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[3] ) , 
+    .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( Test_en_N_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( net_net_67 ) , .X ( Test_en_E_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( clk_3_S_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , 
+    .HI ( optlc_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , 
+    .HI ( optlc_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , 
+    .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1303 ( .A ( ZBUF_6_f_0 ) , 
+    .X ( clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , 
+    .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , 
+    .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1304 ( .A ( ZBUF_6_f_1 ) , 
+    .X ( prog_clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1325 ( .A ( copt_net_91 ) , 
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1337 ( .A ( ropt_net_99 ) , 
+    .X ( clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_87 ) , 
+    .X ( copt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_92 ) , 
+    .X ( copt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_90 ) , 
+    .X ( copt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1331 ( .A ( ropt_net_93 ) , 
+    .X ( prog_clk_2_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1332 ( .A ( ropt_net_94 ) , 
+    .X ( Test_en_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1333 ( .A ( ropt_net_95 ) , 
+    .X ( prog_clk_3_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v
new file mode 100644
index 0000000..82186fb
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v
@@ -0,0 +1,1564 @@
+//
+//
+//
+//
+//
+//
+module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_100 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_81 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_81 ) , 
+    .X ( copt_net_82 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1314 ( .A ( copt_net_82 ) , 
+    .X ( copt_net_83 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1315 ( .A ( copt_net_83 ) , 
+    .X ( copt_net_84 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( copt_net_84 ) , 
+    .X ( copt_net_85 ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1324 ( .A ( copt_net_85 ) , 
+    .X ( copt_net_86 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1334 ( .A ( ropt_net_97 ) , 
+    .X ( ropt_net_96 ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1335 ( .A ( ropt_net_98 ) , 
+    .X ( ropt_net_97 ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1336 ( .A ( copt_net_86 ) , 
+    .X ( ropt_net_98 ) ) ;
+sky130_fd_sc_hd__buf_2 ropt_h_inst_1339 ( .A ( ropt_net_96 ) , 
+    .X ( ropt_net_100 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_75 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , 
+    left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , 
+    left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , 
+    left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , 
+    left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , 
+    left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in , 
+    Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out , 
+    Test_en_E_out , prog_clk_0_W_in , prog_clk_0_S_out , prog_clk_0_N_out , 
+    prog_clk_2_N_in , prog_clk_2_S_in , prog_clk_2_S_out , prog_clk_2_N_out , 
+    prog_clk_3_S_in , prog_clk_3_N_in , prog_clk_3_N_out , prog_clk_3_S_out , 
+    clk_2_N_in , clk_2_S_in , clk_2_S_out , clk_2_N_out , clk_3_S_in , 
+    clk_3_N_in , clk_3_N_out , clk_3_S_out ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input  Test_en_S_in ;
+input  Test_en_E_in ;
+input  Test_en_W_in ;
+output Test_en_N_out ;
+output Test_en_W_out ;
+output Test_en_E_out ;
+input  prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+input  prog_clk_2_N_in ;
+input  prog_clk_2_S_in ;
+output prog_clk_2_S_out ;
+output prog_clk_2_N_out ;
+input  prog_clk_3_S_in ;
+input  prog_clk_3_N_in ;
+output prog_clk_3_N_out ;
+output prog_clk_3_S_out ;
+input  clk_2_N_in ;
+input  clk_2_S_in ;
+output clk_2_S_out ;
+output clk_2_N_out ;
+input  clk_3_S_in ;
+input  clk_3_N_in ;
+output clk_3_N_out ;
+output clk_3_S_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign Test_en_E_in = Test_en_S_in ;
+assign Test_en_E_in = Test_en_W_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_2_S_in = prog_clk_2_N_in ;
+assign prog_clk_3_N_in = prog_clk_3_S_in ;
+assign clk_2_S_in = clk_2_N_in ;
+assign clk_3_N_in = clk_3_S_in ;
+
+cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , 
+        chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[8] , chany_bottom_out[8] , chany_top_out[14] , 
+        chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[11] , chany_bottom_out[11] , chany_top_out[17] , 
+        chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , 
+        chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[11] , chany_bottom_out[11] , chany_top_out[15] , 
+        chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_12 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[15] , chany_bottom_out[15] , chany_top_out[19] , 
+        chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { copt_net_87 } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[13] , chany_bottom_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[17] , chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[13] , chany_bottom_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[17] , chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_14 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__buf_4 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( ropt_net_94 ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( net_net_67 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_179 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_280 ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , 
+    .X ( ropt_net_93 ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , 
+    .X ( ZBUF_6_f_1 ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , 
+    .X ( prog_clk_3_N_out ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , 
+    .X ( ropt_net_95 ) ) ;
+sky130_fd_sc_hd__buf_4 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , 
+    .X ( clk_2_S_out ) ) ;
+sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , .X ( ZBUF_6_f_0 ) ) ;
+sky130_fd_sc_hd__buf_4 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , 
+    .X ( ropt_net_99 ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , 
+    .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[3] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_66 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( net_net_67 ) , .X ( Test_en_E_out ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( clk_3_S_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_69 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , 
+    .HI ( optlc_net_76 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , 
+    .HI ( optlc_net_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , 
+    .HI ( optlc_net_78 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1303 ( .A ( ZBUF_6_f_0 ) , 
+    .X ( clk_2_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , 
+    .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , 
+    .X ( prog_clk_0_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1304 ( .A ( ZBUF_6_f_1 ) , 
+    .X ( prog_clk_2_N_out ) ) ;
+sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1325 ( .A ( copt_net_91 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1337 ( .A ( ropt_net_99 ) , 
+    .X ( clk_3_N_out ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_87 ) , 
+    .X ( copt_net_90 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_92 ) , 
+    .X ( copt_net_91 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_90 ) , 
+    .X ( copt_net_92 ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1331 ( .A ( ropt_net_93 ) , 
+    .X ( prog_clk_2_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1332 ( .A ( ropt_net_94 ) , 
+    .X ( Test_en_W_out ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1333 ( .A ( ropt_net_95 ) , 
+    .X ( prog_clk_3_S_out ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.top_only.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..0eff2e7
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.top_only.pt.v
@@ -0,0 +1,471 @@
+//
+//
+//
+//
+//
+//
+module cby_1__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , 
+    left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , 
+    left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , 
+    left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , 
+    left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , 
+    left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in , 
+    Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out , 
+    Test_en_E_out , prog_clk_0_W_in , prog_clk_0_S_out , prog_clk_0_N_out , 
+    prog_clk_2_N_in , prog_clk_2_S_in , prog_clk_2_S_out , prog_clk_2_N_out , 
+    prog_clk_3_S_in , prog_clk_3_N_in , prog_clk_3_N_out , prog_clk_3_S_out , 
+    clk_2_N_in , clk_2_S_in , clk_2_S_out , clk_2_N_out , clk_3_S_in , 
+    clk_3_N_in , clk_3_N_out , clk_3_S_out ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input  Test_en_S_in ;
+input  Test_en_E_in ;
+input  Test_en_W_in ;
+output Test_en_N_out ;
+output Test_en_W_out ;
+output Test_en_E_out ;
+input  prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+input  prog_clk_2_N_in ;
+input  prog_clk_2_S_in ;
+output prog_clk_2_S_out ;
+output prog_clk_2_N_out ;
+input  prog_clk_3_S_in ;
+input  prog_clk_3_N_in ;
+output prog_clk_3_N_out ;
+output prog_clk_3_S_out ;
+input  clk_2_N_in ;
+input  clk_2_S_in ;
+output clk_2_S_out ;
+output clk_2_N_out ;
+input  clk_3_S_in ;
+input  clk_3_N_in ;
+output clk_3_N_out ;
+output clk_3_S_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign Test_en_E_in = Test_en_S_in ;
+assign Test_en_E_in = Test_en_W_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_2_S_in = prog_clk_2_N_in ;
+assign prog_clk_3_N_in = prog_clk_3_S_in ;
+assign clk_2_S_in = clk_2_N_in ;
+assign clk_3_N_in = clk_3_S_in ;
+
+cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , 
+        chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[8] , chany_bottom_out[8] , chany_top_out[14] , 
+        chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[11] , chany_bottom_out[11] , chany_top_out[17] , 
+        chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , 
+        chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[11] , chany_bottom_out[11] , chany_top_out[15] , 
+        chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_12 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[15] , chany_bottom_out[15] , chany_top_out[19] , 
+        chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { copt_net_87 } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[13] , chany_bottom_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[17] , chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[13] , chany_bottom_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[17] , chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_14 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__buf_4 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( ropt_net_94 ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( net_net_67 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_179 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_280 ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , 
+    .X ( ropt_net_93 ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , 
+    .X ( ZBUF_6_f_1 ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , 
+    .X ( prog_clk_3_N_out ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , 
+    .X ( ropt_net_95 ) ) ;
+sky130_fd_sc_hd__buf_4 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , 
+    .X ( clk_2_S_out ) ) ;
+sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , .X ( ZBUF_6_f_0 ) ) ;
+sky130_fd_sc_hd__buf_4 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , 
+    .X ( ropt_net_99 ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , 
+    .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[3] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_66 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( net_net_67 ) , .X ( Test_en_E_out ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( clk_3_S_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_69 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , 
+    .HI ( optlc_net_76 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , 
+    .HI ( optlc_net_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , 
+    .HI ( optlc_net_78 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1303 ( .A ( ZBUF_6_f_0 ) , 
+    .X ( clk_2_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , 
+    .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , 
+    .X ( prog_clk_0_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1304 ( .A ( ZBUF_6_f_1 ) , 
+    .X ( prog_clk_2_N_out ) ) ;
+sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1325 ( .A ( copt_net_91 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1337 ( .A ( ropt_net_99 ) , 
+    .X ( clk_3_N_out ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_87 ) , 
+    .X ( copt_net_90 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_92 ) , 
+    .X ( copt_net_91 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_90 ) , 
+    .X ( copt_net_92 ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1331 ( .A ( ropt_net_93 ) , 
+    .X ( prog_clk_2_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1332 ( .A ( ropt_net_94 ) , 
+    .X ( Test_en_W_out ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1333 ( .A ( ropt_net_95 ) , 
+    .X ( prog_clk_3_S_out ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v
new file mode 100644
index 0000000..c542fbf
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v
@@ -0,0 +1,1877 @@
+//
+//
+//
+//
+//
+//
+module cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( copt_net_90 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1312 ( .A ( mem_out[0] ) , 
+    .X ( copt_net_90 ) ) ;
+endmodule
+
+
+module cby_2__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , 
+    .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , 
+    .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( aps_rename_505_ ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_60 ) ) ;
+endmodule
+
+
+module cby_2__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head , 
+    iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cby_2__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cby_2__1__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__const1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cby_2__1__const1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__const1_15 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cby_2__1__const1_15 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__const1_14 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cby_2__1__const1_14 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__const1_13 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cby_2__1__const1_13 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__const1_12 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cby_2__1__const1_12 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__const1_11 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cby_2__1__const1_11 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__const1_10 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cby_2__1__const1_10 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__const1_9 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+cby_2__1__const1_9 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_89 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_86 ) , 
+    .X ( copt_net_82 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1305 ( .A ( copt_net_85 ) , 
+    .X ( copt_net_83 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_87 ) , 
+    .X ( copt_net_84 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_84 ) , 
+    .X ( copt_net_85 ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1308 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_86 ) ) ;
+sky130_fd_sc_hd__buf_2 copt_h_inst_1309 ( .A ( copt_net_82 ) , 
+    .X ( copt_net_87 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_83 ) , 
+    .X ( copt_net_88 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1311 ( .A ( copt_net_88 ) , 
+    .X ( copt_net_89 ) ) ;
+endmodule
+
+
+module cby_2__1__const1_8 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_2__1__const1_8 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__const1_7 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_2__1__const1_7 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_67 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__const1_6 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_2__1__const1_6 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_65 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__const1_5 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_2__1__const1_5 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__const1_4 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_2__1__const1_4 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_63 ) ) ;
+endmodule
+
+
+module cby_2__1__const1_3 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_2__1__const1_3 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__const1_2 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_2__1__const1_2 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__const1_1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_2__1__const1_1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__const1_0 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_2__1__const1_0 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , 
+    left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , 
+    left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , 
+    left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , 
+    left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , 
+    left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , 
+    IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , 
+    left_width_0_height_0__pin_1_lower , prog_clk_0_W_in , prog_clk_0_S_out , 
+    prog_clk_0_N_out ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] right_grid_pin_0_ ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] left_width_0_height_0__pin_0_ ;
+output [0:0] left_width_0_height_0__pin_1_upper ;
+output [0:0] left_width_0_height_0__pin_1_lower ;
+input  prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[11] , chany_bottom_out[11] , chany_top_out[17] , 
+        chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[8] , chany_bottom_out[8] , chany_top_out[14] , 
+        chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[9] , chany_bottom_out[9] , chany_top_out[15] , 
+        chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , 
+        chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , 
+        chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[17] , 
+        chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[15] , chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , 
+        chany_top_out[19] , chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[15] , chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , 
+        chany_top_out[19] , chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
+        SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( left_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( left_width_0_height_0__pin_1_lower ) ,
+    .ccff_tail ( { ropt_net_91 } ) ) ;
+sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_179 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_280 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[3] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( 
+    .A ( left_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( left_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , 
+    .HI ( optlc_net_75 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , 
+    .HI ( optlc_net_76 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , 
+    .HI ( optlc_net_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , 
+    .HI ( optlc_net_78 ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_h_inst_1313 ( .A ( ropt_net_92 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , 
+    .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , 
+    .X ( prog_clk_0_N_out ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , 
+    .X ( ropt_net_92 ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v
new file mode 100644
index 0000000..0959695
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v
@@ -0,0 +1,2014 @@
+//
+//
+//
+//
+//
+//
+module cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( copt_net_90 ) , 
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1312 ( .A ( mem_out[0] ) , 
+    .X ( copt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , 
+    .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , 
+    .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( aps_rename_505_ ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head , 
+    iopad_inpad , ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
+
+cby_2__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_89 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_86 ) , 
+    .X ( copt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1305 ( .A ( copt_net_85 ) , 
+    .X ( copt_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_87 ) , 
+    .X ( copt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_84 ) , 
+    .X ( copt_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1308 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_2 copt_h_inst_1309 ( .A ( copt_net_82 ) , 
+    .X ( copt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_83 ) , 
+    .X ( copt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1311 ( .A ( copt_net_88 ) , 
+    .X ( copt_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_65 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_2__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , 
+    left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , 
+    left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , 
+    left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , 
+    left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , 
+    left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , 
+    IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , 
+    left_width_0_height_0__pin_1_lower , prog_clk_0_W_in , prog_clk_0_S_out , 
+    prog_clk_0_N_out , VDD , VSS ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] right_grid_pin_0_ ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] left_width_0_height_0__pin_0_ ;
+output [0:0] left_width_0_height_0__pin_1_upper ;
+output [0:0] left_width_0_height_0__pin_1_lower ;
+input  prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[11] , chany_bottom_out[11] , chany_top_out[17] , 
+        chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_77 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[8] , chany_bottom_out[8] , chany_top_out[14] , 
+        chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[9] , chany_bottom_out[9] , chany_top_out[15] , 
+        chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , 
+        chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_78 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , 
+        chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[17] , 
+        chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_77 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[15] , chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_78 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , 
+        chany_top_out[19] , chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[15] , chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_77 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , 
+        chany_top_out[19] , chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
+        SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( left_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( left_width_0_height_0__pin_1_lower ) ,
+    .ccff_tail ( { ropt_net_91 } ) ,
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , 
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_280 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) , 
+    .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[3] ) , 
+    .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( 
+    .A ( left_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( left_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , 
+    .HI ( optlc_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , 
+    .HI ( optlc_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , 
+    .HI ( optlc_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , 
+    .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_h_inst_1313 ( .A ( ropt_net_92 ) , 
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , 
+    .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , 
+    .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , 
+    .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v
new file mode 100644
index 0000000..8698628
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v
@@ -0,0 +1,1690 @@
+//
+//
+//
+//
+//
+//
+module cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( copt_net_90 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1312 ( .A ( mem_out[0] ) , 
+    .X ( copt_net_90 ) ) ;
+endmodule
+
+
+module cby_2__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , 
+    .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , 
+    .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( aps_rename_505_ ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_60 ) ) ;
+endmodule
+
+
+module cby_2__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head , 
+    iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cby_2__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cby_2__1__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_89 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_86 ) , 
+    .X ( copt_net_82 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1305 ( .A ( copt_net_85 ) , 
+    .X ( copt_net_83 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_87 ) , 
+    .X ( copt_net_84 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_84 ) , 
+    .X ( copt_net_85 ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1308 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_86 ) ) ;
+sky130_fd_sc_hd__buf_2 copt_h_inst_1309 ( .A ( copt_net_82 ) , 
+    .X ( copt_net_87 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_83 ) , 
+    .X ( copt_net_88 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1311 ( .A ( copt_net_88 ) , 
+    .X ( copt_net_89 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_67 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_65 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_63 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , 
+    left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , 
+    left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , 
+    left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , 
+    left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , 
+    left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , 
+    IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , 
+    left_width_0_height_0__pin_1_lower , prog_clk_0_W_in , prog_clk_0_S_out , 
+    prog_clk_0_N_out ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] right_grid_pin_0_ ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] left_width_0_height_0__pin_0_ ;
+output [0:0] left_width_0_height_0__pin_1_upper ;
+output [0:0] left_width_0_height_0__pin_1_lower ;
+input  prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[11] , chany_bottom_out[11] , chany_top_out[17] , 
+        chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[8] , chany_bottom_out[8] , chany_top_out[14] , 
+        chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[9] , chany_bottom_out[9] , chany_top_out[15] , 
+        chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , 
+        chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , 
+        chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[17] , 
+        chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[15] , chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , 
+        chany_top_out[19] , chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[15] , chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , 
+        chany_top_out[19] , chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
+        SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( left_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( left_width_0_height_0__pin_1_lower ) ,
+    .ccff_tail ( { ropt_net_91 } ) ) ;
+sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_179 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_280 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[3] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( 
+    .A ( left_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( left_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , 
+    .HI ( optlc_net_75 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , 
+    .HI ( optlc_net_76 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , 
+    .HI ( optlc_net_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , 
+    .HI ( optlc_net_78 ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_h_inst_1313 ( .A ( ropt_net_92 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , 
+    .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , 
+    .X ( prog_clk_0_N_out ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , 
+    .X ( ropt_net_92 ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.top_only.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..45184b1
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.top_only.pt.v
@@ -0,0 +1,436 @@
+//
+//
+//
+//
+//
+//
+module cby_2__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , 
+    left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , 
+    left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , 
+    left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , 
+    left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , 
+    left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , 
+    IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , 
+    left_width_0_height_0__pin_1_lower , prog_clk_0_W_in , prog_clk_0_S_out , 
+    prog_clk_0_N_out ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] right_grid_pin_0_ ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] left_width_0_height_0__pin_0_ ;
+output [0:0] left_width_0_height_0__pin_1_upper ;
+output [0:0] left_width_0_height_0__pin_1_lower ;
+input  prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[11] , chany_bottom_out[11] , chany_top_out[17] , 
+        chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[8] , chany_bottom_out[8] , chany_top_out[14] , 
+        chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[9] , chany_bottom_out[9] , chany_top_out[15] , 
+        chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , 
+        chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , 
+        chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[17] , 
+        chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[15] , chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , 
+        chany_top_out[19] , chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[15] , chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , 
+        chany_top_out[19] , chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
+        SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( left_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( left_width_0_height_0__pin_1_lower ) ,
+    .ccff_tail ( { ropt_net_91 } ) ) ;
+sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_179 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_280 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[3] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( 
+    .A ( left_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( left_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , 
+    .HI ( optlc_net_75 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , 
+    .HI ( optlc_net_76 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , 
+    .HI ( optlc_net_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , 
+    .HI ( optlc_net_78 ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_h_inst_1313 ( .A ( ropt_net_92 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , 
+    .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , 
+    .X ( prog_clk_0_N_out ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , 
+    .X ( ropt_net_92 ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v
new file mode 100644
index 0000000..2d0391a
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v
@@ -0,0 +1,1598 @@
+//
+//
+//
+//
+//
+//
+module sb_0__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__const1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_0__0__const1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_73 ) ) ;
+endmodule
+
+
+module sb_0__0__const1_22 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_0__0__const1_22 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__const1_21 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_0__0__const1_21 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__const1_20 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_0__0__const1_20 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__const1_19 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_0__0__const1_19 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__const1_18 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_0__0__const1_18 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_71 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_91 ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_1 copt_h_inst_1251 ( .A ( mem_out[1] ) , 
+    .X ( copt_net_87 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_87 ) , 
+    .X ( copt_net_88 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_88 ) , 
+    .X ( copt_net_89 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_89 ) , 
+    .X ( copt_net_90 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_90 ) , 
+    .X ( copt_net_91 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1244 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_80 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1245 ( .A ( copt_net_80 ) , 
+    .X ( copt_net_81 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1246 ( .A ( copt_net_85 ) , 
+    .X ( copt_net_82 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1247 ( .A ( copt_net_81 ) , 
+    .X ( copt_net_83 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1248 ( .A ( copt_net_82 ) , 
+    .X ( copt_net_84 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1249 ( .A ( copt_net_83 ) , 
+    .X ( copt_net_85 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( copt_net_84 ) , 
+    .X ( ropt_net_115 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1280 ( .A ( ropt_net_115 ) , 
+    .X ( ropt_net_116 ) ) ;
+endmodule
+
+
+module sb_0__0__const1_17 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_17 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_69 ) ) ;
+endmodule
+
+
+module sb_0__0__const1_16 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_16 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_67 ) ) ;
+endmodule
+
+
+module sb_0__0__const1_15 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_15 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_65 ) ) ;
+endmodule
+
+
+module sb_0__0__const1_14 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_14 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_63 ) ) ;
+endmodule
+
+
+module sb_0__0__const1_13 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_13 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_61 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__const1_12 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_12 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_58 ( .A ( BUF_net_59 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_59 ) ) ;
+endmodule
+
+
+module sb_0__0__const1_11 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_11 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__const1_10 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_10 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_57 ) ) ;
+endmodule
+
+
+module sb_0__0__const1_9 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_9 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_55 ) ) ;
+endmodule
+
+
+module sb_0__0__const1_8 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_8 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_53 ) ) ;
+endmodule
+
+
+module sb_0__0__const1_7 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_7 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_51 ) ) ;
+endmodule
+
+
+module sb_0__0__const1_6 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_6 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_48 ( .A ( BUF_net_49 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_49 ) ) ;
+endmodule
+
+
+module sb_0__0__const1_5 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_5 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_46 ( .A ( BUF_net_47 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_47 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_47 ) ) ;
+endmodule
+
+
+module sb_0__0__const1_4 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_4 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_45 ) ) ;
+endmodule
+
+
+module sb_0__0__const1_3 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_3 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__const1_2 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_2 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_43 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__const1_1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__const1_0 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__0__const1_0 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_40 ( .A ( BUF_net_41 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_41 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_41 ) ) ;
+endmodule
+
+
+module sb_0__0_ ( chany_top_in , top_left_grid_pin_1_ , chanx_right_in , 
+    right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , 
+    right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , 
+    right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , 
+    right_bottom_grid_pin_13_ , right_bottom_grid_pin_15_ , 
+    right_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , 
+    ccff_tail , prog_clk_0_E_in ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_1_ ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_bottom_grid_pin_1_ ;
+input  [0:0] right_bottom_grid_pin_3_ ;
+input  [0:0] right_bottom_grid_pin_5_ ;
+input  [0:0] right_bottom_grid_pin_7_ ;
+input  [0:0] right_bottom_grid_pin_9_ ;
+input  [0:0] right_bottom_grid_pin_11_ ;
+input  [0:0] right_bottom_grid_pin_13_ ;
+input  [0:0] right_bottom_grid_pin_15_ ;
+input  [0:0] right_bottom_grid_pin_17_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:0] ccff_tail ;
+input  prog_clk_0_E_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_4 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_8 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_24 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_10 (
+    .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) ,
+    .out ( chanx_right_out[5] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_12 (
+    .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_right_out[6] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_14 (
+    .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) ,
+    .out ( chanx_right_out[7] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_16 (
+    .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_18 (
+    .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chanx_right_out[9] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_20 (
+    .in ( { chany_top_in[9] , right_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chanx_right_out[10] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_22 (
+    .in ( { chany_top_in[10] , right_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
+    .out ( chanx_right_out[11] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 (
+    .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_right_out[13] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_28 (
+    .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+    .out ( chanx_right_out[14] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_30 (
+    .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_right_out[15] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_32 (
+    .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_34 (
+    .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_right_out[17] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_36 (
+    .in ( { chany_top_in[17] , right_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chanx_right_out[18] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2 mux_right_track_38 (
+    .in ( { chany_top_in[18] , right_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chanx_right_out[19] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem mem_right_track_38 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size6_0 mux_right_track_0 (
+    .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , 
+        right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 (
+    .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , 
+        right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , 
+        SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size6_mem mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size5_0 mux_right_track_2 (
+    .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , 
+        right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , 
+        right_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , 
+        SYNOPSYS_UNCONNECTED_45 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 (
+    .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , 
+        right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , 
+        right_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , 
+        SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chanx_right_out[3] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size5_mem mem_right_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_8 (
+    .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size3 mux_right_track_24 (
+    .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_mem mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_25__24 ( .A ( chanx_right_in[0] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chanx_right_in[2] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( chanx_right_in[4] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[6] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[7] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[8] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[9] ) , 
+    .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[10] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( chanx_right_in[11] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[12] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[14] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[15] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[16] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[17] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[18] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , 
+    .HI ( optlc_net_76 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , 
+    .HI ( optlc_net_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , 
+    .HI ( optlc_net_78 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , 
+    .HI ( optlc_net_79 ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v
new file mode 100644
index 0000000..dc78144
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v
@@ -0,0 +1,1683 @@
+//
+//
+//
+//
+//
+//
+module sb_0__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_91 ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 copt_h_inst_1251 ( .A ( mem_out[1] ) , 
+    .X ( copt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_87 ) , 
+    .X ( copt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_88 ) , 
+    .X ( copt_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_89 ) , 
+    .X ( copt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_90 ) , 
+    .X ( copt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1244 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1245 ( .A ( copt_net_80 ) , 
+    .X ( copt_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1246 ( .A ( copt_net_85 ) , 
+    .X ( copt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1247 ( .A ( copt_net_81 ) , 
+    .X ( copt_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1248 ( .A ( copt_net_82 ) , 
+    .X ( copt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1249 ( .A ( copt_net_83 ) , 
+    .X ( copt_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( copt_net_84 ) , 
+    .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1280 ( .A ( ropt_net_115 ) , 
+    .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_61 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_58 ( .A ( BUF_net_59 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_48 ( .A ( BUF_net_49 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_46 ( .A ( BUF_net_47 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_47 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_47 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_45 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_43 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_40 ( .A ( BUF_net_41 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_41 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_41 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__0_ ( chany_top_in , top_left_grid_pin_1_ , chanx_right_in , 
+    right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , 
+    right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , 
+    right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , 
+    right_bottom_grid_pin_13_ , right_bottom_grid_pin_15_ , 
+    right_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , 
+    ccff_tail , prog_clk_0_E_in , VDD , VSS ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_1_ ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_bottom_grid_pin_1_ ;
+input  [0:0] right_bottom_grid_pin_3_ ;
+input  [0:0] right_bottom_grid_pin_5_ ;
+input  [0:0] right_bottom_grid_pin_7_ ;
+input  [0:0] right_bottom_grid_pin_9_ ;
+input  [0:0] right_bottom_grid_pin_11_ ;
+input  [0:0] right_bottom_grid_pin_13_ ;
+input  [0:0] right_bottom_grid_pin_15_ ;
+input  [0:0] right_bottom_grid_pin_17_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:0] ccff_tail ;
+input  prog_clk_0_E_in ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_4 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_8 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_24 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_10 (
+    .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) ,
+    .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_12 (
+    .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_14 (
+    .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) ,
+    .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_16 (
+    .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_18 (
+    .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_20 (
+    .in ( { chany_top_in[9] , right_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_22 (
+    .in ( { chany_top_in[10] , right_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
+    .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 (
+    .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_28 (
+    .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+    .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_30 (
+    .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_32 (
+    .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_34 (
+    .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_36 (
+    .in ( { chany_top_in[17] , right_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2 mux_right_track_38 (
+    .in ( { chany_top_in[18] , right_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem mem_right_track_38 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size6_0 mux_right_track_0 (
+    .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , 
+        right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 } ) ,
+    .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 (
+    .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , 
+        right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , 
+        SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size6_mem mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size5_0 mux_right_track_2 (
+    .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , 
+        right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , 
+        right_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , 
+        SYNOPSYS_UNCONNECTED_45 } ) ,
+    .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 (
+    .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , 
+        right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , 
+        right_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , 
+        SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size5_mem mem_right_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_8 (
+    .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size3 mux_right_track_24 (
+    .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_mem mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_25__24 ( .A ( chanx_right_in[0] ) , 
+    .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chanx_right_in[2] ) , 
+    .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( chanx_right_in[4] ) , 
+    .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[6] ) , 
+    .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[7] ) , 
+    .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[8] ) , 
+    .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[9] ) , 
+    .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[10] ) , 
+    .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( chanx_right_in[11] ) , 
+    .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[12] ) , 
+    .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[14] ) , 
+    .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[15] ) , 
+    .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[16] ) , 
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[17] ) , 
+    .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[18] ) , 
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , 
+    .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , 
+    .HI ( optlc_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , 
+    .HI ( optlc_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , 
+    .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , 
+    .HI ( optlc_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v
new file mode 100644
index 0000000..a86c965
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v
@@ -0,0 +1,1334 @@
+//
+//
+//
+//
+//
+//
+module sb_0__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_73 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_71 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_91 ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_1 copt_h_inst_1251 ( .A ( mem_out[1] ) , 
+    .X ( copt_net_87 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_87 ) , 
+    .X ( copt_net_88 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_88 ) , 
+    .X ( copt_net_89 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_89 ) , 
+    .X ( copt_net_90 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_90 ) , 
+    .X ( copt_net_91 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1244 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_80 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1245 ( .A ( copt_net_80 ) , 
+    .X ( copt_net_81 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1246 ( .A ( copt_net_85 ) , 
+    .X ( copt_net_82 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1247 ( .A ( copt_net_81 ) , 
+    .X ( copt_net_83 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1248 ( .A ( copt_net_82 ) , 
+    .X ( copt_net_84 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1249 ( .A ( copt_net_83 ) , 
+    .X ( copt_net_85 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( copt_net_84 ) , 
+    .X ( ropt_net_115 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1280 ( .A ( ropt_net_115 ) , 
+    .X ( ropt_net_116 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_69 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_67 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_65 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_63 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_61 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_58 ( .A ( BUF_net_59 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_59 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_57 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_55 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_53 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_51 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_48 ( .A ( BUF_net_49 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_49 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_46 ( .A ( BUF_net_47 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_47 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_47 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_45 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_43 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_40 ( .A ( BUF_net_41 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_41 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_41 ) ) ;
+endmodule
+
+
+module sb_0__0_ ( chany_top_in , top_left_grid_pin_1_ , chanx_right_in , 
+    right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , 
+    right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , 
+    right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , 
+    right_bottom_grid_pin_13_ , right_bottom_grid_pin_15_ , 
+    right_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , 
+    ccff_tail , prog_clk_0_E_in ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_1_ ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_bottom_grid_pin_1_ ;
+input  [0:0] right_bottom_grid_pin_3_ ;
+input  [0:0] right_bottom_grid_pin_5_ ;
+input  [0:0] right_bottom_grid_pin_7_ ;
+input  [0:0] right_bottom_grid_pin_9_ ;
+input  [0:0] right_bottom_grid_pin_11_ ;
+input  [0:0] right_bottom_grid_pin_13_ ;
+input  [0:0] right_bottom_grid_pin_15_ ;
+input  [0:0] right_bottom_grid_pin_17_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:0] ccff_tail ;
+input  prog_clk_0_E_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_4 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_8 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_24 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_10 (
+    .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) ,
+    .out ( chanx_right_out[5] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_12 (
+    .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_right_out[6] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_14 (
+    .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) ,
+    .out ( chanx_right_out[7] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_16 (
+    .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_18 (
+    .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chanx_right_out[9] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_20 (
+    .in ( { chany_top_in[9] , right_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chanx_right_out[10] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_22 (
+    .in ( { chany_top_in[10] , right_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
+    .out ( chanx_right_out[11] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 (
+    .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_right_out[13] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_28 (
+    .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+    .out ( chanx_right_out[14] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_30 (
+    .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_right_out[15] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_32 (
+    .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_34 (
+    .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_right_out[17] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_36 (
+    .in ( { chany_top_in[17] , right_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chanx_right_out[18] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2 mux_right_track_38 (
+    .in ( { chany_top_in[18] , right_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chanx_right_out[19] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem mem_right_track_38 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size6_0 mux_right_track_0 (
+    .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , 
+        right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 (
+    .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , 
+        right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , 
+        SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size6_mem mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size5_0 mux_right_track_2 (
+    .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , 
+        right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , 
+        right_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , 
+        SYNOPSYS_UNCONNECTED_45 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 (
+    .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , 
+        right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , 
+        right_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , 
+        SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chanx_right_out[3] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size5_mem mem_right_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_8 (
+    .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size3 mux_right_track_24 (
+    .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_mem mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_25__24 ( .A ( chanx_right_in[0] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chanx_right_in[2] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( chanx_right_in[4] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[6] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[7] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[8] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[9] ) , 
+    .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[10] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( chanx_right_in[11] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[12] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[14] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[15] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[16] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[17] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[18] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , 
+    .HI ( optlc_net_76 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , 
+    .HI ( optlc_net_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , 
+    .HI ( optlc_net_78 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , 
+    .HI ( optlc_net_79 ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.top_only.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..f92a7f4
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.top_only.pt.v
@@ -0,0 +1,380 @@
+//
+//
+//
+//
+//
+//
+module sb_0__0_ ( chany_top_in , top_left_grid_pin_1_ , chanx_right_in , 
+    right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , 
+    right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , 
+    right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , 
+    right_bottom_grid_pin_13_ , right_bottom_grid_pin_15_ , 
+    right_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , 
+    ccff_tail , prog_clk_0_E_in ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_1_ ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_bottom_grid_pin_1_ ;
+input  [0:0] right_bottom_grid_pin_3_ ;
+input  [0:0] right_bottom_grid_pin_5_ ;
+input  [0:0] right_bottom_grid_pin_7_ ;
+input  [0:0] right_bottom_grid_pin_9_ ;
+input  [0:0] right_bottom_grid_pin_11_ ;
+input  [0:0] right_bottom_grid_pin_13_ ;
+input  [0:0] right_bottom_grid_pin_15_ ;
+input  [0:0] right_bottom_grid_pin_17_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:0] ccff_tail ;
+input  prog_clk_0_E_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_4 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_8 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_24 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_10 (
+    .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) ,
+    .out ( chanx_right_out[5] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_12 (
+    .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_right_out[6] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_14 (
+    .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) ,
+    .out ( chanx_right_out[7] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_16 (
+    .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_18 (
+    .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chanx_right_out[9] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_20 (
+    .in ( { chany_top_in[9] , right_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chanx_right_out[10] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_22 (
+    .in ( { chany_top_in[10] , right_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
+    .out ( chanx_right_out[11] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 (
+    .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_right_out[13] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_28 (
+    .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+    .out ( chanx_right_out[14] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_30 (
+    .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_right_out[15] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_32 (
+    .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_34 (
+    .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_right_out[17] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_36 (
+    .in ( { chany_top_in[17] , right_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chanx_right_out[18] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2 mux_right_track_38 (
+    .in ( { chany_top_in[18] , right_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chanx_right_out[19] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem mem_right_track_38 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size6_0 mux_right_track_0 (
+    .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , 
+        right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 (
+    .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , 
+        right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , 
+        SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size6_mem mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size5_0 mux_right_track_2 (
+    .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , 
+        right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , 
+        right_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , 
+        SYNOPSYS_UNCONNECTED_45 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 (
+    .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , 
+        right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , 
+        right_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , 
+        SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chanx_right_out[3] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size5_mem mem_right_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_8 (
+    .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size3 mux_right_track_24 (
+    .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_76 ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_mem mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_25__24 ( .A ( chanx_right_in[0] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chanx_right_in[2] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( chanx_right_in[4] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[6] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[7] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[8] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[9] ) , 
+    .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[10] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( chanx_right_in[11] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[12] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[14] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[15] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[16] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[17] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[18] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , 
+    .HI ( optlc_net_76 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , 
+    .HI ( optlc_net_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , 
+    .HI ( optlc_net_78 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , 
+    .HI ( optlc_net_79 ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v
new file mode 100644
index 0000000..9381cf8
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v
@@ -0,0 +1,2470 @@
+//
+//
+//
+//
+//
+//
+module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__1__const1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_31 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__1__const1_31 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_97 ) ) ;
+endmodule
+
+
+module sb_0__1__const1_30 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__1__const1_30 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_29 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__1__const1_29 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_107 ) ) ;
+endmodule
+
+
+module sb_0__1__const1_28 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__1__const1_28 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_93 ) ) ;
+endmodule
+
+
+module sb_0__1__const1_27 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__1__const1_27 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_91 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_100 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+wire copt_net_125 ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_125 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_125 ) , 
+    .X ( copt_net_120 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_120 ) , 
+    .X ( copt_net_121 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_121 ) , 
+    .X ( copt_net_122 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_122 ) , 
+    .X ( copt_net_123 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_123 ) , 
+    .X ( copt_net_124 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_124 ) , 
+    .X ( mem_out[1] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_26 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_0__1__const1_26 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_89 ) ) ;
+endmodule
+
+
+module sb_0__1__const1_25 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_0__1__const1_25 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_24 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_0__1__const1_24 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_23 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_0__1__const1_23 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_85 ) ) ;
+endmodule
+
+
+module sb_0__1__const1_22 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_0__1__const1_22 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_21 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_0__1__const1_21 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_83 ) ) ;
+endmodule
+
+
+module sb_0__1__const1_20 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_0__1__const1_20 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_81 ) ) ;
+endmodule
+
+
+module sb_0__1__const1_19 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_0__1__const1_19 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_18 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sb_0__1__const1_18 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .Y ( BUF_net_78 ) ) ;
+endmodule
+
+
+module sb_0__1__const1_17 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sb_0__1__const1_17 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .Y ( BUF_net_76 ) ) ;
+endmodule
+
+
+module sb_0__1__const1_16 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sb_0__1__const1_16 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_15 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sb_0__1__const1_15 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .Y ( BUF_net_74 ) ) ;
+endmodule
+
+
+module sb_0__1__const1_14 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sb_0__1__const1_14 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .Y ( BUF_net_72 ) ) ;
+endmodule
+
+
+module sb_0__1__const1_13 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sb_0__1__const1_13 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_12 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sb_0__1__const1_12 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_11 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_0__1__const1_11 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_69 ) ) ;
+endmodule
+
+
+module sb_0__1__const1_10 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_0__1__const1_10 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_9 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_0__1__const1_9 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_8 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_0__1__const1_8 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_67 ) ) ;
+endmodule
+
+
+module sb_0__1__const1_7 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_0__1__const1_7 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_65 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_129 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_115 ) , 
+    .X ( copt_net_114 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_115 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_114 ) , 
+    .X ( copt_net_116 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_119 ) , 
+    .X ( copt_net_117 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_116 ) , 
+    .X ( copt_net_118 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_118 ) , 
+    .X ( copt_net_119 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1289 ( .A ( copt_net_117 ) , 
+    .X ( ropt_net_127 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1290 ( .A ( ropt_net_127 ) , 
+    .X ( ropt_net_128 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1291 ( .A ( ropt_net_128 ) , 
+    .X ( ropt_net_129 ) ) ;
+endmodule
+
+
+module sb_0__1__const1_6 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_0__1__const1_6 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_5 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_0__1__const1_5 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_4 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_0__1__const1_4 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_3 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_0__1__const1_3 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_2 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_0__1__const1_2 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_0__1__const1_1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_62 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_104 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__const1_0 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_0__1__const1_0 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1_ ( chany_top_in , top_left_grid_pin_1_ , chanx_right_in , 
+    right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , 
+    right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , 
+    right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , 
+    right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , 
+    bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , 
+    chany_bottom_out , ccff_tail , prog_clk_0_E_in ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_1_ ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_bottom_grid_pin_34_ ;
+input  [0:0] right_bottom_grid_pin_35_ ;
+input  [0:0] right_bottom_grid_pin_36_ ;
+input  [0:0] right_bottom_grid_pin_37_ ;
+input  [0:0] right_bottom_grid_pin_38_ ;
+input  [0:0] right_bottom_grid_pin_39_ ;
+input  [0:0] right_bottom_grid_pin_40_ ;
+input  [0:0] right_bottom_grid_pin_41_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_left_grid_pin_1_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:0] ccff_tail ;
+input  prog_clk_0_E_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:2] mux_tree_tapbuf_size4_4_sram ;
+wire [0:2] mux_tree_tapbuf_size4_5_sram ;
+wire [0:2] mux_tree_tapbuf_size4_6_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:2] mux_tree_tapbuf_size5_4_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:2] mux_tree_tapbuf_size6_4_sram ;
+wire [0:2] mux_tree_tapbuf_size6_5_sram ;
+wire [0:2] mux_tree_tapbuf_size6_6_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , 
+        chanx_right_in[15] , chany_top_out[3] , chany_top_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_4 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , 
+        chanx_right_in[17] , chany_top_out[6] , chany_top_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , 
+        SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_8 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , 
+        chanx_right_in[18] , chany_top_out[7] , chany_top_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , 
+        SYNOPSYS_UNCONNECTED_9 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 (
+    .in ( { chany_bottom_out[3] , right_bottom_grid_pin_34_[0] , 
+        right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , 
+        right_bottom_grid_pin_40_[0] , chany_top_out[3] } ) ,
+    .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , 
+        SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_4 mux_bottom_track_1 (
+    .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_right_in[5] , 
+        chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_5 mux_bottom_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_right_in[3] , 
+        chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , 
+        SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_9 (
+    .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[2] , 
+        chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , 
+        SYNOPSYS_UNCONNECTED_21 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 (
+    .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , 
+        chany_top_out[5] , chany_top_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , 
+        SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chany_top_out[1] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_16 (
+    .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , 
+        chany_top_out[9] , chany_top_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 } ) ,
+    .out ( chany_top_out[8] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_right_in[4] , 
+        chanx_right_in[11] , chanx_right_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , 
+        SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_3 mux_bottom_track_17 (
+    .in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] , 
+        chanx_right_in[8] , chanx_right_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , 
+        SYNOPSYS_UNCONNECTED_33 } ) ,
+    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_25 (
+    .in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] , 
+        chanx_right_in[7] , chanx_right_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size5_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , 
+        SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_24 (
+    .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_top_out[10] , 
+        chany_top_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_32 (
+    .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , 
+        chany_top_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , 
+        SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chany_top_out[16] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_8 (
+    .in ( { chany_top_in[7] , chany_bottom_out[9] , 
+        right_bottom_grid_pin_34_[0] , chany_top_out[9] } ) ,
+    .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , 
+        SYNOPSYS_UNCONNECTED_45 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_10 (
+    .in ( { chany_bottom_out[10] , chany_top_in[11] , 
+        right_bottom_grid_pin_35_[0] , chany_top_out[10] } ) ,
+    .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , 
+        SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chanx_right_out[5] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_12 (
+    .in ( { chany_bottom_out[11] , chany_top_in[15] , 
+        right_bottom_grid_pin_36_[0] , chany_top_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size4_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 } ) ,
+    .out ( chanx_right_out[6] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_14 (
+    .in ( { chany_bottom_out[13] , chany_top_in[19] , 
+        right_bottom_grid_pin_37_[0] , chany_top_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size4_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , 
+        SYNOPSYS_UNCONNECTED_54 } ) ,
+    .out ( chanx_right_out[7] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4 mux_right_track_24 (
+    .in ( { chany_bottom_out[19] , right_bottom_grid_pin_34_[0] , 
+        chany_top_out[19] , chany_bottom_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size4_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , 
+        SYNOPSYS_UNCONNECTED_57 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_top_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_right_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 (
+    .in ( { chany_top_in[0] , chany_bottom_out[5] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_39_[0] , chanx_right_out[19] , 
+        chany_top_out[5] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , 
+        SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 (
+    .in ( { chany_top_in[1] , chany_bottom_out[6] , 
+        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_top_out[6] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 (
+    .in ( { chany_top_in[3] , chany_bottom_out[7] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_39_[0] , chanx_right_out[19] , 
+        chany_top_out[7] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , 
+        SYNOPSYS_UNCONNECTED_66 } ) ,
+    .out ( chanx_right_out[3] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_0 mux_right_track_16 (
+    .in ( { chany_bottom_out[14] , right_bottom_grid_pin_38_[0] , 
+        chany_top_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_18 (
+    .in ( { chany_bottom_out[15] , right_bottom_grid_pin_39_[0] , 
+        chany_top_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+    .out ( chanx_right_out[9] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_20 (
+    .in ( { chany_bottom_out[17] , right_bottom_grid_pin_40_[0] , 
+        chany_top_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chanx_right_out[10] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_22 (
+    .in ( { chany_bottom_out[18] , chanx_right_out[19] , chany_top_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chanx_right_out[11] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_33 (
+    .in ( { chany_bottom_out[11] , chanx_right_in[6] , chanx_right_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem mem_bottom_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 (
+    .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chanx_right_out[13] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 (
+    .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+    .out ( chanx_right_out[14] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 (
+    .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+    .out ( chanx_right_out[15] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 (
+    .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 (
+    .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
+    .out ( chanx_right_out[17] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 (
+    .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+    .out ( chanx_right_out[18] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( right_bottom_grid_pin_41_[0] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , 
+    .HI ( optlc_net_110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , 
+    .HI ( optlc_net_111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , 
+    .HI ( optlc_net_112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , 
+    .HI ( optlc_net_113 ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v
new file mode 100644
index 0000000..d31f87b
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v
@@ -0,0 +1,2613 @@
+//
+//
+//
+//
+//
+//
+module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_100 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+wire copt_net_125 ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_125 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_125 ) , 
+    .X ( copt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_120 ) , 
+    .X ( copt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_121 ) , 
+    .X ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_122 ) , 
+    .X ( copt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_123 ) , 
+    .X ( copt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_124 ) , 
+    .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_129 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_115 ) , 
+    .X ( copt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_114 ) , 
+    .X ( copt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_119 ) , 
+    .X ( copt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_116 ) , 
+    .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_118 ) , 
+    .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1289 ( .A ( copt_net_117 ) , 
+    .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1290 ( .A ( ropt_net_127 ) , 
+    .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1291 ( .A ( ropt_net_128 ) , 
+    .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_104 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__1_ ( chany_top_in , top_left_grid_pin_1_ , chanx_right_in , 
+    right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , 
+    right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , 
+    right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , 
+    right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , 
+    bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , 
+    chany_bottom_out , ccff_tail , prog_clk_0_E_in , VDD , VSS ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_1_ ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_bottom_grid_pin_34_ ;
+input  [0:0] right_bottom_grid_pin_35_ ;
+input  [0:0] right_bottom_grid_pin_36_ ;
+input  [0:0] right_bottom_grid_pin_37_ ;
+input  [0:0] right_bottom_grid_pin_38_ ;
+input  [0:0] right_bottom_grid_pin_39_ ;
+input  [0:0] right_bottom_grid_pin_40_ ;
+input  [0:0] right_bottom_grid_pin_41_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_left_grid_pin_1_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:0] ccff_tail ;
+input  prog_clk_0_E_in ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:2] mux_tree_tapbuf_size4_4_sram ;
+wire [0:2] mux_tree_tapbuf_size4_5_sram ;
+wire [0:2] mux_tree_tapbuf_size4_6_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:2] mux_tree_tapbuf_size5_4_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:2] mux_tree_tapbuf_size6_4_sram ;
+wire [0:2] mux_tree_tapbuf_size6_5_sram ;
+wire [0:2] mux_tree_tapbuf_size6_6_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , 
+        chanx_right_in[15] , chany_top_out[3] , chany_top_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 } ) ,
+    .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_4 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , 
+        chanx_right_in[17] , chany_top_out[6] , chany_top_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , 
+        SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_8 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , 
+        chanx_right_in[18] , chany_top_out[7] , chany_top_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , 
+        SYNOPSYS_UNCONNECTED_9 } ) ,
+    .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 (
+    .in ( { chany_bottom_out[3] , right_bottom_grid_pin_34_[0] , 
+        right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , 
+        right_bottom_grid_pin_40_[0] , chany_top_out[3] } ) ,
+    .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , 
+        SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_4 mux_bottom_track_1 (
+    .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_right_in[5] , 
+        chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 } ) ,
+    .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_5 mux_bottom_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_right_in[3] , 
+        chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , 
+        SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_9 (
+    .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[2] , 
+        chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , 
+        SYNOPSYS_UNCONNECTED_21 } ) ,
+    .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 (
+    .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , 
+        chany_top_out[5] , chany_top_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , 
+        SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_16 (
+    .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , 
+        chany_top_out[9] , chany_top_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 } ) ,
+    .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_right_in[4] , 
+        chanx_right_in[11] , chanx_right_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , 
+        SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_3 mux_bottom_track_17 (
+    .in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] , 
+        chanx_right_in[8] , chanx_right_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , 
+        SYNOPSYS_UNCONNECTED_33 } ) ,
+    .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_25 (
+    .in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] , 
+        chanx_right_in[7] , chanx_right_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size5_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , 
+        SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_24 (
+    .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_top_out[10] , 
+        chany_top_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 } ) ,
+    .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_32 (
+    .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , 
+        chany_top_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , 
+        SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_8 (
+    .in ( { chany_top_in[7] , chany_bottom_out[9] , 
+        right_bottom_grid_pin_34_[0] , chany_top_out[9] } ) ,
+    .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , 
+        SYNOPSYS_UNCONNECTED_45 } ) ,
+    .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_10 (
+    .in ( { chany_bottom_out[10] , chany_top_in[11] , 
+        right_bottom_grid_pin_35_[0] , chany_top_out[10] } ) ,
+    .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , 
+        SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_12 (
+    .in ( { chany_bottom_out[11] , chany_top_in[15] , 
+        right_bottom_grid_pin_36_[0] , chany_top_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size4_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 } ) ,
+    .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_14 (
+    .in ( { chany_bottom_out[13] , chany_top_in[19] , 
+        right_bottom_grid_pin_37_[0] , chany_top_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size4_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , 
+        SYNOPSYS_UNCONNECTED_54 } ) ,
+    .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4 mux_right_track_24 (
+    .in ( { chany_bottom_out[19] , right_bottom_grid_pin_34_[0] , 
+        chany_top_out[19] , chany_bottom_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size4_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , 
+        SYNOPSYS_UNCONNECTED_57 } ) ,
+    .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_top_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_right_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 (
+    .in ( { chany_top_in[0] , chany_bottom_out[5] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_39_[0] , chanx_right_out[19] , 
+        chany_top_out[5] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , 
+        SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 (
+    .in ( { chany_top_in[1] , chany_bottom_out[6] , 
+        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_top_out[6] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 } ) ,
+    .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 (
+    .in ( { chany_top_in[3] , chany_bottom_out[7] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_39_[0] , chanx_right_out[19] , 
+        chany_top_out[7] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , 
+        SYNOPSYS_UNCONNECTED_66 } ) ,
+    .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_0 mux_right_track_16 (
+    .in ( { chany_bottom_out[14] , right_bottom_grid_pin_38_[0] , 
+        chany_top_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_18 (
+    .in ( { chany_bottom_out[15] , right_bottom_grid_pin_39_[0] , 
+        chany_top_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+    .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_20 (
+    .in ( { chany_bottom_out[17] , right_bottom_grid_pin_40_[0] , 
+        chany_top_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_22 (
+    .in ( { chany_bottom_out[18] , chanx_right_out[19] , chany_top_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_33 (
+    .in ( { chany_bottom_out[11] , chanx_right_in[6] , chanx_right_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem mem_bottom_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 (
+    .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 (
+    .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+    .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 (
+    .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+    .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 (
+    .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+    .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 (
+    .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
+    .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 (
+    .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+    .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( right_bottom_grid_pin_41_[0] ) , 
+    .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , 
+    .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , 
+    .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , 
+    .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , 
+    .HI ( optlc_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v
new file mode 100644
index 0000000..aa363c2
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v
@@ -0,0 +1,2107 @@
+//
+//
+//
+//
+//
+//
+module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_97 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_107 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_93 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_91 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_100 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+wire copt_net_125 ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_125 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_125 ) , 
+    .X ( copt_net_120 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_120 ) , 
+    .X ( copt_net_121 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_121 ) , 
+    .X ( copt_net_122 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_122 ) , 
+    .X ( copt_net_123 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_123 ) , 
+    .X ( copt_net_124 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_124 ) , 
+    .X ( mem_out[1] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_89 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_85 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_83 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_81 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .Y ( BUF_net_78 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .Y ( BUF_net_76 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .Y ( BUF_net_74 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .Y ( BUF_net_72 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_69 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_67 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_65 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_129 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_115 ) , 
+    .X ( copt_net_114 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_115 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_114 ) , 
+    .X ( copt_net_116 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_119 ) , 
+    .X ( copt_net_117 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_116 ) , 
+    .X ( copt_net_118 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_118 ) , 
+    .X ( copt_net_119 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1289 ( .A ( copt_net_117 ) , 
+    .X ( ropt_net_127 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1290 ( .A ( ropt_net_127 ) , 
+    .X ( ropt_net_128 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1291 ( .A ( ropt_net_128 ) , 
+    .X ( ropt_net_129 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_62 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_104 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1_ ( chany_top_in , top_left_grid_pin_1_ , chanx_right_in , 
+    right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , 
+    right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , 
+    right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , 
+    right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , 
+    bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , 
+    chany_bottom_out , ccff_tail , prog_clk_0_E_in ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_1_ ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_bottom_grid_pin_34_ ;
+input  [0:0] right_bottom_grid_pin_35_ ;
+input  [0:0] right_bottom_grid_pin_36_ ;
+input  [0:0] right_bottom_grid_pin_37_ ;
+input  [0:0] right_bottom_grid_pin_38_ ;
+input  [0:0] right_bottom_grid_pin_39_ ;
+input  [0:0] right_bottom_grid_pin_40_ ;
+input  [0:0] right_bottom_grid_pin_41_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_left_grid_pin_1_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:0] ccff_tail ;
+input  prog_clk_0_E_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:2] mux_tree_tapbuf_size4_4_sram ;
+wire [0:2] mux_tree_tapbuf_size4_5_sram ;
+wire [0:2] mux_tree_tapbuf_size4_6_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:2] mux_tree_tapbuf_size5_4_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:2] mux_tree_tapbuf_size6_4_sram ;
+wire [0:2] mux_tree_tapbuf_size6_5_sram ;
+wire [0:2] mux_tree_tapbuf_size6_6_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , 
+        chanx_right_in[15] , chany_top_out[3] , chany_top_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_4 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , 
+        chanx_right_in[17] , chany_top_out[6] , chany_top_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , 
+        SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_8 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , 
+        chanx_right_in[18] , chany_top_out[7] , chany_top_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , 
+        SYNOPSYS_UNCONNECTED_9 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 (
+    .in ( { chany_bottom_out[3] , right_bottom_grid_pin_34_[0] , 
+        right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , 
+        right_bottom_grid_pin_40_[0] , chany_top_out[3] } ) ,
+    .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , 
+        SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_4 mux_bottom_track_1 (
+    .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_right_in[5] , 
+        chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_5 mux_bottom_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_right_in[3] , 
+        chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , 
+        SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_9 (
+    .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[2] , 
+        chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , 
+        SYNOPSYS_UNCONNECTED_21 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 (
+    .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , 
+        chany_top_out[5] , chany_top_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , 
+        SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chany_top_out[1] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_16 (
+    .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , 
+        chany_top_out[9] , chany_top_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 } ) ,
+    .out ( chany_top_out[8] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_right_in[4] , 
+        chanx_right_in[11] , chanx_right_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , 
+        SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_3 mux_bottom_track_17 (
+    .in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] , 
+        chanx_right_in[8] , chanx_right_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , 
+        SYNOPSYS_UNCONNECTED_33 } ) ,
+    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_25 (
+    .in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] , 
+        chanx_right_in[7] , chanx_right_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size5_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , 
+        SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_24 (
+    .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_top_out[10] , 
+        chany_top_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_32 (
+    .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , 
+        chany_top_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , 
+        SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chany_top_out[16] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_8 (
+    .in ( { chany_top_in[7] , chany_bottom_out[9] , 
+        right_bottom_grid_pin_34_[0] , chany_top_out[9] } ) ,
+    .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , 
+        SYNOPSYS_UNCONNECTED_45 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_10 (
+    .in ( { chany_bottom_out[10] , chany_top_in[11] , 
+        right_bottom_grid_pin_35_[0] , chany_top_out[10] } ) ,
+    .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , 
+        SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chanx_right_out[5] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_12 (
+    .in ( { chany_bottom_out[11] , chany_top_in[15] , 
+        right_bottom_grid_pin_36_[0] , chany_top_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size4_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 } ) ,
+    .out ( chanx_right_out[6] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_14 (
+    .in ( { chany_bottom_out[13] , chany_top_in[19] , 
+        right_bottom_grid_pin_37_[0] , chany_top_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size4_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , 
+        SYNOPSYS_UNCONNECTED_54 } ) ,
+    .out ( chanx_right_out[7] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4 mux_right_track_24 (
+    .in ( { chany_bottom_out[19] , right_bottom_grid_pin_34_[0] , 
+        chany_top_out[19] , chany_bottom_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size4_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , 
+        SYNOPSYS_UNCONNECTED_57 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_top_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_right_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 (
+    .in ( { chany_top_in[0] , chany_bottom_out[5] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_39_[0] , chanx_right_out[19] , 
+        chany_top_out[5] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , 
+        SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 (
+    .in ( { chany_top_in[1] , chany_bottom_out[6] , 
+        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_top_out[6] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 (
+    .in ( { chany_top_in[3] , chany_bottom_out[7] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_39_[0] , chanx_right_out[19] , 
+        chany_top_out[7] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , 
+        SYNOPSYS_UNCONNECTED_66 } ) ,
+    .out ( chanx_right_out[3] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_0 mux_right_track_16 (
+    .in ( { chany_bottom_out[14] , right_bottom_grid_pin_38_[0] , 
+        chany_top_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_18 (
+    .in ( { chany_bottom_out[15] , right_bottom_grid_pin_39_[0] , 
+        chany_top_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+    .out ( chanx_right_out[9] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_20 (
+    .in ( { chany_bottom_out[17] , right_bottom_grid_pin_40_[0] , 
+        chany_top_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chanx_right_out[10] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_22 (
+    .in ( { chany_bottom_out[18] , chanx_right_out[19] , chany_top_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chanx_right_out[11] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_33 (
+    .in ( { chany_bottom_out[11] , chanx_right_in[6] , chanx_right_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem mem_bottom_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 (
+    .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chanx_right_out[13] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 (
+    .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+    .out ( chanx_right_out[14] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 (
+    .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+    .out ( chanx_right_out[15] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 (
+    .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 (
+    .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
+    .out ( chanx_right_out[17] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 (
+    .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+    .out ( chanx_right_out[18] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( right_bottom_grid_pin_41_[0] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , 
+    .HI ( optlc_net_110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , 
+    .HI ( optlc_net_111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , 
+    .HI ( optlc_net_112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , 
+    .HI ( optlc_net_113 ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.top_only.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..f894582
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.top_only.pt.v
@@ -0,0 +1,552 @@
+//
+//
+//
+//
+//
+//
+module sb_0__1_ ( chany_top_in , top_left_grid_pin_1_ , chanx_right_in , 
+    right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , 
+    right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , 
+    right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , 
+    right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , 
+    bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , 
+    chany_bottom_out , ccff_tail , prog_clk_0_E_in ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_1_ ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_bottom_grid_pin_34_ ;
+input  [0:0] right_bottom_grid_pin_35_ ;
+input  [0:0] right_bottom_grid_pin_36_ ;
+input  [0:0] right_bottom_grid_pin_37_ ;
+input  [0:0] right_bottom_grid_pin_38_ ;
+input  [0:0] right_bottom_grid_pin_39_ ;
+input  [0:0] right_bottom_grid_pin_40_ ;
+input  [0:0] right_bottom_grid_pin_41_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_left_grid_pin_1_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:0] ccff_tail ;
+input  prog_clk_0_E_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:2] mux_tree_tapbuf_size4_4_sram ;
+wire [0:2] mux_tree_tapbuf_size4_5_sram ;
+wire [0:2] mux_tree_tapbuf_size4_6_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:2] mux_tree_tapbuf_size5_4_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:2] mux_tree_tapbuf_size6_4_sram ;
+wire [0:2] mux_tree_tapbuf_size6_5_sram ;
+wire [0:2] mux_tree_tapbuf_size6_6_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , 
+        chanx_right_in[15] , chany_top_out[3] , chany_top_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_4 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , 
+        chanx_right_in[17] , chany_top_out[6] , chany_top_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , 
+        SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_8 (
+    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , 
+        chanx_right_in[18] , chany_top_out[7] , chany_top_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , 
+        SYNOPSYS_UNCONNECTED_9 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 (
+    .in ( { chany_bottom_out[3] , right_bottom_grid_pin_34_[0] , 
+        right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , 
+        right_bottom_grid_pin_40_[0] , chany_top_out[3] } ) ,
+    .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , 
+        SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_4 mux_bottom_track_1 (
+    .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_right_in[5] , 
+        chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_5 mux_bottom_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_right_in[3] , 
+        chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , 
+        SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_9 (
+    .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[2] , 
+        chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , 
+        SYNOPSYS_UNCONNECTED_21 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 (
+    .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , 
+        chany_top_out[5] , chany_top_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , 
+        SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chany_top_out[1] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_16 (
+    .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , 
+        chany_top_out[9] , chany_top_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 } ) ,
+    .out ( chany_top_out[8] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_right_in[4] , 
+        chanx_right_in[11] , chanx_right_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , 
+        SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_3 mux_bottom_track_17 (
+    .in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] , 
+        chanx_right_in[8] , chanx_right_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , 
+        SYNOPSYS_UNCONNECTED_33 } ) ,
+    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_25 (
+    .in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] , 
+        chanx_right_in[7] , chanx_right_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size5_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , 
+        SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_24 (
+    .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_top_out[10] , 
+        chany_top_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_32 (
+    .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , 
+        chany_top_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , 
+        SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chany_top_out[16] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_8 (
+    .in ( { chany_top_in[7] , chany_bottom_out[9] , 
+        right_bottom_grid_pin_34_[0] , chany_top_out[9] } ) ,
+    .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , 
+        SYNOPSYS_UNCONNECTED_45 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_10 (
+    .in ( { chany_bottom_out[10] , chany_top_in[11] , 
+        right_bottom_grid_pin_35_[0] , chany_top_out[10] } ) ,
+    .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , 
+        SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chanx_right_out[5] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_12 (
+    .in ( { chany_bottom_out[11] , chany_top_in[15] , 
+        right_bottom_grid_pin_36_[0] , chany_top_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size4_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 } ) ,
+    .out ( chanx_right_out[6] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_14 (
+    .in ( { chany_bottom_out[13] , chany_top_in[19] , 
+        right_bottom_grid_pin_37_[0] , chany_top_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size4_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , 
+        SYNOPSYS_UNCONNECTED_54 } ) ,
+    .out ( chanx_right_out[7] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4 mux_right_track_24 (
+    .in ( { chany_bottom_out[19] , right_bottom_grid_pin_34_[0] , 
+        chany_top_out[19] , chany_bottom_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size4_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , 
+        SYNOPSYS_UNCONNECTED_57 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_top_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_right_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 (
+    .in ( { chany_top_in[0] , chany_bottom_out[5] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_39_[0] , chanx_right_out[19] , 
+        chany_top_out[5] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , 
+        SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 (
+    .in ( { chany_top_in[1] , chany_bottom_out[6] , 
+        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_top_out[6] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_112 ) ) ;
+sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 (
+    .in ( { chany_top_in[3] , chany_bottom_out[7] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_39_[0] , chanx_right_out[19] , 
+        chany_top_out[7] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , 
+        SYNOPSYS_UNCONNECTED_66 } ) ,
+    .out ( chanx_right_out[3] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_0 mux_right_track_16 (
+    .in ( { chany_bottom_out[14] , right_bottom_grid_pin_38_[0] , 
+        chany_top_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_18 (
+    .in ( { chany_bottom_out[15] , right_bottom_grid_pin_39_[0] , 
+        chany_top_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+    .out ( chanx_right_out[9] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_20 (
+    .in ( { chany_bottom_out[17] , right_bottom_grid_pin_40_[0] , 
+        chany_top_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chanx_right_out[10] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_22 (
+    .in ( { chany_bottom_out[18] , chanx_right_out[19] , chany_top_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chanx_right_out[11] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_33 (
+    .in ( { chany_bottom_out[11] , chanx_right_in[6] , chanx_right_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem mem_bottom_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 (
+    .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chanx_right_out[13] ) , .p0 ( optlc_net_110 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 (
+    .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+    .out ( chanx_right_out[14] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 (
+    .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+    .out ( chanx_right_out[15] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 (
+    .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 (
+    .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
+    .out ( chanx_right_out[17] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 (
+    .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+    .out ( chanx_right_out[18] ) , .p0 ( optlc_net_111 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( right_bottom_grid_pin_41_[0] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , 
+    .HI ( optlc_net_110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , 
+    .HI ( optlc_net_111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , 
+    .HI ( optlc_net_112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , 
+    .HI ( optlc_net_113 ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v
new file mode 100644
index 0000000..bab76b8
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v
@@ -0,0 +1,1598 @@
+//
+//
+//
+//
+//
+//
+module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+wire copt_net_79 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_79 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1238 ( .A ( copt_net_79 ) , 
+    .X ( copt_net_75 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1239 ( .A ( copt_net_75 ) , 
+    .X ( copt_net_76 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1240 ( .A ( copt_net_76 ) , 
+    .X ( copt_net_77 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1241 ( .A ( copt_net_77 ) , 
+    .X ( copt_net_78 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1242 ( .A ( copt_net_78 ) , 
+    .X ( mem_out[1] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1_22 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1_22 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1_21 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1_21 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1_20 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1_20 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1_19 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1_19 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1_18 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1_18 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1_17 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1_17 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1_16 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1_16 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_58 ) ) ;
+endmodule
+
+
+module sb_0__2__const1_15 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1_15 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_56 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_63 ( .A ( BUF_net_56 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1_14 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1_14 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1_13 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1_13 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1_12 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1_12 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1_11 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1_11 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_53 ) ) ;
+endmodule
+
+
+module sb_0__2__const1_10 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1_10 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1_9 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1_9 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1_8 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1_8 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_51 ) ) ;
+endmodule
+
+
+module sb_0__2__const1_7 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1_7 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1_6 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_0__2__const1_6 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1_5 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_0__2__const1_5 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_48 ) ) ;
+endmodule
+
+
+module sb_0__2__const1_4 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_0__2__const1_4 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_46 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1_3 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_0__2__const1_3 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_43 ( .A ( BUF_net_44 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_44 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_44 ) ) ;
+endmodule
+
+
+module sb_0__2__const1_2 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_0__2__const1_2 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_131 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_69 ) , 
+    .X ( copt_net_68 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_71 ) , 
+    .X ( copt_net_69 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_73 ) , 
+    .X ( copt_net_70 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1234 ( .A ( copt_net_70 ) , 
+    .X ( copt_net_71 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_72 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_72 ) , 
+    .X ( copt_net_73 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1292 ( .A ( ropt_net_132 ) , 
+    .X ( ropt_net_131 ) ) ;
+sky130_fd_sc_hd__buf_4 ropt_h_inst_1293 ( .A ( copt_net_68 ) , 
+    .X ( ropt_net_132 ) ) ;
+endmodule
+
+
+module sb_0__2__const1_1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_0__2__const1_1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_41 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__const1_0 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_0__2__const1_0 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2_ ( chanx_right_in , right_top_grid_pin_1_ , 
+    right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , 
+    right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , 
+    right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , 
+    right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , 
+    bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , 
+    ccff_tail , SC_IN_TOP , SC_OUT_BOT , prog_clk_0_E_in ) ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_top_grid_pin_1_ ;
+input  [0:0] right_bottom_grid_pin_34_ ;
+input  [0:0] right_bottom_grid_pin_35_ ;
+input  [0:0] right_bottom_grid_pin_36_ ;
+input  [0:0] right_bottom_grid_pin_37_ ;
+input  [0:0] right_bottom_grid_pin_38_ ;
+input  [0:0] right_bottom_grid_pin_39_ ;
+input  [0:0] right_bottom_grid_pin_40_ ;
+input  [0:0] right_bottom_grid_pin_41_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_left_grid_pin_1_ ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:0] ccff_tail ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  prog_clk_0_E_in ;
+
+wire ropt_net_95 ;
+wire ropt_net_96 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , 
+        SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 (
+    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[17] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , 
+        SYNOPSYS_UNCONNECTED_9 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 (
+    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , 
+        SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_right_out[3] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_8 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_bottom_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size3 mux_right_track_24 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_bottom_in[6] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_10 (
+    .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chanx_right_out[5] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_12 (
+    .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chanx_right_out[6] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_14 (
+    .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
+    .out ( chanx_right_out[7] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_16 (
+    .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_18 (
+    .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+    .out ( chanx_right_out[9] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_20 (
+    .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_right_out[10] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_22 (
+    .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chanx_right_out[11] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 (
+    .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) ,
+    .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_right_out[13] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_28 (
+    .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) ,
+    .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chanx_right_out[14] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_30 (
+    .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) ,
+    .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chanx_right_out[15] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_32 (
+    .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) ,
+    .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_34 (
+    .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chanx_right_out[17] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_36 (
+    .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chanx_right_out[18] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_38 (
+    .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( chanx_right_out[19] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_14 mux_bottom_track_1 (
+    .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_15 mux_bottom_track_5 (
+    .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_16 mux_bottom_track_9 (
+    .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_25 (
+    .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_28 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_30 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_34 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_36 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_38 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_right_in[0] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_right_in[1] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_right_in[2] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[3] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[4] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[5] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[7] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[8] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chanx_right_in[10] ) , 
+    .X ( ropt_net_95 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_right_in[11] ) , 
+    .X ( ropt_net_96 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[12] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[13] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[15] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[17] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , 
+    .HI ( optlc_net_65 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , 
+    .HI ( optlc_net_66 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , 
+    .HI ( optlc_net_67 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1257 ( .A ( ropt_net_95 ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_96 ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v
new file mode 100644
index 0000000..556fc2e
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v
@@ -0,0 +1,1678 @@
+//
+//
+//
+//
+//
+//
+module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+wire copt_net_79 ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_79 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1238 ( .A ( copt_net_79 ) , 
+    .X ( copt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1239 ( .A ( copt_net_75 ) , 
+    .X ( copt_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1240 ( .A ( copt_net_76 ) , 
+    .X ( copt_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1241 ( .A ( copt_net_77 ) , 
+    .X ( copt_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1242 ( .A ( copt_net_78 ) , 
+    .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_63 ( .A ( BUF_net_56 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_43 ( .A ( BUF_net_44 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_44 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_44 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_131 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_69 ) , 
+    .X ( copt_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_71 ) , 
+    .X ( copt_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_73 ) , 
+    .X ( copt_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1234 ( .A ( copt_net_70 ) , 
+    .X ( copt_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_72 ) , 
+    .X ( copt_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1292 ( .A ( ropt_net_132 ) , 
+    .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_4 ropt_h_inst_1293 ( .A ( copt_net_68 ) , 
+    .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_41 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_0__2_ ( chanx_right_in , right_top_grid_pin_1_ , 
+    right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , 
+    right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , 
+    right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , 
+    right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , 
+    bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , 
+    ccff_tail , SC_IN_TOP , SC_OUT_BOT , prog_clk_0_E_in , VDD , VSS ) ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_top_grid_pin_1_ ;
+input  [0:0] right_bottom_grid_pin_34_ ;
+input  [0:0] right_bottom_grid_pin_35_ ;
+input  [0:0] right_bottom_grid_pin_36_ ;
+input  [0:0] right_bottom_grid_pin_37_ ;
+input  [0:0] right_bottom_grid_pin_38_ ;
+input  [0:0] right_bottom_grid_pin_39_ ;
+input  [0:0] right_bottom_grid_pin_40_ ;
+input  [0:0] right_bottom_grid_pin_41_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_left_grid_pin_1_ ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:0] ccff_tail ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  prog_clk_0_E_in ;
+input  VDD ;
+input  VSS ;
+
+wire ropt_net_95 ;
+wire ropt_net_96 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 } ) ,
+    .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , 
+        SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 (
+    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[17] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , 
+        SYNOPSYS_UNCONNECTED_9 } ) ,
+    .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 (
+    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , 
+        SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_8 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_bottom_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) ,
+    .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size3 mux_right_track_24 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_bottom_in[6] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_10 (
+    .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_12 (
+    .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_14 (
+    .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
+    .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_16 (
+    .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_18 (
+    .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+    .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_20 (
+    .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_22 (
+    .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 (
+    .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) ,
+    .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_28 (
+    .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) ,
+    .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_30 (
+    .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) ,
+    .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_32 (
+    .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) ,
+    .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+    .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_34 (
+    .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_36 (
+    .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_38 (
+    .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_14 mux_bottom_track_1 (
+    .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+    .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_15 mux_bottom_track_5 (
+    .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_16 mux_bottom_track_9 (
+    .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_25 (
+    .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_28 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_30 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_34 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_36 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_38 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_right_in[0] ) , 
+    .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_right_in[1] ) , 
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_right_in[2] ) , 
+    .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[3] ) , 
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[4] ) , 
+    .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[5] ) , 
+    .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[7] ) , 
+    .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[8] ) , 
+    .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[9] ) , 
+    .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chanx_right_in[10] ) , 
+    .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_right_in[11] ) , 
+    .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[12] ) , 
+    .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[13] ) , 
+    .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[15] ) , 
+    .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[17] ) , 
+    .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[19] ) , 
+    .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , 
+    .HI ( optlc_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , 
+    .HI ( optlc_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , 
+    .HI ( optlc_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1257 ( .A ( ropt_net_95 ) , 
+    .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_96 ) , 
+    .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v
new file mode 100644
index 0000000..c987235
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v
@@ -0,0 +1,1334 @@
+//
+//
+//
+//
+//
+//
+module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+wire copt_net_79 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_79 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1238 ( .A ( copt_net_79 ) , 
+    .X ( copt_net_75 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1239 ( .A ( copt_net_75 ) , 
+    .X ( copt_net_76 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1240 ( .A ( copt_net_76 ) , 
+    .X ( copt_net_77 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1241 ( .A ( copt_net_77 ) , 
+    .X ( copt_net_78 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1242 ( .A ( copt_net_78 ) , 
+    .X ( mem_out[1] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_58 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_56 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_63 ( .A ( BUF_net_56 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_53 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_51 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_48 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_46 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_43 ( .A ( BUF_net_44 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_44 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_44 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_131 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_69 ) , 
+    .X ( copt_net_68 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_71 ) , 
+    .X ( copt_net_69 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_73 ) , 
+    .X ( copt_net_70 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1234 ( .A ( copt_net_70 ) , 
+    .X ( copt_net_71 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_72 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_72 ) , 
+    .X ( copt_net_73 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1292 ( .A ( ropt_net_132 ) , 
+    .X ( ropt_net_131 ) ) ;
+sky130_fd_sc_hd__buf_4 ropt_h_inst_1293 ( .A ( copt_net_68 ) , 
+    .X ( ropt_net_132 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_41 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2_ ( chanx_right_in , right_top_grid_pin_1_ , 
+    right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , 
+    right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , 
+    right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , 
+    right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , 
+    bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , 
+    ccff_tail , SC_IN_TOP , SC_OUT_BOT , prog_clk_0_E_in ) ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_top_grid_pin_1_ ;
+input  [0:0] right_bottom_grid_pin_34_ ;
+input  [0:0] right_bottom_grid_pin_35_ ;
+input  [0:0] right_bottom_grid_pin_36_ ;
+input  [0:0] right_bottom_grid_pin_37_ ;
+input  [0:0] right_bottom_grid_pin_38_ ;
+input  [0:0] right_bottom_grid_pin_39_ ;
+input  [0:0] right_bottom_grid_pin_40_ ;
+input  [0:0] right_bottom_grid_pin_41_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_left_grid_pin_1_ ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:0] ccff_tail ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  prog_clk_0_E_in ;
+
+wire ropt_net_95 ;
+wire ropt_net_96 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , 
+        SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 (
+    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[17] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , 
+        SYNOPSYS_UNCONNECTED_9 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 (
+    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , 
+        SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_right_out[3] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_8 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_bottom_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size3 mux_right_track_24 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_bottom_in[6] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_10 (
+    .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chanx_right_out[5] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_12 (
+    .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chanx_right_out[6] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_14 (
+    .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
+    .out ( chanx_right_out[7] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_16 (
+    .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_18 (
+    .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+    .out ( chanx_right_out[9] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_20 (
+    .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_right_out[10] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_22 (
+    .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chanx_right_out[11] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 (
+    .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) ,
+    .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_right_out[13] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_28 (
+    .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) ,
+    .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chanx_right_out[14] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_30 (
+    .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) ,
+    .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chanx_right_out[15] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_32 (
+    .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) ,
+    .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_34 (
+    .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chanx_right_out[17] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_36 (
+    .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chanx_right_out[18] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_38 (
+    .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( chanx_right_out[19] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_14 mux_bottom_track_1 (
+    .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_15 mux_bottom_track_5 (
+    .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_16 mux_bottom_track_9 (
+    .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_25 (
+    .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_28 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_30 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_34 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_36 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_38 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_right_in[0] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_right_in[1] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_right_in[2] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[3] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[4] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[5] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[7] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[8] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chanx_right_in[10] ) , 
+    .X ( ropt_net_95 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_right_in[11] ) , 
+    .X ( ropt_net_96 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[12] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[13] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[15] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[17] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , 
+    .HI ( optlc_net_65 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , 
+    .HI ( optlc_net_66 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , 
+    .HI ( optlc_net_67 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1257 ( .A ( ropt_net_95 ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_96 ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.top_only.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..4713a1f
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.top_only.pt.v
@@ -0,0 +1,387 @@
+//
+//
+//
+//
+//
+//
+module sb_0__2_ ( chanx_right_in , right_top_grid_pin_1_ , 
+    right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , 
+    right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , 
+    right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , 
+    right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , 
+    bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , 
+    ccff_tail , SC_IN_TOP , SC_OUT_BOT , prog_clk_0_E_in ) ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_top_grid_pin_1_ ;
+input  [0:0] right_bottom_grid_pin_34_ ;
+input  [0:0] right_bottom_grid_pin_35_ ;
+input  [0:0] right_bottom_grid_pin_36_ ;
+input  [0:0] right_bottom_grid_pin_37_ ;
+input  [0:0] right_bottom_grid_pin_38_ ;
+input  [0:0] right_bottom_grid_pin_39_ ;
+input  [0:0] right_bottom_grid_pin_40_ ;
+input  [0:0] right_bottom_grid_pin_41_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_left_grid_pin_1_ ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:0] ccff_tail ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  prog_clk_0_E_in ;
+
+wire ropt_net_95 ;
+wire ropt_net_96 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , 
+        SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 (
+    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[17] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , 
+        SYNOPSYS_UNCONNECTED_9 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 (
+    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , 
+        SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_right_out[3] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_8 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_bottom_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size3 mux_right_track_24 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_bottom_in[6] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_10 (
+    .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chanx_right_out[5] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_12 (
+    .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chanx_right_out[6] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_14 (
+    .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
+    .out ( chanx_right_out[7] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_16 (
+    .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_18 (
+    .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+    .out ( chanx_right_out[9] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_20 (
+    .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_right_out[10] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_22 (
+    .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chanx_right_out[11] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 (
+    .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) ,
+    .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_right_out[13] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_28 (
+    .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) ,
+    .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chanx_right_out[14] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_30 (
+    .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) ,
+    .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chanx_right_out[15] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_32 (
+    .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) ,
+    .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_34 (
+    .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chanx_right_out[17] ) , .p0 ( optlc_net_67 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_36 (
+    .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chanx_right_out[18] ) , .p0 ( optlc_net_65 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_38 (
+    .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( chanx_right_out[19] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_14 mux_bottom_track_1 (
+    .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_15 mux_bottom_track_5 (
+    .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_16 mux_bottom_track_9 (
+    .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_25 (
+    .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_66 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_28 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_30 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_34 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_36 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_38 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_right_in[0] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_right_in[1] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_right_in[2] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[3] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[4] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[5] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[7] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[8] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chanx_right_in[10] ) , 
+    .X ( ropt_net_95 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_right_in[11] ) , 
+    .X ( ropt_net_96 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[12] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[13] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[15] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[17] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , 
+    .HI ( optlc_net_65 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , 
+    .HI ( optlc_net_66 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , 
+    .HI ( optlc_net_67 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1257 ( .A ( ropt_net_95 ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_96 ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v
new file mode 100644
index 0000000..cb328a5
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v
@@ -0,0 +1,2453 @@
+//
+//
+//
+//
+//
+//
+module sb_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__0__const1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+wire copt_net_107 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_107 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_106 ) , 
+    .X ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_107 ) , 
+    .X ( copt_net_106 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1288 ( .A ( copt_net_105 ) , 
+    .X ( mem_out[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_26 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_1__0__const1_26 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_25 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_1__0__const1_25 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_84 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_24 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__0__const1_24 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_23 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__0__const1_23 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , 
+    .Y ( BUF_net_82 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_22 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sb_1__0__const1_22 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_21 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sb_1__0__const1_21 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_20 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_1__0__const1_20 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_19 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_1__0__const1_19 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_92 ) ) ;
+endmodule
+
+
+module sb_1__0__const1_18 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_1__0__const1_18 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_78 ) ) ;
+endmodule
+
+
+module sb_1__0__const1_17 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_1__0__const1_17 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_76 ) ) ;
+endmodule
+
+
+module sb_1__0__const1_16 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_1__0__const1_16 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_74 ) ) ;
+endmodule
+
+
+module sb_1__0__const1_15 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_1__0__const1_15 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_72 ) ) ;
+endmodule
+
+
+module sb_1__0__const1_14 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_1__0__const1_14 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_70 ) ) ;
+endmodule
+
+
+module sb_1__0__const1_13 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_1__0__const1_13 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_12 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sb_1__0__const1_12 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_11 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sb_1__0__const1_11 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_10 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__0__const1_10 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_9 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__0__const1_9 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_8 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__0__const1_8 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_66 ) ) ;
+endmodule
+
+
+module sb_1__0__const1_7 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__0__const1_7 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_6 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__0__const1_6 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_5 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__0__const1_5 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_4 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__0__const1_4 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_133 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_98 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , 
+    .X ( copt_net_99 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_99 ) , 
+    .X ( copt_net_100 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_100 ) , 
+    .X ( copt_net_101 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_101 ) , 
+    .X ( copt_net_102 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_102 ) , 
+    .X ( copt_net_103 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1308 ( .A ( ropt_net_134 ) , 
+    .X ( ropt_net_132 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( ropt_net_132 ) , 
+    .X ( ropt_net_133 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( copt_net_103 ) , 
+    .X ( ropt_net_134 ) ) ;
+endmodule
+
+
+module sb_1__0__const1_3 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sb_1__0__const1_3 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_2 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sb_1__0__const1_2 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__const1_1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sb_1__0__const1_1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .Y ( BUF_net_64 ) ) ;
+endmodule
+
+
+module sb_1__0__const1_0 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sb_1__0__const1_0 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .Y ( BUF_net_62 ) ) ;
+endmodule
+
+
+module sb_1__0_ ( chany_top_in , top_left_grid_pin_42_ , 
+    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
+    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
+    top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ , 
+    right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , 
+    right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , 
+    right_bottom_grid_pin_11_ , right_bottom_grid_pin_13_ , 
+    right_bottom_grid_pin_15_ , right_bottom_grid_pin_17_ , chanx_left_in , 
+    left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , 
+    left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , 
+    left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , 
+    left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , 
+    left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , 
+    chanx_left_out , ccff_tail , SC_IN_TOP , SC_OUT_TOP , Test_en_S_in , 
+    Test_en_N_out , prog_clk_0_N_in , prog_clk_3_S_in , prog_clk_3_N_out , 
+    clk_3_S_in , clk_3_N_out ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_42_ ;
+input  [0:0] top_left_grid_pin_43_ ;
+input  [0:0] top_left_grid_pin_44_ ;
+input  [0:0] top_left_grid_pin_45_ ;
+input  [0:0] top_left_grid_pin_46_ ;
+input  [0:0] top_left_grid_pin_47_ ;
+input  [0:0] top_left_grid_pin_48_ ;
+input  [0:0] top_left_grid_pin_49_ ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_bottom_grid_pin_1_ ;
+input  [0:0] right_bottom_grid_pin_3_ ;
+input  [0:0] right_bottom_grid_pin_5_ ;
+input  [0:0] right_bottom_grid_pin_7_ ;
+input  [0:0] right_bottom_grid_pin_9_ ;
+input  [0:0] right_bottom_grid_pin_11_ ;
+input  [0:0] right_bottom_grid_pin_13_ ;
+input  [0:0] right_bottom_grid_pin_15_ ;
+input  [0:0] right_bottom_grid_pin_17_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_bottom_grid_pin_1_ ;
+input  [0:0] left_bottom_grid_pin_3_ ;
+input  [0:0] left_bottom_grid_pin_5_ ;
+input  [0:0] left_bottom_grid_pin_7_ ;
+input  [0:0] left_bottom_grid_pin_9_ ;
+input  [0:0] left_bottom_grid_pin_11_ ;
+input  [0:0] left_bottom_grid_pin_13_ ;
+input  [0:0] left_bottom_grid_pin_15_ ;
+input  [0:0] left_bottom_grid_pin_17_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  SC_IN_TOP ;
+output SC_OUT_TOP ;
+input  Test_en_S_in ;
+output Test_en_N_out ;
+input  prog_clk_0_N_in ;
+input  prog_clk_3_S_in ;
+output prog_clk_3_N_out ;
+input  clk_3_S_in ;
+output clk_3_N_out ;
+
+wire ropt_net_118 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size14_0_sram ;
+wire [0:3] mux_tree_tapbuf_size14_1_sram ;
+wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:1] mux_tree_tapbuf_size3_5_sram ;
+wire [0:1] mux_tree_tapbuf_size3_6_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:3] mux_tree_tapbuf_size9_1_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_1__0__mux_tree_tapbuf_size8_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        chanx_right_in[1] , chanx_left_out[3] , chanx_left_in[0] , 
+        chanx_right_out[3] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 (
+    .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , 
+        right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , 
+        right_bottom_grid_pin_17_[0] , chanx_right_out[7] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 (
+    .in ( { chany_top_in[6] , chany_top_in[13] , chanx_left_out[5] , 
+        chanx_left_out[14] , left_bottom_grid_pin_3_[0] , 
+        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , 
+        left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 (
+    .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , 
+        chanx_left_out[7] , chanx_left_out[17] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem_2 mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_2 (
+    .in ( { chany_top_out[13] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_right_in[3] , chanx_left_out[5] , chanx_right_out[5] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 } ) ,
+    .out ( chany_top_out[1] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        chanx_left_out[6] , chanx_right_in[7] , chanx_right_out[6] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , 
+        SYNOPSYS_UNCONNECTED_22 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 (
+    .in ( { chany_top_out[13] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_left_out[7] , chanx_right_in[11] , chanx_right_out[7] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , 
+        SYNOPSYS_UNCONNECTED_25 } ) ,
+    .out ( chany_top_out[3] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 (
+    .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , 
+        right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , 
+        chanx_right_out[9] , chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , 
+        SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_24 (
+    .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_13_[0] , 
+        chanx_right_out[10] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_17 (
+    .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , 
+        chanx_left_out[9] , chanx_left_out[18] , left_bottom_grid_pin_3_[0] , 
+        left_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , 
+        SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 (
+    .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , 
+        chanx_left_out[10] , chanx_left_out[19] , left_bottom_grid_pin_5_[0] , 
+        left_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , 
+        SYNOPSYS_UNCONNECTED_37 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_top_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_8 (
+    .in ( { top_left_grid_pin_42_[0] , chanx_left_out[9] , 
+        chanx_right_in[15] , chanx_right_out[9] } ) ,
+    .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , 
+        SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size4 mux_top_track_10 (
+    .in ( { chany_top_out[13] , chanx_left_out[10] , chanx_right_in[19] , 
+        chanx_right_out[10] } ) ,
+    .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 } ) ,
+    .out ( chany_top_out[5] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_10 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 (
+    .in ( { top_left_grid_pin_44_[0] , chanx_left_out[11] , 
+        chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) ,
+    .out ( chany_top_out[6] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 (
+    .in ( { top_left_grid_pin_45_[0] , chanx_left_out[13] , 
+        chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) ,
+    .out ( chany_top_out[7] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 (
+    .in ( { top_left_grid_pin_46_[0] , chanx_left_out[14] , 
+        chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) ,
+    .out ( chany_top_out[8] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 (
+    .in ( { top_left_grid_pin_47_[0] , chanx_left_out[15] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) ,
+    .out ( chany_top_out[9] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 (
+    .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) ,
+    .out ( chany_top_out[10] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 (
+    .in ( { top_left_grid_pin_49_[0] , chanx_left_out[18] , 
+        chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size3_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) ,
+    .out ( chany_top_out[11] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 (
+    .in ( { top_left_grid_pin_42_[0] , chanx_left_out[19] , 
+        chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size3_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 (
+    .in ( { chanx_right_in[0] , chanx_left_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) ,
+    .out ( chany_top_out[19] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_0 (
+    .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , 
+        right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] , 
+        chanx_right_out[3] , chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , 
+        SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size9 mux_right_track_2 (
+    .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , 
+        right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , 
+        right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_15_[0] , 
+        chanx_right_out[5] , chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size9_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , 
+        SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_mem mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size14_0 mux_right_track_4 (
+    .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , 
+        right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , 
+        right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , 
+        right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_15_[0] , 
+        right_bottom_grid_pin_17_[0] , chanx_right_out[6] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size14_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , 
+        SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size14 mux_left_track_5 (
+    .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , 
+        chanx_left_out[6] , chanx_left_out[15] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , 
+        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , 
+        left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_13_[0] , 
+        left_bottom_grid_pin_15_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size14_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , 
+        SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size14_mem mem_left_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_0 mux_right_track_32 (
+    .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , 
+        right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_15_[0] , 
+        chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , 
+        SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 (
+    .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , 
+        chanx_left_out[11] , left_bottom_grid_pin_7_[0] , 
+        left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , 
+        SYNOPSYS_UNCONNECTED_81 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_mem mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size10 mux_left_track_1 (
+    .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , 
+        chanx_left_out[3] , chanx_left_out[13] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , 
+        left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , 
+        SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size10_mem mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , 
+    .HI ( optlc_net_93 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , 
+    .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , 
+    .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( top_left_grid_pin_43_[0] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[3] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[7] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_left_in[11] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_left_in[15] ) , 
+    .X ( ropt_net_118 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( chanx_left_in[19] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( Test_en_S_in ) , .Y ( BUF_net_86 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , 
+    .Y ( prog_clk_3_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_88 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( clk_3_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_90 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , 
+    .HI ( optlc_net_94 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , 
+    .HI ( optlc_net_95 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , 
+    .HI ( optlc_net_96 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , 
+    .HI ( optlc_net_97 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_118 ) , 
+    .X ( chany_top_out[15] ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v
new file mode 100644
index 0000000..34c4da4
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v
@@ -0,0 +1,2612 @@
+//
+//
+//
+//
+//
+//
+module sb_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+wire copt_net_107 ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_107 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_106 ) , 
+    .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_107 ) , 
+    .X ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1288 ( .A ( copt_net_105 ) , 
+    .X ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , 
+    .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_133 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , 
+    .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_99 ) , 
+    .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_100 ) , 
+    .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_101 ) , 
+    .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_102 ) , 
+    .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1308 ( .A ( ropt_net_134 ) , 
+    .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( ropt_net_132 ) , 
+    .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( copt_net_103 ) , 
+    .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__0_ ( chany_top_in , top_left_grid_pin_42_ , 
+    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
+    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
+    top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ , 
+    right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , 
+    right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , 
+    right_bottom_grid_pin_11_ , right_bottom_grid_pin_13_ , 
+    right_bottom_grid_pin_15_ , right_bottom_grid_pin_17_ , chanx_left_in , 
+    left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , 
+    left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , 
+    left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , 
+    left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , 
+    left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , 
+    chanx_left_out , ccff_tail , SC_IN_TOP , SC_OUT_TOP , Test_en_S_in , 
+    Test_en_N_out , prog_clk_0_N_in , prog_clk_3_S_in , prog_clk_3_N_out , 
+    clk_3_S_in , clk_3_N_out , VDD , VSS ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_42_ ;
+input  [0:0] top_left_grid_pin_43_ ;
+input  [0:0] top_left_grid_pin_44_ ;
+input  [0:0] top_left_grid_pin_45_ ;
+input  [0:0] top_left_grid_pin_46_ ;
+input  [0:0] top_left_grid_pin_47_ ;
+input  [0:0] top_left_grid_pin_48_ ;
+input  [0:0] top_left_grid_pin_49_ ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_bottom_grid_pin_1_ ;
+input  [0:0] right_bottom_grid_pin_3_ ;
+input  [0:0] right_bottom_grid_pin_5_ ;
+input  [0:0] right_bottom_grid_pin_7_ ;
+input  [0:0] right_bottom_grid_pin_9_ ;
+input  [0:0] right_bottom_grid_pin_11_ ;
+input  [0:0] right_bottom_grid_pin_13_ ;
+input  [0:0] right_bottom_grid_pin_15_ ;
+input  [0:0] right_bottom_grid_pin_17_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_bottom_grid_pin_1_ ;
+input  [0:0] left_bottom_grid_pin_3_ ;
+input  [0:0] left_bottom_grid_pin_5_ ;
+input  [0:0] left_bottom_grid_pin_7_ ;
+input  [0:0] left_bottom_grid_pin_9_ ;
+input  [0:0] left_bottom_grid_pin_11_ ;
+input  [0:0] left_bottom_grid_pin_13_ ;
+input  [0:0] left_bottom_grid_pin_15_ ;
+input  [0:0] left_bottom_grid_pin_17_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  SC_IN_TOP ;
+output SC_OUT_TOP ;
+input  Test_en_S_in ;
+output Test_en_N_out ;
+input  prog_clk_0_N_in ;
+input  prog_clk_3_S_in ;
+output prog_clk_3_N_out ;
+input  clk_3_S_in ;
+output clk_3_N_out ;
+input  VDD ;
+input  VSS ;
+
+wire ropt_net_118 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size14_0_sram ;
+wire [0:3] mux_tree_tapbuf_size14_1_sram ;
+wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:1] mux_tree_tapbuf_size3_5_sram ;
+wire [0:1] mux_tree_tapbuf_size3_6_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:3] mux_tree_tapbuf_size9_1_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_1__0__mux_tree_tapbuf_size8_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        chanx_right_in[1] , chanx_left_out[3] , chanx_left_in[0] , 
+        chanx_right_out[3] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 (
+    .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , 
+        right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , 
+        right_bottom_grid_pin_17_[0] , chanx_right_out[7] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 (
+    .in ( { chany_top_in[6] , chany_top_in[13] , chanx_left_out[5] , 
+        chanx_left_out[14] , left_bottom_grid_pin_3_[0] , 
+        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , 
+        left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 (
+    .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , 
+        chanx_left_out[7] , chanx_left_out[17] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem_2 mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_2 (
+    .in ( { chany_top_out[13] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_right_in[3] , chanx_left_out[5] , chanx_right_out[5] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 } ) ,
+    .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        chanx_left_out[6] , chanx_right_in[7] , chanx_right_out[6] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , 
+        SYNOPSYS_UNCONNECTED_22 } ) ,
+    .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 (
+    .in ( { chany_top_out[13] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_left_out[7] , chanx_right_in[11] , chanx_right_out[7] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , 
+        SYNOPSYS_UNCONNECTED_25 } ) ,
+    .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 (
+    .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , 
+        right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , 
+        chanx_right_out[9] , chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , 
+        SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_24 (
+    .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_13_[0] , 
+        chanx_right_out[10] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 } ) ,
+    .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_17 (
+    .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , 
+        chanx_left_out[9] , chanx_left_out[18] , left_bottom_grid_pin_3_[0] , 
+        left_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , 
+        SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 (
+    .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , 
+        chanx_left_out[10] , chanx_left_out[19] , left_bottom_grid_pin_5_[0] , 
+        left_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , 
+        SYNOPSYS_UNCONNECTED_37 } ) ,
+    .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_top_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_8 (
+    .in ( { top_left_grid_pin_42_[0] , chanx_left_out[9] , 
+        chanx_right_in[15] , chanx_right_out[9] } ) ,
+    .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , 
+        SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size4 mux_top_track_10 (
+    .in ( { chany_top_out[13] , chanx_left_out[10] , chanx_right_in[19] , 
+        chanx_right_out[10] } ) ,
+    .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 } ) ,
+    .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_10 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 (
+    .in ( { top_left_grid_pin_44_[0] , chanx_left_out[11] , 
+        chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) ,
+    .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 (
+    .in ( { top_left_grid_pin_45_[0] , chanx_left_out[13] , 
+        chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) ,
+    .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 (
+    .in ( { top_left_grid_pin_46_[0] , chanx_left_out[14] , 
+        chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) ,
+    .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 (
+    .in ( { top_left_grid_pin_47_[0] , chanx_left_out[15] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) ,
+    .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 (
+    .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) ,
+    .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 (
+    .in ( { top_left_grid_pin_49_[0] , chanx_left_out[18] , 
+        chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size3_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) ,
+    .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 (
+    .in ( { top_left_grid_pin_42_[0] , chanx_left_out[19] , 
+        chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size3_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) ,
+    .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 (
+    .in ( { chanx_right_in[0] , chanx_left_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) ,
+    .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_0 (
+    .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , 
+        right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] , 
+        chanx_right_out[3] , chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , 
+        SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) ,
+    .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size9 mux_right_track_2 (
+    .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , 
+        right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , 
+        right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_15_[0] , 
+        chanx_right_out[5] , chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size9_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , 
+        SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) ,
+    .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_mem mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size14_0 mux_right_track_4 (
+    .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , 
+        right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , 
+        right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , 
+        right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_15_[0] , 
+        right_bottom_grid_pin_17_[0] , chanx_right_out[6] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size14_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , 
+        SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) ,
+    .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size14 mux_left_track_5 (
+    .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , 
+        chanx_left_out[6] , chanx_left_out[15] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , 
+        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , 
+        left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_13_[0] , 
+        left_bottom_grid_pin_15_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size14_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , 
+        SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) ,
+    .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size14_mem mem_left_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_0 mux_right_track_32 (
+    .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , 
+        right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_15_[0] , 
+        chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , 
+        SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 (
+    .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , 
+        chanx_left_out[11] , left_bottom_grid_pin_7_[0] , 
+        left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , 
+        SYNOPSYS_UNCONNECTED_81 } ) ,
+    .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_mem mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__0__mux_tree_tapbuf_size10 mux_left_track_1 (
+    .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , 
+        chanx_left_out[3] , chanx_left_out[13] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , 
+        left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , 
+        SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) ,
+    .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size10_mem mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , 
+    .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , 
+    .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , 
+    .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( top_left_grid_pin_43_[0] ) , 
+    .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[3] ) , 
+    .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[7] ) , 
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_left_in[11] ) , 
+    .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_left_in[15] ) , 
+    .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( chanx_left_in[19] ) , 
+    .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_TOP ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( Test_en_N_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( Test_en_S_in ) , .Y ( BUF_net_86 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , 
+    .Y ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( clk_3_N_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , 
+    .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , 
+    .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , 
+    .HI ( optlc_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , 
+    .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_118 ) , 
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v
new file mode 100644
index 0000000..d8a05c3
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v
@@ -0,0 +1,2145 @@
+//
+//
+//
+//
+//
+//
+module sb_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+wire copt_net_107 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_107 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_106 ) , 
+    .X ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_107 ) , 
+    .X ( copt_net_106 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1288 ( .A ( copt_net_105 ) , 
+    .X ( mem_out[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_84 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , 
+    .Y ( BUF_net_82 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_92 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_78 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_76 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_74 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_72 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_70 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_66 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_133 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_98 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , 
+    .X ( copt_net_99 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_99 ) , 
+    .X ( copt_net_100 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_100 ) , 
+    .X ( copt_net_101 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_101 ) , 
+    .X ( copt_net_102 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_102 ) , 
+    .X ( copt_net_103 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1308 ( .A ( ropt_net_134 ) , 
+    .X ( ropt_net_132 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( ropt_net_132 ) , 
+    .X ( ropt_net_133 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( copt_net_103 ) , 
+    .X ( ropt_net_134 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .Y ( BUF_net_64 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .Y ( BUF_net_62 ) ) ;
+endmodule
+
+
+module sb_1__0_ ( chany_top_in , top_left_grid_pin_42_ , 
+    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
+    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
+    top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ , 
+    right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , 
+    right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , 
+    right_bottom_grid_pin_11_ , right_bottom_grid_pin_13_ , 
+    right_bottom_grid_pin_15_ , right_bottom_grid_pin_17_ , chanx_left_in , 
+    left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , 
+    left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , 
+    left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , 
+    left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , 
+    left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , 
+    chanx_left_out , ccff_tail , SC_IN_TOP , SC_OUT_TOP , Test_en_S_in , 
+    Test_en_N_out , prog_clk_0_N_in , prog_clk_3_S_in , prog_clk_3_N_out , 
+    clk_3_S_in , clk_3_N_out ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_42_ ;
+input  [0:0] top_left_grid_pin_43_ ;
+input  [0:0] top_left_grid_pin_44_ ;
+input  [0:0] top_left_grid_pin_45_ ;
+input  [0:0] top_left_grid_pin_46_ ;
+input  [0:0] top_left_grid_pin_47_ ;
+input  [0:0] top_left_grid_pin_48_ ;
+input  [0:0] top_left_grid_pin_49_ ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_bottom_grid_pin_1_ ;
+input  [0:0] right_bottom_grid_pin_3_ ;
+input  [0:0] right_bottom_grid_pin_5_ ;
+input  [0:0] right_bottom_grid_pin_7_ ;
+input  [0:0] right_bottom_grid_pin_9_ ;
+input  [0:0] right_bottom_grid_pin_11_ ;
+input  [0:0] right_bottom_grid_pin_13_ ;
+input  [0:0] right_bottom_grid_pin_15_ ;
+input  [0:0] right_bottom_grid_pin_17_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_bottom_grid_pin_1_ ;
+input  [0:0] left_bottom_grid_pin_3_ ;
+input  [0:0] left_bottom_grid_pin_5_ ;
+input  [0:0] left_bottom_grid_pin_7_ ;
+input  [0:0] left_bottom_grid_pin_9_ ;
+input  [0:0] left_bottom_grid_pin_11_ ;
+input  [0:0] left_bottom_grid_pin_13_ ;
+input  [0:0] left_bottom_grid_pin_15_ ;
+input  [0:0] left_bottom_grid_pin_17_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  SC_IN_TOP ;
+output SC_OUT_TOP ;
+input  Test_en_S_in ;
+output Test_en_N_out ;
+input  prog_clk_0_N_in ;
+input  prog_clk_3_S_in ;
+output prog_clk_3_N_out ;
+input  clk_3_S_in ;
+output clk_3_N_out ;
+
+wire ropt_net_118 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size14_0_sram ;
+wire [0:3] mux_tree_tapbuf_size14_1_sram ;
+wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:1] mux_tree_tapbuf_size3_5_sram ;
+wire [0:1] mux_tree_tapbuf_size3_6_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:3] mux_tree_tapbuf_size9_1_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_1__0__mux_tree_tapbuf_size8_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        chanx_right_in[1] , chanx_left_out[3] , chanx_left_in[0] , 
+        chanx_right_out[3] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 (
+    .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , 
+        right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , 
+        right_bottom_grid_pin_17_[0] , chanx_right_out[7] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 (
+    .in ( { chany_top_in[6] , chany_top_in[13] , chanx_left_out[5] , 
+        chanx_left_out[14] , left_bottom_grid_pin_3_[0] , 
+        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , 
+        left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 (
+    .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , 
+        chanx_left_out[7] , chanx_left_out[17] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem_2 mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_2 (
+    .in ( { chany_top_out[13] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_right_in[3] , chanx_left_out[5] , chanx_right_out[5] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 } ) ,
+    .out ( chany_top_out[1] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        chanx_left_out[6] , chanx_right_in[7] , chanx_right_out[6] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , 
+        SYNOPSYS_UNCONNECTED_22 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 (
+    .in ( { chany_top_out[13] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_left_out[7] , chanx_right_in[11] , chanx_right_out[7] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , 
+        SYNOPSYS_UNCONNECTED_25 } ) ,
+    .out ( chany_top_out[3] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 (
+    .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , 
+        right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , 
+        chanx_right_out[9] , chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , 
+        SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_24 (
+    .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_13_[0] , 
+        chanx_right_out[10] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_17 (
+    .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , 
+        chanx_left_out[9] , chanx_left_out[18] , left_bottom_grid_pin_3_[0] , 
+        left_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , 
+        SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 (
+    .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , 
+        chanx_left_out[10] , chanx_left_out[19] , left_bottom_grid_pin_5_[0] , 
+        left_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , 
+        SYNOPSYS_UNCONNECTED_37 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_top_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_8 (
+    .in ( { top_left_grid_pin_42_[0] , chanx_left_out[9] , 
+        chanx_right_in[15] , chanx_right_out[9] } ) ,
+    .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , 
+        SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size4 mux_top_track_10 (
+    .in ( { chany_top_out[13] , chanx_left_out[10] , chanx_right_in[19] , 
+        chanx_right_out[10] } ) ,
+    .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 } ) ,
+    .out ( chany_top_out[5] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_10 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 (
+    .in ( { top_left_grid_pin_44_[0] , chanx_left_out[11] , 
+        chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) ,
+    .out ( chany_top_out[6] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 (
+    .in ( { top_left_grid_pin_45_[0] , chanx_left_out[13] , 
+        chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) ,
+    .out ( chany_top_out[7] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 (
+    .in ( { top_left_grid_pin_46_[0] , chanx_left_out[14] , 
+        chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) ,
+    .out ( chany_top_out[8] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 (
+    .in ( { top_left_grid_pin_47_[0] , chanx_left_out[15] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) ,
+    .out ( chany_top_out[9] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 (
+    .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) ,
+    .out ( chany_top_out[10] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 (
+    .in ( { top_left_grid_pin_49_[0] , chanx_left_out[18] , 
+        chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size3_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) ,
+    .out ( chany_top_out[11] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 (
+    .in ( { top_left_grid_pin_42_[0] , chanx_left_out[19] , 
+        chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size3_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 (
+    .in ( { chanx_right_in[0] , chanx_left_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) ,
+    .out ( chany_top_out[19] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_0 (
+    .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , 
+        right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] , 
+        chanx_right_out[3] , chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , 
+        SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size9 mux_right_track_2 (
+    .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , 
+        right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , 
+        right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_15_[0] , 
+        chanx_right_out[5] , chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size9_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , 
+        SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_mem mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size14_0 mux_right_track_4 (
+    .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , 
+        right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , 
+        right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , 
+        right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_15_[0] , 
+        right_bottom_grid_pin_17_[0] , chanx_right_out[6] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size14_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , 
+        SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size14 mux_left_track_5 (
+    .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , 
+        chanx_left_out[6] , chanx_left_out[15] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , 
+        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , 
+        left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_13_[0] , 
+        left_bottom_grid_pin_15_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size14_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , 
+        SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size14_mem mem_left_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_0 mux_right_track_32 (
+    .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , 
+        right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_15_[0] , 
+        chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , 
+        SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 (
+    .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , 
+        chanx_left_out[11] , left_bottom_grid_pin_7_[0] , 
+        left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , 
+        SYNOPSYS_UNCONNECTED_81 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_mem mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size10 mux_left_track_1 (
+    .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , 
+        chanx_left_out[3] , chanx_left_out[13] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , 
+        left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , 
+        SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size10_mem mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , 
+    .HI ( optlc_net_93 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , 
+    .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , 
+    .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( top_left_grid_pin_43_[0] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[3] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[7] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_left_in[11] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_left_in[15] ) , 
+    .X ( ropt_net_118 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( chanx_left_in[19] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( Test_en_S_in ) , .Y ( BUF_net_86 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , 
+    .Y ( prog_clk_3_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_88 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( clk_3_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_90 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , 
+    .HI ( optlc_net_94 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , 
+    .HI ( optlc_net_95 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , 
+    .HI ( optlc_net_96 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , 
+    .HI ( optlc_net_97 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_118 ) , 
+    .X ( chany_top_out[15] ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.top_only.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..5714919
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.top_only.pt.v
@@ -0,0 +1,574 @@
+//
+//
+//
+//
+//
+//
+module sb_1__0_ ( chany_top_in , top_left_grid_pin_42_ , 
+    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
+    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
+    top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ , 
+    right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , 
+    right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , 
+    right_bottom_grid_pin_11_ , right_bottom_grid_pin_13_ , 
+    right_bottom_grid_pin_15_ , right_bottom_grid_pin_17_ , chanx_left_in , 
+    left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , 
+    left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , 
+    left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , 
+    left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , 
+    left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , 
+    chanx_left_out , ccff_tail , SC_IN_TOP , SC_OUT_TOP , Test_en_S_in , 
+    Test_en_N_out , prog_clk_0_N_in , prog_clk_3_S_in , prog_clk_3_N_out , 
+    clk_3_S_in , clk_3_N_out ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_42_ ;
+input  [0:0] top_left_grid_pin_43_ ;
+input  [0:0] top_left_grid_pin_44_ ;
+input  [0:0] top_left_grid_pin_45_ ;
+input  [0:0] top_left_grid_pin_46_ ;
+input  [0:0] top_left_grid_pin_47_ ;
+input  [0:0] top_left_grid_pin_48_ ;
+input  [0:0] top_left_grid_pin_49_ ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_bottom_grid_pin_1_ ;
+input  [0:0] right_bottom_grid_pin_3_ ;
+input  [0:0] right_bottom_grid_pin_5_ ;
+input  [0:0] right_bottom_grid_pin_7_ ;
+input  [0:0] right_bottom_grid_pin_9_ ;
+input  [0:0] right_bottom_grid_pin_11_ ;
+input  [0:0] right_bottom_grid_pin_13_ ;
+input  [0:0] right_bottom_grid_pin_15_ ;
+input  [0:0] right_bottom_grid_pin_17_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_bottom_grid_pin_1_ ;
+input  [0:0] left_bottom_grid_pin_3_ ;
+input  [0:0] left_bottom_grid_pin_5_ ;
+input  [0:0] left_bottom_grid_pin_7_ ;
+input  [0:0] left_bottom_grid_pin_9_ ;
+input  [0:0] left_bottom_grid_pin_11_ ;
+input  [0:0] left_bottom_grid_pin_13_ ;
+input  [0:0] left_bottom_grid_pin_15_ ;
+input  [0:0] left_bottom_grid_pin_17_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  SC_IN_TOP ;
+output SC_OUT_TOP ;
+input  Test_en_S_in ;
+output Test_en_N_out ;
+input  prog_clk_0_N_in ;
+input  prog_clk_3_S_in ;
+output prog_clk_3_N_out ;
+input  clk_3_S_in ;
+output clk_3_N_out ;
+
+wire ropt_net_118 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size14_0_sram ;
+wire [0:3] mux_tree_tapbuf_size14_1_sram ;
+wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:1] mux_tree_tapbuf_size3_5_sram ;
+wire [0:1] mux_tree_tapbuf_size3_6_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:3] mux_tree_tapbuf_size9_1_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_1__0__mux_tree_tapbuf_size8_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        chanx_right_in[1] , chanx_left_out[3] , chanx_left_in[0] , 
+        chanx_right_out[3] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 (
+    .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , 
+        right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , 
+        right_bottom_grid_pin_17_[0] , chanx_right_out[7] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 (
+    .in ( { chany_top_in[6] , chany_top_in[13] , chanx_left_out[5] , 
+        chanx_left_out[14] , left_bottom_grid_pin_3_[0] , 
+        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , 
+        left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 (
+    .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , 
+        chanx_left_out[7] , chanx_left_out[17] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem_2 mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_2 (
+    .in ( { chany_top_out[13] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_right_in[3] , chanx_left_out[5] , chanx_right_out[5] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 } ) ,
+    .out ( chany_top_out[1] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        chanx_left_out[6] , chanx_right_in[7] , chanx_right_out[6] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , 
+        SYNOPSYS_UNCONNECTED_22 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 (
+    .in ( { chany_top_out[13] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_left_out[7] , chanx_right_in[11] , chanx_right_out[7] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , 
+        SYNOPSYS_UNCONNECTED_25 } ) ,
+    .out ( chany_top_out[3] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 (
+    .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , 
+        right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , 
+        chanx_right_out[9] , chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , 
+        SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_24 (
+    .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_13_[0] , 
+        chanx_right_out[10] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_17 (
+    .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , 
+        chanx_left_out[9] , chanx_left_out[18] , left_bottom_grid_pin_3_[0] , 
+        left_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , 
+        SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 (
+    .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , 
+        chanx_left_out[10] , chanx_left_out[19] , left_bottom_grid_pin_5_[0] , 
+        left_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , 
+        SYNOPSYS_UNCONNECTED_37 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_top_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_8 (
+    .in ( { top_left_grid_pin_42_[0] , chanx_left_out[9] , 
+        chanx_right_in[15] , chanx_right_out[9] } ) ,
+    .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , 
+        SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size4 mux_top_track_10 (
+    .in ( { chany_top_out[13] , chanx_left_out[10] , chanx_right_in[19] , 
+        chanx_right_out[10] } ) ,
+    .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 } ) ,
+    .out ( chany_top_out[5] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_10 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 (
+    .in ( { top_left_grid_pin_44_[0] , chanx_left_out[11] , 
+        chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) ,
+    .out ( chany_top_out[6] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 (
+    .in ( { top_left_grid_pin_45_[0] , chanx_left_out[13] , 
+        chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) ,
+    .out ( chany_top_out[7] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 (
+    .in ( { top_left_grid_pin_46_[0] , chanx_left_out[14] , 
+        chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) ,
+    .out ( chany_top_out[8] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 (
+    .in ( { top_left_grid_pin_47_[0] , chanx_left_out[15] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) ,
+    .out ( chany_top_out[9] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 (
+    .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) ,
+    .out ( chany_top_out[10] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 (
+    .in ( { top_left_grid_pin_49_[0] , chanx_left_out[18] , 
+        chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size3_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) ,
+    .out ( chany_top_out[11] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 (
+    .in ( { top_left_grid_pin_42_[0] , chanx_left_out[19] , 
+        chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size3_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 (
+    .in ( { chanx_right_in[0] , chanx_left_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) ,
+    .out ( chany_top_out[19] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_0 (
+    .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , 
+        right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] , 
+        chanx_right_out[3] , chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , 
+        SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size9 mux_right_track_2 (
+    .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , 
+        right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , 
+        right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_15_[0] , 
+        chanx_right_out[5] , chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size9_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , 
+        SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_mem mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size14_0 mux_right_track_4 (
+    .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , 
+        right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , 
+        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , 
+        right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , 
+        right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_15_[0] , 
+        right_bottom_grid_pin_17_[0] , chanx_right_out[6] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size14_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , 
+        SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size14 mux_left_track_5 (
+    .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , 
+        chanx_left_out[6] , chanx_left_out[15] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , 
+        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , 
+        left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_13_[0] , 
+        left_bottom_grid_pin_15_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size14_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , 
+        SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size14_mem mem_left_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_0 mux_right_track_32 (
+    .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , 
+        right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_15_[0] , 
+        chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , 
+        SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 (
+    .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , 
+        chanx_left_out[11] , left_bottom_grid_pin_7_[0] , 
+        left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , 
+        SYNOPSYS_UNCONNECTED_81 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_mem mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size10 mux_left_track_1 (
+    .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , 
+        chanx_left_out[3] , chanx_left_out[13] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , 
+        left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , 
+        SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size10_mem mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , 
+    .HI ( optlc_net_93 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , 
+    .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , 
+    .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( top_left_grid_pin_43_[0] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[3] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[7] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_left_in[11] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_left_in[15] ) , 
+    .X ( ropt_net_118 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( chanx_left_in[19] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( Test_en_S_in ) , .Y ( BUF_net_86 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , 
+    .Y ( prog_clk_3_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_88 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( clk_3_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_90 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , 
+    .HI ( optlc_net_94 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , 
+    .HI ( optlc_net_95 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , 
+    .HI ( optlc_net_96 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , 
+    .HI ( optlc_net_97 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_118 ) , 
+    .X ( chany_top_out[15] ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v
new file mode 100644
index 0000000..7a82381
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v
@@ -0,0 +1,3185 @@
+//
+//
+//
+//
+//
+//
+module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( copt_net_119 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( mem_out[2] ) , 
+    .X ( copt_net_119 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__1__const1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_26 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__1__const1_26 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_25 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__1__const1_25 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_24 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__1__const1_24 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_23 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_23 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_22 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_22 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_21 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_21 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_99 ) ) ;
+endmodule
+
+
+module sb_1__1__const1_20 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_20 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_19 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_19 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_18 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_18 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_17 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_17 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_97 ) ) ;
+endmodule
+
+
+module sb_1__1__const1_16 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_16 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_95 ) ) ;
+endmodule
+
+
+module sb_1__1__const1_15 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_15 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_93 ) ) ;
+endmodule
+
+
+module sb_1__1__const1_14 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_14 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_13 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_13 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_12 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_12 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_89 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:4] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:4] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:4] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:4] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_11 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:15] in ;
+input  [0:4] sram ;
+input  [0:4] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_11 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_10 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:15] in ;
+input  [0:4] sram ;
+input  [0:4] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_10 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_9 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:15] in ;
+input  [0:4] sram ;
+input  [0:4] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_9 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_8 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:15] in ;
+input  [0:4] sram ;
+input  [0:4] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_8 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , 
+    .Y ( BUF_net_87 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_124 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_113 ) , 
+    .X ( copt_net_108 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_108 ) , 
+    .X ( copt_net_109 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_109 ) , 
+    .X ( copt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_110 ) , 
+    .X ( copt_net_111 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( copt_net_111 ) , 
+    .X ( copt_net_112 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_113 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1301 ( .A ( ropt_net_122 ) , 
+    .X ( ropt_net_121 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1302 ( .A ( copt_net_112 ) , 
+    .X ( ropt_net_122 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1303 ( .A ( ropt_net_121 ) , 
+    .X ( ropt_net_123 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1304 ( .A ( ropt_net_123 ) , 
+    .X ( ropt_net_124 ) ) ;
+endmodule
+
+
+module sb_1__1__const1_7 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_7 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_6 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_6 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
+    .Y ( BUF_net_85 ) ) ;
+endmodule
+
+
+module sb_1__1__const1_5 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_5 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_4 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_4 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_3 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_3 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_2 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_2 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__const1_1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
+    .Y ( BUF_net_82 ) ) ;
+endmodule
+
+
+module sb_1__1__const1_0 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__1__const1_0 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1_ ( chany_top_in , top_left_grid_pin_42_ , 
+    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
+    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
+    top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ , 
+    right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ , 
+    right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , 
+    right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , 
+    right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ , 
+    bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , 
+    bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , 
+    bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , 
+    bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , 
+    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
+    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
+    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
+    left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , 
+    chany_bottom_out , chanx_left_out , ccff_tail , Test_en_S_in , 
+    Test_en_N_out , prog_clk_0_N_in , prog_clk_1_N_in , prog_clk_1_S_in , 
+    prog_clk_1_E_out , prog_clk_1_W_out , prog_clk_2_N_in , prog_clk_2_E_in , 
+    prog_clk_2_S_in , prog_clk_2_W_in , prog_clk_2_W_out , prog_clk_2_S_out , 
+    prog_clk_2_N_out , prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , 
+    prog_clk_3_S_in , prog_clk_3_N_in , prog_clk_3_E_out , prog_clk_3_W_out , 
+    prog_clk_3_N_out , prog_clk_3_S_out , clk_1_N_in , clk_1_S_in , 
+    clk_1_E_out , clk_1_W_out , clk_2_N_in , clk_2_E_in , clk_2_S_in , 
+    clk_2_W_in , clk_2_W_out , clk_2_S_out , clk_2_N_out , clk_2_E_out , 
+    clk_3_W_in , clk_3_E_in , clk_3_S_in , clk_3_N_in , clk_3_E_out , 
+    clk_3_W_out , clk_3_N_out , clk_3_S_out ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_42_ ;
+input  [0:0] top_left_grid_pin_43_ ;
+input  [0:0] top_left_grid_pin_44_ ;
+input  [0:0] top_left_grid_pin_45_ ;
+input  [0:0] top_left_grid_pin_46_ ;
+input  [0:0] top_left_grid_pin_47_ ;
+input  [0:0] top_left_grid_pin_48_ ;
+input  [0:0] top_left_grid_pin_49_ ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_bottom_grid_pin_34_ ;
+input  [0:0] right_bottom_grid_pin_35_ ;
+input  [0:0] right_bottom_grid_pin_36_ ;
+input  [0:0] right_bottom_grid_pin_37_ ;
+input  [0:0] right_bottom_grid_pin_38_ ;
+input  [0:0] right_bottom_grid_pin_39_ ;
+input  [0:0] right_bottom_grid_pin_40_ ;
+input  [0:0] right_bottom_grid_pin_41_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_left_grid_pin_42_ ;
+input  [0:0] bottom_left_grid_pin_43_ ;
+input  [0:0] bottom_left_grid_pin_44_ ;
+input  [0:0] bottom_left_grid_pin_45_ ;
+input  [0:0] bottom_left_grid_pin_46_ ;
+input  [0:0] bottom_left_grid_pin_47_ ;
+input  [0:0] bottom_left_grid_pin_48_ ;
+input  [0:0] bottom_left_grid_pin_49_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_bottom_grid_pin_34_ ;
+input  [0:0] left_bottom_grid_pin_35_ ;
+input  [0:0] left_bottom_grid_pin_36_ ;
+input  [0:0] left_bottom_grid_pin_37_ ;
+input  [0:0] left_bottom_grid_pin_38_ ;
+input  [0:0] left_bottom_grid_pin_39_ ;
+input  [0:0] left_bottom_grid_pin_40_ ;
+input  [0:0] left_bottom_grid_pin_41_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  Test_en_S_in ;
+output Test_en_N_out ;
+input  prog_clk_0_N_in ;
+input  prog_clk_1_N_in ;
+input  prog_clk_1_S_in ;
+output prog_clk_1_E_out ;
+output prog_clk_1_W_out ;
+input  prog_clk_2_N_in ;
+input  prog_clk_2_E_in ;
+input  prog_clk_2_S_in ;
+input  prog_clk_2_W_in ;
+output prog_clk_2_W_out ;
+output prog_clk_2_S_out ;
+output prog_clk_2_N_out ;
+output prog_clk_2_E_out ;
+input  prog_clk_3_W_in ;
+input  prog_clk_3_E_in ;
+input  prog_clk_3_S_in ;
+input  prog_clk_3_N_in ;
+output prog_clk_3_E_out ;
+output prog_clk_3_W_out ;
+output prog_clk_3_N_out ;
+output prog_clk_3_S_out ;
+input  clk_1_N_in ;
+input  clk_1_S_in ;
+output clk_1_E_out ;
+output clk_1_W_out ;
+input  clk_2_N_in ;
+input  clk_2_E_in ;
+input  clk_2_S_in ;
+input  clk_2_W_in ;
+output clk_2_W_out ;
+output clk_2_S_out ;
+output clk_2_N_out ;
+output clk_2_E_out ;
+input  clk_3_W_in ;
+input  clk_3_E_in ;
+input  clk_3_S_in ;
+input  clk_3_N_in ;
+output clk_3_E_out ;
+output clk_3_W_out ;
+output clk_3_N_out ;
+output clk_3_S_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_10_sram ;
+wire [0:3] mux_tree_tapbuf_size10_11_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:3] mux_tree_tapbuf_size10_9_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size12_0_sram ;
+wire [0:3] mux_tree_tapbuf_size12_1_sram ;
+wire [0:3] mux_tree_tapbuf_size12_2_sram ;
+wire [0:3] mux_tree_tapbuf_size12_3_sram ;
+wire [0:3] mux_tree_tapbuf_size12_4_sram ;
+wire [0:3] mux_tree_tapbuf_size12_5_sram ;
+wire [0:3] mux_tree_tapbuf_size12_6_sram ;
+wire [0:3] mux_tree_tapbuf_size12_7_sram ;
+wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
+wire [0:4] mux_tree_tapbuf_size16_0_sram ;
+wire [0:4] mux_tree_tapbuf_size16_1_sram ;
+wire [0:4] mux_tree_tapbuf_size16_2_sram ;
+wire [0:4] mux_tree_tapbuf_size16_3_sram ;
+wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+
+assign prog_clk_1_E_out = prog_clk_1_S_in ;
+assign prog_clk_1_W_out = prog_clk_1_S_in ;
+assign prog_clk_2_W_out = prog_clk_2_W_in ;
+assign prog_clk_2_S_out = prog_clk_2_W_in ;
+assign prog_clk_2_N_out = prog_clk_2_W_in ;
+assign prog_clk_2_E_out = prog_clk_2_W_in ;
+assign prog_clk_3_E_out = prog_clk_3_N_in ;
+assign prog_clk_3_W_out = prog_clk_3_N_in ;
+assign prog_clk_3_N_out = prog_clk_3_N_in ;
+assign prog_clk_3_S_out = prog_clk_3_N_in ;
+assign clk_1_E_out = clk_1_S_in ;
+assign clk_1_W_out = clk_1_S_in ;
+assign clk_2_W_out = clk_2_W_in ;
+assign clk_2_S_out = clk_2_W_in ;
+assign clk_2_N_out = clk_2_W_in ;
+assign clk_2_E_out = clk_2_W_in ;
+assign clk_3_E_out = clk_3_N_in ;
+assign clk_3_W_out = clk_3_N_in ;
+assign clk_3_N_out = clk_3_N_in ;
+assign clk_3_S_out = clk_3_N_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_1_N_in = prog_clk_1_S_in ;
+assign prog_clk_2_W_in = prog_clk_2_N_in ;
+assign prog_clk_2_W_in = prog_clk_2_S_in ;
+assign prog_clk_3_N_in = prog_clk_3_W_in ;
+assign prog_clk_3_N_in = prog_clk_3_S_in ;
+assign clk_1_N_in = clk_1_S_in ;
+assign clk_2_W_in = clk_2_N_in ;
+assign clk_2_W_in = clk_2_S_in ;
+assign clk_3_N_in = clk_3_W_in ;
+assign clk_3_N_in = clk_3_S_in ;
+assign prog_clk_2_W_in = prog_clk_2_E_in ;
+assign prog_clk_3_N_in = prog_clk_3_E_in ;
+assign clk_2_W_in = clk_2_E_in ;
+assign clk_3_N_in = clk_3_E_in ;
+
+sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        chanx_right_in[1] , chanx_left_out[3] , chanx_left_out[13] , 
+        chany_top_out[3] , chany_top_out[13] , chanx_left_in[0] , 
+        chanx_right_out[3] , chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size12_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_2 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_right_in[3] , chanx_left_out[5] , chanx_left_out[14] , 
+        chany_top_out[5] , chany_top_out[14] , chanx_right_out[5] , 
+        chanx_right_out[14] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size12_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chany_top_out[1] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_0 (
+    .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chany_top_in[19] , 
+        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_top_out[3] , chany_top_out[13] , chany_bottom_in[15] , 
+        chanx_right_out[3] , chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size12_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 (
+    .in ( { chany_top_in[0] , chany_bottom_out[5] , chany_bottom_out[14] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_top_out[5] , chany_bottom_in[11] , chany_top_out[14] , 
+        chanx_right_out[5] , chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size12_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 (
+    .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_left_out[3] , 
+        chanx_left_out[13] , chanx_right_in[15] , 
+        bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_left_in[1] , chanx_right_out[3] , chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size12_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_left_out[5] , 
+        chanx_right_in[11] , chanx_left_out[14] , 
+        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , 
+        bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , 
+        chanx_left_in[3] , chanx_right_out[5] , chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size12_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_1 (
+    .in ( { chany_top_in[0] , chany_bottom_out[3] , chany_bottom_out[13] , 
+        chanx_left_out[3] , chanx_left_out[13] , chany_top_out[3] , 
+        chany_top_out[13] , chany_bottom_in[19] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size12_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_104 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chany_top_in[19] , 
+        chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , 
+        chany_top_out[5] , chany_top_out[14] , left_bottom_grid_pin_35_[0] , 
+        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size12_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_105 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_0 mux_top_track_4 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , 
+        top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , 
+        top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , 
+        chanx_left_out[6] , chanx_right_in[7] , chanx_left_out[15] , 
+        chany_top_out[6] , chany_top_out[15] , chanx_right_out[6] , 
+        chanx_right_out[15] , chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size16_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , 
+        SYNOPSYS_UNCONNECTED_37 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_1 mux_right_track_4 (
+    .in ( { chany_top_in[1] , chany_bottom_out[6] , chany_bottom_out[15] , 
+        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , 
+        right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] , 
+        right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_top_out[6] , chany_bottom_in[7] , chany_top_out[15] , 
+        chanx_right_out[6] , chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size16_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , 
+        SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , 
+        SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_2 mux_bottom_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_left_out[6] , 
+        chanx_right_in[7] , chanx_left_out[15] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , 
+        bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_right_out[6] , chanx_left_in[7] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size16_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , 
+        SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16 mux_left_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chany_top_in[15] , 
+        chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] , 
+        chany_top_out[6] , chany_top_out[15] , left_bottom_grid_pin_34_[0] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_38_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size16_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , 
+        SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , 
+        SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_105 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size16_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size16_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size16_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem mem_left_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size16_3_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_0 mux_top_track_8 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , 
+        chanx_left_out[7] , chanx_right_in[11] , chanx_left_out[17] , 
+        chany_top_out[7] , chany_top_out[17] , chanx_right_out[7] , 
+        chanx_left_in[11] , chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_16 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , 
+        chanx_left_out[9] , chanx_right_in[15] , chanx_left_out[18] , 
+        chany_top_out[9] , chany_top_out[18] , chanx_left_in[7] , 
+        chanx_right_out[9] , chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( chany_top_out[8] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 (
+    .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , 
+        chanx_left_out[10] , chanx_left_out[19] , chanx_right_in[19] , 
+        chany_top_out[10] , chany_top_out[19] , chanx_left_in[3] , 
+        chanx_right_out[10] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_8 (
+    .in ( { chany_top_in[3] , chany_bottom_out[7] , chany_bottom_out[17] , 
+        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , 
+        chany_bottom_in[3] , chany_top_out[7] , chany_top_out[17] , 
+        chanx_right_out[7] , chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
+        SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_16 (
+    .in ( { chany_top_in[7] , chany_bottom_out[9] , chany_bottom_out[18] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , 
+        chany_bottom_in[1] , chany_top_out[9] , chany_top_out[18] , 
+        chanx_right_out[9] , chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , 
+        SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 (
+    .in ( { chany_bottom_out[10] , chany_top_in[11] , chany_bottom_out[19] , 
+        right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[0] , chany_top_out[10] , chany_top_out[19] , 
+        chanx_right_out[10] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , 
+        SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_107 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_9 (
+    .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[3] , 
+        chanx_left_out[7] , chanx_left_out[17] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_46_[0] , chanx_right_out[7] , chanx_left_in[11] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , 
+        SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_7 mux_bottom_track_17 (
+    .in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] , 
+        chanx_left_out[9] , chanx_left_out[18] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_47_[0] , chanx_right_out[9] , chanx_left_in[15] , 
+        chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , 
+        SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_25 (
+    .in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] , 
+        chanx_left_out[10] , chanx_left_out[19] , 
+        bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_right_out[10] , chanx_right_out[19] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , 
+        SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_9 (
+    .in ( { chany_bottom_out[7] , chany_top_in[11] , chany_bottom_out[17] , 
+        chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[3] , 
+        chany_top_out[7] , chany_top_out[17] , left_bottom_grid_pin_34_[0] , 
+        left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size10_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , 
+        SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_17 (
+    .in ( { chany_top_in[7] , chany_bottom_out[9] , chany_bottom_out[18] , 
+        chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[7] , 
+        chany_top_out[9] , chany_top_out[18] , left_bottom_grid_pin_35_[0] , 
+        left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size10_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , 
+        SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_104 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 (
+    .in ( { chany_top_in[3] , chany_bottom_out[10] , chany_bottom_out[19] , 
+        chanx_left_out[10] , chanx_left_out[19] , chany_top_out[10] , 
+        chany_bottom_in[11] , chany_top_out[19] , 
+        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size10_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , 
+        SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_104 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_left_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_0 mux_top_track_32 (
+    .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , 
+        chanx_right_in[0] , chanx_left_out[11] , chany_top_out[11] , 
+        chanx_left_in[1] , chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , 
+        SYNOPSYS_UNCONNECTED_103 } ) ,
+    .out ( chany_top_out[16] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 (
+    .in ( { chany_bottom_out[11] , chany_top_in[15] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_top_out[11] , chany_bottom_in[19] , chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , 
+        SYNOPSYS_UNCONNECTED_106 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_2 mux_bottom_track_33 (
+    .in ( { chany_bottom_out[11] , chanx_left_out[11] , chanx_right_in[19] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , 
+        chanx_left_in[0] , chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 , 
+        SYNOPSYS_UNCONNECTED_109 } ) ,
+    .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7 mux_left_track_33 (
+    .in ( { chany_top_in[1] , chany_bottom_out[11] , chanx_left_out[11] , 
+        chany_top_out[11] , chany_bottom_in[15] , 
+        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , 
+        SYNOPSYS_UNCONNECTED_112 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_105 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sky130_fd_sc_hd__buf_6 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , 
+    .X ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , 
+    .HI ( optlc_net_102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , 
+    .HI ( optlc_net_103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_115 ) , 
+    .HI ( optlc_net_104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_116 ) , 
+    .HI ( optlc_net_105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , 
+    .HI ( optlc_net_106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , 
+    .HI ( optlc_net_107 ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v
new file mode 100644
index 0000000..4069db1
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v
@@ -0,0 +1,3397 @@
+//
+//
+//
+//
+//
+//
+module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( copt_net_119 ) , 
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( mem_out[2] ) , 
+    .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:4] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:4] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:4] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:4] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:15] in ;
+input  [0:4] sram ;
+input  [0:4] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:15] in ;
+input  [0:4] sram ;
+input  [0:4] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:15] in ;
+input  [0:4] sram ;
+input  [0:4] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:15] in ;
+input  [0:4] sram ;
+input  [0:4] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , 
+    .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_124 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_113 ) , 
+    .X ( copt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_108 ) , 
+    .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_109 ) , 
+    .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_110 ) , 
+    .X ( copt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( copt_net_111 ) , 
+    .X ( copt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1301 ( .A ( ropt_net_122 ) , 
+    .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1302 ( .A ( copt_net_112 ) , 
+    .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1303 ( .A ( ropt_net_121 ) , 
+    .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1304 ( .A ( ropt_net_123 ) , 
+    .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
+    .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
+    .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__1_ ( chany_top_in , top_left_grid_pin_42_ , 
+    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
+    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
+    top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ , 
+    right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ , 
+    right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , 
+    right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , 
+    right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ , 
+    bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , 
+    bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , 
+    bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , 
+    bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , 
+    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
+    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
+    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
+    left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , 
+    chany_bottom_out , chanx_left_out , ccff_tail , Test_en_S_in , 
+    Test_en_N_out , prog_clk_0_N_in , prog_clk_1_N_in , prog_clk_1_S_in , 
+    prog_clk_1_E_out , prog_clk_1_W_out , prog_clk_2_N_in , prog_clk_2_E_in , 
+    prog_clk_2_S_in , prog_clk_2_W_in , prog_clk_2_W_out , prog_clk_2_S_out , 
+    prog_clk_2_N_out , prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , 
+    prog_clk_3_S_in , prog_clk_3_N_in , prog_clk_3_E_out , prog_clk_3_W_out , 
+    prog_clk_3_N_out , prog_clk_3_S_out , clk_1_N_in , clk_1_S_in , 
+    clk_1_E_out , clk_1_W_out , clk_2_N_in , clk_2_E_in , clk_2_S_in , 
+    clk_2_W_in , clk_2_W_out , clk_2_S_out , clk_2_N_out , clk_2_E_out , 
+    clk_3_W_in , clk_3_E_in , clk_3_S_in , clk_3_N_in , clk_3_E_out , 
+    clk_3_W_out , clk_3_N_out , clk_3_S_out , VDD , VSS ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_42_ ;
+input  [0:0] top_left_grid_pin_43_ ;
+input  [0:0] top_left_grid_pin_44_ ;
+input  [0:0] top_left_grid_pin_45_ ;
+input  [0:0] top_left_grid_pin_46_ ;
+input  [0:0] top_left_grid_pin_47_ ;
+input  [0:0] top_left_grid_pin_48_ ;
+input  [0:0] top_left_grid_pin_49_ ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_bottom_grid_pin_34_ ;
+input  [0:0] right_bottom_grid_pin_35_ ;
+input  [0:0] right_bottom_grid_pin_36_ ;
+input  [0:0] right_bottom_grid_pin_37_ ;
+input  [0:0] right_bottom_grid_pin_38_ ;
+input  [0:0] right_bottom_grid_pin_39_ ;
+input  [0:0] right_bottom_grid_pin_40_ ;
+input  [0:0] right_bottom_grid_pin_41_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_left_grid_pin_42_ ;
+input  [0:0] bottom_left_grid_pin_43_ ;
+input  [0:0] bottom_left_grid_pin_44_ ;
+input  [0:0] bottom_left_grid_pin_45_ ;
+input  [0:0] bottom_left_grid_pin_46_ ;
+input  [0:0] bottom_left_grid_pin_47_ ;
+input  [0:0] bottom_left_grid_pin_48_ ;
+input  [0:0] bottom_left_grid_pin_49_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_bottom_grid_pin_34_ ;
+input  [0:0] left_bottom_grid_pin_35_ ;
+input  [0:0] left_bottom_grid_pin_36_ ;
+input  [0:0] left_bottom_grid_pin_37_ ;
+input  [0:0] left_bottom_grid_pin_38_ ;
+input  [0:0] left_bottom_grid_pin_39_ ;
+input  [0:0] left_bottom_grid_pin_40_ ;
+input  [0:0] left_bottom_grid_pin_41_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  Test_en_S_in ;
+output Test_en_N_out ;
+input  prog_clk_0_N_in ;
+input  prog_clk_1_N_in ;
+input  prog_clk_1_S_in ;
+output prog_clk_1_E_out ;
+output prog_clk_1_W_out ;
+input  prog_clk_2_N_in ;
+input  prog_clk_2_E_in ;
+input  prog_clk_2_S_in ;
+input  prog_clk_2_W_in ;
+output prog_clk_2_W_out ;
+output prog_clk_2_S_out ;
+output prog_clk_2_N_out ;
+output prog_clk_2_E_out ;
+input  prog_clk_3_W_in ;
+input  prog_clk_3_E_in ;
+input  prog_clk_3_S_in ;
+input  prog_clk_3_N_in ;
+output prog_clk_3_E_out ;
+output prog_clk_3_W_out ;
+output prog_clk_3_N_out ;
+output prog_clk_3_S_out ;
+input  clk_1_N_in ;
+input  clk_1_S_in ;
+output clk_1_E_out ;
+output clk_1_W_out ;
+input  clk_2_N_in ;
+input  clk_2_E_in ;
+input  clk_2_S_in ;
+input  clk_2_W_in ;
+output clk_2_W_out ;
+output clk_2_S_out ;
+output clk_2_N_out ;
+output clk_2_E_out ;
+input  clk_3_W_in ;
+input  clk_3_E_in ;
+input  clk_3_S_in ;
+input  clk_3_N_in ;
+output clk_3_E_out ;
+output clk_3_W_out ;
+output clk_3_N_out ;
+output clk_3_S_out ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_10_sram ;
+wire [0:3] mux_tree_tapbuf_size10_11_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:3] mux_tree_tapbuf_size10_9_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size12_0_sram ;
+wire [0:3] mux_tree_tapbuf_size12_1_sram ;
+wire [0:3] mux_tree_tapbuf_size12_2_sram ;
+wire [0:3] mux_tree_tapbuf_size12_3_sram ;
+wire [0:3] mux_tree_tapbuf_size12_4_sram ;
+wire [0:3] mux_tree_tapbuf_size12_5_sram ;
+wire [0:3] mux_tree_tapbuf_size12_6_sram ;
+wire [0:3] mux_tree_tapbuf_size12_7_sram ;
+wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
+wire [0:4] mux_tree_tapbuf_size16_0_sram ;
+wire [0:4] mux_tree_tapbuf_size16_1_sram ;
+wire [0:4] mux_tree_tapbuf_size16_2_sram ;
+wire [0:4] mux_tree_tapbuf_size16_3_sram ;
+wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
+
+assign prog_clk_1_E_out = prog_clk_1_S_in ;
+assign prog_clk_1_W_out = prog_clk_1_S_in ;
+assign prog_clk_2_W_out = prog_clk_2_W_in ;
+assign prog_clk_2_S_out = prog_clk_2_W_in ;
+assign prog_clk_2_N_out = prog_clk_2_W_in ;
+assign prog_clk_2_E_out = prog_clk_2_W_in ;
+assign prog_clk_3_E_out = prog_clk_3_N_in ;
+assign prog_clk_3_W_out = prog_clk_3_N_in ;
+assign prog_clk_3_N_out = prog_clk_3_N_in ;
+assign prog_clk_3_S_out = prog_clk_3_N_in ;
+assign clk_1_E_out = clk_1_S_in ;
+assign clk_1_W_out = clk_1_S_in ;
+assign clk_2_W_out = clk_2_W_in ;
+assign clk_2_S_out = clk_2_W_in ;
+assign clk_2_N_out = clk_2_W_in ;
+assign clk_2_E_out = clk_2_W_in ;
+assign clk_3_E_out = clk_3_N_in ;
+assign clk_3_W_out = clk_3_N_in ;
+assign clk_3_N_out = clk_3_N_in ;
+assign clk_3_S_out = clk_3_N_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_1_N_in = prog_clk_1_S_in ;
+assign prog_clk_2_W_in = prog_clk_2_N_in ;
+assign prog_clk_2_W_in = prog_clk_2_S_in ;
+assign prog_clk_3_N_in = prog_clk_3_W_in ;
+assign prog_clk_3_N_in = prog_clk_3_S_in ;
+assign clk_1_N_in = clk_1_S_in ;
+assign clk_2_W_in = clk_2_N_in ;
+assign clk_2_W_in = clk_2_S_in ;
+assign clk_3_N_in = clk_3_W_in ;
+assign clk_3_N_in = clk_3_S_in ;
+assign prog_clk_2_W_in = prog_clk_2_E_in ;
+assign prog_clk_3_N_in = prog_clk_3_E_in ;
+assign clk_2_W_in = clk_2_E_in ;
+assign clk_3_N_in = clk_3_E_in ;
+
+sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        chanx_right_in[1] , chanx_left_out[3] , chanx_left_out[13] , 
+        chany_top_out[3] , chany_top_out[13] , chanx_left_in[0] , 
+        chanx_right_out[3] , chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size12_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_2 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_right_in[3] , chanx_left_out[5] , chanx_left_out[14] , 
+        chany_top_out[5] , chany_top_out[14] , chanx_right_out[5] , 
+        chanx_right_out[14] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size12_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_0 (
+    .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chany_top_in[19] , 
+        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_top_out[3] , chany_top_out[13] , chany_bottom_in[15] , 
+        chanx_right_out[3] , chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size12_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 (
+    .in ( { chany_top_in[0] , chany_bottom_out[5] , chany_bottom_out[14] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_top_out[5] , chany_bottom_in[11] , chany_top_out[14] , 
+        chanx_right_out[5] , chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size12_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 (
+    .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_left_out[3] , 
+        chanx_left_out[13] , chanx_right_in[15] , 
+        bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_left_in[1] , chanx_right_out[3] , chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size12_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_left_out[5] , 
+        chanx_right_in[11] , chanx_left_out[14] , 
+        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , 
+        bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , 
+        chanx_left_in[3] , chanx_right_out[5] , chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size12_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_1 (
+    .in ( { chany_top_in[0] , chany_bottom_out[3] , chany_bottom_out[13] , 
+        chanx_left_out[3] , chanx_left_out[13] , chany_top_out[3] , 
+        chany_top_out[13] , chany_bottom_in[19] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size12_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_104 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chany_top_in[19] , 
+        chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , 
+        chany_top_out[5] , chany_top_out[14] , left_bottom_grid_pin_35_[0] , 
+        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size12_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_105 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_0 mux_top_track_4 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , 
+        top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , 
+        top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , 
+        chanx_left_out[6] , chanx_right_in[7] , chanx_left_out[15] , 
+        chany_top_out[6] , chany_top_out[15] , chanx_right_out[6] , 
+        chanx_right_out[15] , chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size16_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , 
+        SYNOPSYS_UNCONNECTED_37 } ) ,
+    .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_1 mux_right_track_4 (
+    .in ( { chany_top_in[1] , chany_bottom_out[6] , chany_bottom_out[15] , 
+        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , 
+        right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] , 
+        right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_top_out[6] , chany_bottom_in[7] , chany_top_out[15] , 
+        chanx_right_out[6] , chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size16_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , 
+        SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , 
+        SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_2 mux_bottom_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_left_out[6] , 
+        chanx_right_in[7] , chanx_left_out[15] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , 
+        bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_right_out[6] , chanx_left_in[7] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size16_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , 
+        SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 } ) ,
+    .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16 mux_left_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chany_top_in[15] , 
+        chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] , 
+        chany_top_out[6] , chany_top_out[15] , left_bottom_grid_pin_34_[0] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_38_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size16_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , 
+        SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , 
+        SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_105 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size16_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size16_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size16_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem mem_left_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size16_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_0 mux_top_track_8 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , 
+        chanx_left_out[7] , chanx_right_in[11] , chanx_left_out[17] , 
+        chany_top_out[7] , chany_top_out[17] , chanx_right_out[7] , 
+        chanx_left_in[11] , chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_16 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , 
+        chanx_left_out[9] , chanx_right_in[15] , chanx_left_out[18] , 
+        chany_top_out[9] , chany_top_out[18] , chanx_left_in[7] , 
+        chanx_right_out[9] , chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 (
+    .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , 
+        chanx_left_out[10] , chanx_left_out[19] , chanx_right_in[19] , 
+        chany_top_out[10] , chany_top_out[19] , chanx_left_in[3] , 
+        chanx_right_out[10] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_8 (
+    .in ( { chany_top_in[3] , chany_bottom_out[7] , chany_bottom_out[17] , 
+        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , 
+        chany_bottom_in[3] , chany_top_out[7] , chany_top_out[17] , 
+        chanx_right_out[7] , chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
+        SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_16 (
+    .in ( { chany_top_in[7] , chany_bottom_out[9] , chany_bottom_out[18] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , 
+        chany_bottom_in[1] , chany_top_out[9] , chany_top_out[18] , 
+        chanx_right_out[9] , chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , 
+        SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 (
+    .in ( { chany_bottom_out[10] , chany_top_in[11] , chany_bottom_out[19] , 
+        right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[0] , chany_top_out[10] , chany_top_out[19] , 
+        chanx_right_out[10] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , 
+        SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_107 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_9 (
+    .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[3] , 
+        chanx_left_out[7] , chanx_left_out[17] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_46_[0] , chanx_right_out[7] , chanx_left_in[11] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , 
+        SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+    .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_7 mux_bottom_track_17 (
+    .in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] , 
+        chanx_left_out[9] , chanx_left_out[18] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_47_[0] , chanx_right_out[9] , chanx_left_in[15] , 
+        chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , 
+        SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+    .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_25 (
+    .in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] , 
+        chanx_left_out[10] , chanx_left_out[19] , 
+        bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_right_out[10] , chanx_right_out[19] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , 
+        SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+    .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_9 (
+    .in ( { chany_bottom_out[7] , chany_top_in[11] , chany_bottom_out[17] , 
+        chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[3] , 
+        chany_top_out[7] , chany_top_out[17] , left_bottom_grid_pin_34_[0] , 
+        left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size10_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , 
+        SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+    .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_17 (
+    .in ( { chany_top_in[7] , chany_bottom_out[9] , chany_bottom_out[18] , 
+        chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[7] , 
+        chany_top_out[9] , chany_top_out[18] , left_bottom_grid_pin_35_[0] , 
+        left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size10_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , 
+        SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+    .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_104 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 (
+    .in ( { chany_top_in[3] , chany_bottom_out[10] , chany_bottom_out[19] , 
+        chanx_left_out[10] , chanx_left_out[19] , chany_top_out[10] , 
+        chany_bottom_in[11] , chany_top_out[19] , 
+        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size10_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , 
+        SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
+    .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_104 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_left_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_10_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_0 mux_top_track_32 (
+    .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , 
+        chanx_right_in[0] , chanx_left_out[11] , chany_top_out[11] , 
+        chanx_left_in[1] , chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , 
+        SYNOPSYS_UNCONNECTED_103 } ) ,
+    .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 (
+    .in ( { chany_bottom_out[11] , chany_top_in[15] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_top_out[11] , chany_bottom_in[19] , chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , 
+        SYNOPSYS_UNCONNECTED_106 } ) ,
+    .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_2 mux_bottom_track_33 (
+    .in ( { chany_bottom_out[11] , chanx_left_out[11] , chanx_right_in[19] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , 
+        chanx_left_in[0] , chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 , 
+        SYNOPSYS_UNCONNECTED_109 } ) ,
+    .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7 mux_left_track_33 (
+    .in ( { chany_top_in[1] , chany_bottom_out[11] , chanx_left_out[11] , 
+        chany_top_out[11] , chany_bottom_in[15] , 
+        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , 
+        SYNOPSYS_UNCONNECTED_112 } ) ,
+    .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_105 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , 
+    .X ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , 
+    .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , 
+    .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_115 ) , 
+    .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_116 ) , 
+    .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , 
+    .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , 
+    .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v
new file mode 100644
index 0000000..a0e5561
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v
@@ -0,0 +1,2877 @@
+//
+//
+//
+//
+//
+//
+module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( copt_net_119 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( mem_out[2] ) , 
+    .X ( copt_net_119 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_99 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_97 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_95 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_93 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_89 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:4] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:4] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:4] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:4] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:15] in ;
+input  [0:4] sram ;
+input  [0:4] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:15] in ;
+input  [0:4] sram ;
+input  [0:4] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:15] in ;
+input  [0:4] sram ;
+input  [0:4] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:15] in ;
+input  [0:4] sram ;
+input  [0:4] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , 
+    .Y ( BUF_net_87 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_124 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_113 ) , 
+    .X ( copt_net_108 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_108 ) , 
+    .X ( copt_net_109 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_109 ) , 
+    .X ( copt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_110 ) , 
+    .X ( copt_net_111 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( copt_net_111 ) , 
+    .X ( copt_net_112 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_113 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1301 ( .A ( ropt_net_122 ) , 
+    .X ( ropt_net_121 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1302 ( .A ( copt_net_112 ) , 
+    .X ( ropt_net_122 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1303 ( .A ( ropt_net_121 ) , 
+    .X ( ropt_net_123 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1304 ( .A ( ropt_net_123 ) , 
+    .X ( ropt_net_124 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
+    .Y ( BUF_net_85 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
+    .Y ( BUF_net_82 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1_ ( chany_top_in , top_left_grid_pin_42_ , 
+    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
+    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
+    top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ , 
+    right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ , 
+    right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , 
+    right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , 
+    right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ , 
+    bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , 
+    bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , 
+    bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , 
+    bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , 
+    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
+    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
+    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
+    left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , 
+    chany_bottom_out , chanx_left_out , ccff_tail , Test_en_S_in , 
+    Test_en_N_out , prog_clk_0_N_in , prog_clk_1_N_in , prog_clk_1_S_in , 
+    prog_clk_1_E_out , prog_clk_1_W_out , prog_clk_2_N_in , prog_clk_2_E_in , 
+    prog_clk_2_S_in , prog_clk_2_W_in , prog_clk_2_W_out , prog_clk_2_S_out , 
+    prog_clk_2_N_out , prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , 
+    prog_clk_3_S_in , prog_clk_3_N_in , prog_clk_3_E_out , prog_clk_3_W_out , 
+    prog_clk_3_N_out , prog_clk_3_S_out , clk_1_N_in , clk_1_S_in , 
+    clk_1_E_out , clk_1_W_out , clk_2_N_in , clk_2_E_in , clk_2_S_in , 
+    clk_2_W_in , clk_2_W_out , clk_2_S_out , clk_2_N_out , clk_2_E_out , 
+    clk_3_W_in , clk_3_E_in , clk_3_S_in , clk_3_N_in , clk_3_E_out , 
+    clk_3_W_out , clk_3_N_out , clk_3_S_out ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_42_ ;
+input  [0:0] top_left_grid_pin_43_ ;
+input  [0:0] top_left_grid_pin_44_ ;
+input  [0:0] top_left_grid_pin_45_ ;
+input  [0:0] top_left_grid_pin_46_ ;
+input  [0:0] top_left_grid_pin_47_ ;
+input  [0:0] top_left_grid_pin_48_ ;
+input  [0:0] top_left_grid_pin_49_ ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_bottom_grid_pin_34_ ;
+input  [0:0] right_bottom_grid_pin_35_ ;
+input  [0:0] right_bottom_grid_pin_36_ ;
+input  [0:0] right_bottom_grid_pin_37_ ;
+input  [0:0] right_bottom_grid_pin_38_ ;
+input  [0:0] right_bottom_grid_pin_39_ ;
+input  [0:0] right_bottom_grid_pin_40_ ;
+input  [0:0] right_bottom_grid_pin_41_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_left_grid_pin_42_ ;
+input  [0:0] bottom_left_grid_pin_43_ ;
+input  [0:0] bottom_left_grid_pin_44_ ;
+input  [0:0] bottom_left_grid_pin_45_ ;
+input  [0:0] bottom_left_grid_pin_46_ ;
+input  [0:0] bottom_left_grid_pin_47_ ;
+input  [0:0] bottom_left_grid_pin_48_ ;
+input  [0:0] bottom_left_grid_pin_49_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_bottom_grid_pin_34_ ;
+input  [0:0] left_bottom_grid_pin_35_ ;
+input  [0:0] left_bottom_grid_pin_36_ ;
+input  [0:0] left_bottom_grid_pin_37_ ;
+input  [0:0] left_bottom_grid_pin_38_ ;
+input  [0:0] left_bottom_grid_pin_39_ ;
+input  [0:0] left_bottom_grid_pin_40_ ;
+input  [0:0] left_bottom_grid_pin_41_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  Test_en_S_in ;
+output Test_en_N_out ;
+input  prog_clk_0_N_in ;
+input  prog_clk_1_N_in ;
+input  prog_clk_1_S_in ;
+output prog_clk_1_E_out ;
+output prog_clk_1_W_out ;
+input  prog_clk_2_N_in ;
+input  prog_clk_2_E_in ;
+input  prog_clk_2_S_in ;
+input  prog_clk_2_W_in ;
+output prog_clk_2_W_out ;
+output prog_clk_2_S_out ;
+output prog_clk_2_N_out ;
+output prog_clk_2_E_out ;
+input  prog_clk_3_W_in ;
+input  prog_clk_3_E_in ;
+input  prog_clk_3_S_in ;
+input  prog_clk_3_N_in ;
+output prog_clk_3_E_out ;
+output prog_clk_3_W_out ;
+output prog_clk_3_N_out ;
+output prog_clk_3_S_out ;
+input  clk_1_N_in ;
+input  clk_1_S_in ;
+output clk_1_E_out ;
+output clk_1_W_out ;
+input  clk_2_N_in ;
+input  clk_2_E_in ;
+input  clk_2_S_in ;
+input  clk_2_W_in ;
+output clk_2_W_out ;
+output clk_2_S_out ;
+output clk_2_N_out ;
+output clk_2_E_out ;
+input  clk_3_W_in ;
+input  clk_3_E_in ;
+input  clk_3_S_in ;
+input  clk_3_N_in ;
+output clk_3_E_out ;
+output clk_3_W_out ;
+output clk_3_N_out ;
+output clk_3_S_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_10_sram ;
+wire [0:3] mux_tree_tapbuf_size10_11_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:3] mux_tree_tapbuf_size10_9_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size12_0_sram ;
+wire [0:3] mux_tree_tapbuf_size12_1_sram ;
+wire [0:3] mux_tree_tapbuf_size12_2_sram ;
+wire [0:3] mux_tree_tapbuf_size12_3_sram ;
+wire [0:3] mux_tree_tapbuf_size12_4_sram ;
+wire [0:3] mux_tree_tapbuf_size12_5_sram ;
+wire [0:3] mux_tree_tapbuf_size12_6_sram ;
+wire [0:3] mux_tree_tapbuf_size12_7_sram ;
+wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
+wire [0:4] mux_tree_tapbuf_size16_0_sram ;
+wire [0:4] mux_tree_tapbuf_size16_1_sram ;
+wire [0:4] mux_tree_tapbuf_size16_2_sram ;
+wire [0:4] mux_tree_tapbuf_size16_3_sram ;
+wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+
+assign prog_clk_1_E_out = prog_clk_1_S_in ;
+assign prog_clk_1_W_out = prog_clk_1_S_in ;
+assign prog_clk_2_W_out = prog_clk_2_W_in ;
+assign prog_clk_2_S_out = prog_clk_2_W_in ;
+assign prog_clk_2_N_out = prog_clk_2_W_in ;
+assign prog_clk_2_E_out = prog_clk_2_W_in ;
+assign prog_clk_3_E_out = prog_clk_3_N_in ;
+assign prog_clk_3_W_out = prog_clk_3_N_in ;
+assign prog_clk_3_N_out = prog_clk_3_N_in ;
+assign prog_clk_3_S_out = prog_clk_3_N_in ;
+assign clk_1_E_out = clk_1_S_in ;
+assign clk_1_W_out = clk_1_S_in ;
+assign clk_2_W_out = clk_2_W_in ;
+assign clk_2_S_out = clk_2_W_in ;
+assign clk_2_N_out = clk_2_W_in ;
+assign clk_2_E_out = clk_2_W_in ;
+assign clk_3_E_out = clk_3_N_in ;
+assign clk_3_W_out = clk_3_N_in ;
+assign clk_3_N_out = clk_3_N_in ;
+assign clk_3_S_out = clk_3_N_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_1_S_in = prog_clk_1_N_in ;
+assign prog_clk_2_N_in = prog_clk_2_W_in ;
+assign prog_clk_2_S_in = prog_clk_2_W_in ;
+assign prog_clk_3_W_in = prog_clk_3_N_in ;
+assign prog_clk_3_S_in = prog_clk_3_N_in ;
+assign clk_1_S_in = clk_1_N_in ;
+assign clk_2_N_in = clk_2_W_in ;
+assign clk_2_S_in = clk_2_W_in ;
+assign clk_3_W_in = clk_3_N_in ;
+assign clk_3_S_in = clk_3_N_in ;
+assign prog_clk_2_E_in = prog_clk_2_W_in ;
+assign prog_clk_3_E_in = prog_clk_3_N_in ;
+assign clk_2_E_in = clk_2_W_in ;
+assign clk_3_E_in = clk_3_N_in ;
+
+sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        chanx_right_in[1] , chanx_left_out[3] , chanx_left_out[13] , 
+        chany_top_out[3] , chany_top_out[13] , chanx_left_in[0] , 
+        chanx_right_out[3] , chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size12_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_2 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_right_in[3] , chanx_left_out[5] , chanx_left_out[14] , 
+        chany_top_out[5] , chany_top_out[14] , chanx_right_out[5] , 
+        chanx_right_out[14] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size12_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chany_top_out[1] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_0 (
+    .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chany_top_in[19] , 
+        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_top_out[3] , chany_top_out[13] , chany_bottom_in[15] , 
+        chanx_right_out[3] , chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size12_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 (
+    .in ( { chany_top_in[0] , chany_bottom_out[5] , chany_bottom_out[14] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_top_out[5] , chany_bottom_in[11] , chany_top_out[14] , 
+        chanx_right_out[5] , chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size12_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 (
+    .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_left_out[3] , 
+        chanx_left_out[13] , chanx_right_in[15] , 
+        bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_left_in[1] , chanx_right_out[3] , chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size12_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_left_out[5] , 
+        chanx_right_in[11] , chanx_left_out[14] , 
+        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , 
+        bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , 
+        chanx_left_in[3] , chanx_right_out[5] , chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size12_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_1 (
+    .in ( { chany_top_in[0] , chany_bottom_out[3] , chany_bottom_out[13] , 
+        chanx_left_out[3] , chanx_left_out[13] , chany_top_out[3] , 
+        chany_top_out[13] , chany_bottom_in[19] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size12_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_104 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chany_top_in[19] , 
+        chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , 
+        chany_top_out[5] , chany_top_out[14] , left_bottom_grid_pin_35_[0] , 
+        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size12_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_105 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_0 mux_top_track_4 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , 
+        top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , 
+        top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , 
+        chanx_left_out[6] , chanx_right_in[7] , chanx_left_out[15] , 
+        chany_top_out[6] , chany_top_out[15] , chanx_right_out[6] , 
+        chanx_right_out[15] , chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size16_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , 
+        SYNOPSYS_UNCONNECTED_37 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_1 mux_right_track_4 (
+    .in ( { chany_top_in[1] , chany_bottom_out[6] , chany_bottom_out[15] , 
+        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , 
+        right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] , 
+        right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_top_out[6] , chany_bottom_in[7] , chany_top_out[15] , 
+        chanx_right_out[6] , chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size16_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , 
+        SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , 
+        SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_2 mux_bottom_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_left_out[6] , 
+        chanx_right_in[7] , chanx_left_out[15] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , 
+        bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_right_out[6] , chanx_left_in[7] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size16_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , 
+        SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16 mux_left_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chany_top_in[15] , 
+        chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] , 
+        chany_top_out[6] , chany_top_out[15] , left_bottom_grid_pin_34_[0] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_38_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size16_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , 
+        SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , 
+        SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_105 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size16_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size16_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size16_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem mem_left_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size16_3_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_0 mux_top_track_8 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , 
+        chanx_left_out[7] , chanx_right_in[11] , chanx_left_out[17] , 
+        chany_top_out[7] , chany_top_out[17] , chanx_right_out[7] , 
+        chanx_left_in[11] , chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_16 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , 
+        chanx_left_out[9] , chanx_right_in[15] , chanx_left_out[18] , 
+        chany_top_out[9] , chany_top_out[18] , chanx_left_in[7] , 
+        chanx_right_out[9] , chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( chany_top_out[8] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 (
+    .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , 
+        chanx_left_out[10] , chanx_left_out[19] , chanx_right_in[19] , 
+        chany_top_out[10] , chany_top_out[19] , chanx_left_in[3] , 
+        chanx_right_out[10] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_8 (
+    .in ( { chany_top_in[3] , chany_bottom_out[7] , chany_bottom_out[17] , 
+        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , 
+        chany_bottom_in[3] , chany_top_out[7] , chany_top_out[17] , 
+        chanx_right_out[7] , chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
+        SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_16 (
+    .in ( { chany_top_in[7] , chany_bottom_out[9] , chany_bottom_out[18] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , 
+        chany_bottom_in[1] , chany_top_out[9] , chany_top_out[18] , 
+        chanx_right_out[9] , chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , 
+        SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 (
+    .in ( { chany_bottom_out[10] , chany_top_in[11] , chany_bottom_out[19] , 
+        right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[0] , chany_top_out[10] , chany_top_out[19] , 
+        chanx_right_out[10] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , 
+        SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_107 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_9 (
+    .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[3] , 
+        chanx_left_out[7] , chanx_left_out[17] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_46_[0] , chanx_right_out[7] , chanx_left_in[11] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , 
+        SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_7 mux_bottom_track_17 (
+    .in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] , 
+        chanx_left_out[9] , chanx_left_out[18] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_47_[0] , chanx_right_out[9] , chanx_left_in[15] , 
+        chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , 
+        SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_25 (
+    .in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] , 
+        chanx_left_out[10] , chanx_left_out[19] , 
+        bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_right_out[10] , chanx_right_out[19] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , 
+        SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_9 (
+    .in ( { chany_bottom_out[7] , chany_top_in[11] , chany_bottom_out[17] , 
+        chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[3] , 
+        chany_top_out[7] , chany_top_out[17] , left_bottom_grid_pin_34_[0] , 
+        left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size10_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , 
+        SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_17 (
+    .in ( { chany_top_in[7] , chany_bottom_out[9] , chany_bottom_out[18] , 
+        chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[7] , 
+        chany_top_out[9] , chany_top_out[18] , left_bottom_grid_pin_35_[0] , 
+        left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size10_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , 
+        SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_104 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 (
+    .in ( { chany_top_in[3] , chany_bottom_out[10] , chany_bottom_out[19] , 
+        chanx_left_out[10] , chanx_left_out[19] , chany_top_out[10] , 
+        chany_bottom_in[11] , chany_top_out[19] , 
+        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size10_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , 
+        SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_104 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_left_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_0 mux_top_track_32 (
+    .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , 
+        chanx_right_in[0] , chanx_left_out[11] , chany_top_out[11] , 
+        chanx_left_in[1] , chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , 
+        SYNOPSYS_UNCONNECTED_103 } ) ,
+    .out ( chany_top_out[16] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 (
+    .in ( { chany_bottom_out[11] , chany_top_in[15] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_top_out[11] , chany_bottom_in[19] , chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , 
+        SYNOPSYS_UNCONNECTED_106 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_2 mux_bottom_track_33 (
+    .in ( { chany_bottom_out[11] , chanx_left_out[11] , chanx_right_in[19] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , 
+        chanx_left_in[0] , chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 , 
+        SYNOPSYS_UNCONNECTED_109 } ) ,
+    .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7 mux_left_track_33 (
+    .in ( { chany_top_in[1] , chany_bottom_out[11] , chanx_left_out[11] , 
+        chany_top_out[11] , chany_bottom_in[15] , 
+        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , 
+        SYNOPSYS_UNCONNECTED_112 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_105 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sky130_fd_sc_hd__buf_6 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , 
+    .X ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , 
+    .HI ( optlc_net_102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , 
+    .HI ( optlc_net_103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_115 ) , 
+    .HI ( optlc_net_104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_116 ) , 
+    .HI ( optlc_net_105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , 
+    .HI ( optlc_net_106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , 
+    .HI ( optlc_net_107 ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.top_only.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..1a1df73
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.top_only.pt.v
@@ -0,0 +1,746 @@
+//
+//
+//
+//
+//
+//
+module sb_1__1_ ( chany_top_in , top_left_grid_pin_42_ , 
+    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
+    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
+    top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ , 
+    right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ , 
+    right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , 
+    right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , 
+    right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ , 
+    bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , 
+    bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , 
+    bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , 
+    bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , 
+    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
+    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
+    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
+    left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , 
+    chany_bottom_out , chanx_left_out , ccff_tail , Test_en_S_in , 
+    Test_en_N_out , prog_clk_0_N_in , prog_clk_1_N_in , prog_clk_1_S_in , 
+    prog_clk_1_E_out , prog_clk_1_W_out , prog_clk_2_N_in , prog_clk_2_E_in , 
+    prog_clk_2_S_in , prog_clk_2_W_in , prog_clk_2_W_out , prog_clk_2_S_out , 
+    prog_clk_2_N_out , prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , 
+    prog_clk_3_S_in , prog_clk_3_N_in , prog_clk_3_E_out , prog_clk_3_W_out , 
+    prog_clk_3_N_out , prog_clk_3_S_out , clk_1_N_in , clk_1_S_in , 
+    clk_1_E_out , clk_1_W_out , clk_2_N_in , clk_2_E_in , clk_2_S_in , 
+    clk_2_W_in , clk_2_W_out , clk_2_S_out , clk_2_N_out , clk_2_E_out , 
+    clk_3_W_in , clk_3_E_in , clk_3_S_in , clk_3_N_in , clk_3_E_out , 
+    clk_3_W_out , clk_3_N_out , clk_3_S_out ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_42_ ;
+input  [0:0] top_left_grid_pin_43_ ;
+input  [0:0] top_left_grid_pin_44_ ;
+input  [0:0] top_left_grid_pin_45_ ;
+input  [0:0] top_left_grid_pin_46_ ;
+input  [0:0] top_left_grid_pin_47_ ;
+input  [0:0] top_left_grid_pin_48_ ;
+input  [0:0] top_left_grid_pin_49_ ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_bottom_grid_pin_34_ ;
+input  [0:0] right_bottom_grid_pin_35_ ;
+input  [0:0] right_bottom_grid_pin_36_ ;
+input  [0:0] right_bottom_grid_pin_37_ ;
+input  [0:0] right_bottom_grid_pin_38_ ;
+input  [0:0] right_bottom_grid_pin_39_ ;
+input  [0:0] right_bottom_grid_pin_40_ ;
+input  [0:0] right_bottom_grid_pin_41_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_left_grid_pin_42_ ;
+input  [0:0] bottom_left_grid_pin_43_ ;
+input  [0:0] bottom_left_grid_pin_44_ ;
+input  [0:0] bottom_left_grid_pin_45_ ;
+input  [0:0] bottom_left_grid_pin_46_ ;
+input  [0:0] bottom_left_grid_pin_47_ ;
+input  [0:0] bottom_left_grid_pin_48_ ;
+input  [0:0] bottom_left_grid_pin_49_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_bottom_grid_pin_34_ ;
+input  [0:0] left_bottom_grid_pin_35_ ;
+input  [0:0] left_bottom_grid_pin_36_ ;
+input  [0:0] left_bottom_grid_pin_37_ ;
+input  [0:0] left_bottom_grid_pin_38_ ;
+input  [0:0] left_bottom_grid_pin_39_ ;
+input  [0:0] left_bottom_grid_pin_40_ ;
+input  [0:0] left_bottom_grid_pin_41_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  Test_en_S_in ;
+output Test_en_N_out ;
+input  prog_clk_0_N_in ;
+input  prog_clk_1_N_in ;
+input  prog_clk_1_S_in ;
+output prog_clk_1_E_out ;
+output prog_clk_1_W_out ;
+input  prog_clk_2_N_in ;
+input  prog_clk_2_E_in ;
+input  prog_clk_2_S_in ;
+input  prog_clk_2_W_in ;
+output prog_clk_2_W_out ;
+output prog_clk_2_S_out ;
+output prog_clk_2_N_out ;
+output prog_clk_2_E_out ;
+input  prog_clk_3_W_in ;
+input  prog_clk_3_E_in ;
+input  prog_clk_3_S_in ;
+input  prog_clk_3_N_in ;
+output prog_clk_3_E_out ;
+output prog_clk_3_W_out ;
+output prog_clk_3_N_out ;
+output prog_clk_3_S_out ;
+input  clk_1_N_in ;
+input  clk_1_S_in ;
+output clk_1_E_out ;
+output clk_1_W_out ;
+input  clk_2_N_in ;
+input  clk_2_E_in ;
+input  clk_2_S_in ;
+input  clk_2_W_in ;
+output clk_2_W_out ;
+output clk_2_S_out ;
+output clk_2_N_out ;
+output clk_2_E_out ;
+input  clk_3_W_in ;
+input  clk_3_E_in ;
+input  clk_3_S_in ;
+input  clk_3_N_in ;
+output clk_3_E_out ;
+output clk_3_W_out ;
+output clk_3_N_out ;
+output clk_3_S_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_10_sram ;
+wire [0:3] mux_tree_tapbuf_size10_11_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:3] mux_tree_tapbuf_size10_9_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size12_0_sram ;
+wire [0:3] mux_tree_tapbuf_size12_1_sram ;
+wire [0:3] mux_tree_tapbuf_size12_2_sram ;
+wire [0:3] mux_tree_tapbuf_size12_3_sram ;
+wire [0:3] mux_tree_tapbuf_size12_4_sram ;
+wire [0:3] mux_tree_tapbuf_size12_5_sram ;
+wire [0:3] mux_tree_tapbuf_size12_6_sram ;
+wire [0:3] mux_tree_tapbuf_size12_7_sram ;
+wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
+wire [0:4] mux_tree_tapbuf_size16_0_sram ;
+wire [0:4] mux_tree_tapbuf_size16_1_sram ;
+wire [0:4] mux_tree_tapbuf_size16_2_sram ;
+wire [0:4] mux_tree_tapbuf_size16_3_sram ;
+wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+
+assign prog_clk_1_E_out = prog_clk_1_S_in ;
+assign prog_clk_1_W_out = prog_clk_1_S_in ;
+assign prog_clk_2_W_out = prog_clk_2_W_in ;
+assign prog_clk_2_S_out = prog_clk_2_W_in ;
+assign prog_clk_2_N_out = prog_clk_2_W_in ;
+assign prog_clk_2_E_out = prog_clk_2_W_in ;
+assign prog_clk_3_E_out = prog_clk_3_N_in ;
+assign prog_clk_3_W_out = prog_clk_3_N_in ;
+assign prog_clk_3_N_out = prog_clk_3_N_in ;
+assign prog_clk_3_S_out = prog_clk_3_N_in ;
+assign clk_1_E_out = clk_1_S_in ;
+assign clk_1_W_out = clk_1_S_in ;
+assign clk_2_W_out = clk_2_W_in ;
+assign clk_2_S_out = clk_2_W_in ;
+assign clk_2_N_out = clk_2_W_in ;
+assign clk_2_E_out = clk_2_W_in ;
+assign clk_3_E_out = clk_3_N_in ;
+assign clk_3_W_out = clk_3_N_in ;
+assign clk_3_N_out = clk_3_N_in ;
+assign clk_3_S_out = clk_3_N_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_1_S_in = prog_clk_1_N_in ;
+assign prog_clk_2_N_in = prog_clk_2_W_in ;
+assign prog_clk_2_S_in = prog_clk_2_W_in ;
+assign prog_clk_3_W_in = prog_clk_3_N_in ;
+assign prog_clk_3_S_in = prog_clk_3_N_in ;
+assign clk_1_S_in = clk_1_N_in ;
+assign clk_2_N_in = clk_2_W_in ;
+assign clk_2_S_in = clk_2_W_in ;
+assign clk_3_W_in = clk_3_N_in ;
+assign clk_3_S_in = clk_3_N_in ;
+assign prog_clk_2_E_in = prog_clk_2_W_in ;
+assign prog_clk_3_E_in = prog_clk_3_N_in ;
+assign clk_2_E_in = clk_2_W_in ;
+assign clk_3_E_in = clk_3_N_in ;
+
+sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        chanx_right_in[1] , chanx_left_out[3] , chanx_left_out[13] , 
+        chany_top_out[3] , chany_top_out[13] , chanx_left_in[0] , 
+        chanx_right_out[3] , chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size12_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_2 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_right_in[3] , chanx_left_out[5] , chanx_left_out[14] , 
+        chany_top_out[5] , chany_top_out[14] , chanx_right_out[5] , 
+        chanx_right_out[14] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size12_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chany_top_out[1] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_0 (
+    .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chany_top_in[19] , 
+        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_top_out[3] , chany_top_out[13] , chany_bottom_in[15] , 
+        chanx_right_out[3] , chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size12_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 (
+    .in ( { chany_top_in[0] , chany_bottom_out[5] , chany_bottom_out[14] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_top_out[5] , chany_bottom_in[11] , chany_top_out[14] , 
+        chanx_right_out[5] , chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size12_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 (
+    .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_left_out[3] , 
+        chanx_left_out[13] , chanx_right_in[15] , 
+        bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_left_in[1] , chanx_right_out[3] , chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size12_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_left_out[5] , 
+        chanx_right_in[11] , chanx_left_out[14] , 
+        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , 
+        bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , 
+        chanx_left_in[3] , chanx_right_out[5] , chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size12_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_1 (
+    .in ( { chany_top_in[0] , chany_bottom_out[3] , chany_bottom_out[13] , 
+        chanx_left_out[3] , chanx_left_out[13] , chany_top_out[3] , 
+        chany_top_out[13] , chany_bottom_in[19] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size12_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_104 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chany_top_in[19] , 
+        chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , 
+        chany_top_out[5] , chany_top_out[14] , left_bottom_grid_pin_35_[0] , 
+        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size12_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_105 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_0 mux_top_track_4 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , 
+        top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , 
+        top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , 
+        chanx_left_out[6] , chanx_right_in[7] , chanx_left_out[15] , 
+        chany_top_out[6] , chany_top_out[15] , chanx_right_out[6] , 
+        chanx_right_out[15] , chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size16_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , 
+        SYNOPSYS_UNCONNECTED_37 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_1 mux_right_track_4 (
+    .in ( { chany_top_in[1] , chany_bottom_out[6] , chany_bottom_out[15] , 
+        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , 
+        right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] , 
+        right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_top_out[6] , chany_bottom_in[7] , chany_top_out[15] , 
+        chanx_right_out[6] , chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size16_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , 
+        SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , 
+        SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_2 mux_bottom_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_left_out[6] , 
+        chanx_right_in[7] , chanx_left_out[15] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , 
+        bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_right_out[6] , chanx_left_in[7] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size16_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , 
+        SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16 mux_left_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chany_top_in[15] , 
+        chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] , 
+        chany_top_out[6] , chany_top_out[15] , left_bottom_grid_pin_34_[0] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_38_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size16_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , 
+        SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , 
+        SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_105 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size16_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size16_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size16_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem mem_left_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size16_3_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_0 mux_top_track_8 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , 
+        chanx_left_out[7] , chanx_right_in[11] , chanx_left_out[17] , 
+        chany_top_out[7] , chany_top_out[17] , chanx_right_out[7] , 
+        chanx_left_in[11] , chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_16 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , 
+        chanx_left_out[9] , chanx_right_in[15] , chanx_left_out[18] , 
+        chany_top_out[9] , chany_top_out[18] , chanx_left_in[7] , 
+        chanx_right_out[9] , chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( chany_top_out[8] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 (
+    .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , 
+        chanx_left_out[10] , chanx_left_out[19] , chanx_right_in[19] , 
+        chany_top_out[10] , chany_top_out[19] , chanx_left_in[3] , 
+        chanx_right_out[10] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_8 (
+    .in ( { chany_top_in[3] , chany_bottom_out[7] , chany_bottom_out[17] , 
+        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , 
+        chany_bottom_in[3] , chany_top_out[7] , chany_top_out[17] , 
+        chanx_right_out[7] , chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
+        SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_16 (
+    .in ( { chany_top_in[7] , chany_bottom_out[9] , chany_bottom_out[18] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , 
+        chany_bottom_in[1] , chany_top_out[9] , chany_top_out[18] , 
+        chanx_right_out[9] , chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , 
+        SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 (
+    .in ( { chany_bottom_out[10] , chany_top_in[11] , chany_bottom_out[19] , 
+        right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[0] , chany_top_out[10] , chany_top_out[19] , 
+        chanx_right_out[10] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , 
+        SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_107 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_9 (
+    .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[3] , 
+        chanx_left_out[7] , chanx_left_out[17] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_46_[0] , chanx_right_out[7] , chanx_left_in[11] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , 
+        SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_7 mux_bottom_track_17 (
+    .in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] , 
+        chanx_left_out[9] , chanx_left_out[18] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_47_[0] , chanx_right_out[9] , chanx_left_in[15] , 
+        chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , 
+        SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_25 (
+    .in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] , 
+        chanx_left_out[10] , chanx_left_out[19] , 
+        bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_right_out[10] , chanx_right_out[19] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , 
+        SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_9 (
+    .in ( { chany_bottom_out[7] , chany_top_in[11] , chany_bottom_out[17] , 
+        chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[3] , 
+        chany_top_out[7] , chany_top_out[17] , left_bottom_grid_pin_34_[0] , 
+        left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size10_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , 
+        SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_17 (
+    .in ( { chany_top_in[7] , chany_bottom_out[9] , chany_bottom_out[18] , 
+        chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[7] , 
+        chany_top_out[9] , chany_top_out[18] , left_bottom_grid_pin_35_[0] , 
+        left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size10_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , 
+        SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_104 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 (
+    .in ( { chany_top_in[3] , chany_bottom_out[10] , chany_bottom_out[19] , 
+        chanx_left_out[10] , chanx_left_out[19] , chany_top_out[10] , 
+        chany_bottom_in[11] , chany_top_out[19] , 
+        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size10_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , 
+        SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_104 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_left_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_0 mux_top_track_32 (
+    .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , 
+        chanx_right_in[0] , chanx_left_out[11] , chany_top_out[11] , 
+        chanx_left_in[1] , chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , 
+        SYNOPSYS_UNCONNECTED_103 } ) ,
+    .out ( chany_top_out[16] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 (
+    .in ( { chany_bottom_out[11] , chany_top_in[15] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , 
+        chany_top_out[11] , chany_bottom_in[19] , chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , 
+        SYNOPSYS_UNCONNECTED_106 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_2 mux_bottom_track_33 (
+    .in ( { chany_bottom_out[11] , chanx_left_out[11] , chanx_right_in[19] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , 
+        chanx_left_in[0] , chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 , 
+        SYNOPSYS_UNCONNECTED_109 } ) ,
+    .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7 mux_left_track_33 (
+    .in ( { chany_top_in[1] , chany_bottom_out[11] , chanx_left_out[11] , 
+        chany_top_out[11] , chany_bottom_in[15] , 
+        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , 
+        SYNOPSYS_UNCONNECTED_112 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_105 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sky130_fd_sc_hd__buf_6 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , 
+    .X ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , 
+    .HI ( optlc_net_102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , 
+    .HI ( optlc_net_103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_115 ) , 
+    .HI ( optlc_net_104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_116 ) , 
+    .HI ( optlc_net_105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , 
+    .HI ( optlc_net_106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , 
+    .HI ( optlc_net_107 ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v
new file mode 100644
index 0000000..34c6fbb
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v
@@ -0,0 +1,2439 @@
+//
+//
+//
+//
+//
+//
+module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+wire copt_net_105 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_104 ) , 
+    .X ( copt_net_100 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_105 ) , 
+    .X ( copt_net_101 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_103 ) , 
+    .X ( copt_net_102 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_101 ) , 
+    .X ( copt_net_103 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_102 ) , 
+    .X ( copt_net_104 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_100 ) , 
+    .X ( mem_out[2] ) ) ;
+endmodule
+
+
+module sb_1__2__const1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_1__2__const1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_26 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_1__2__const1_26 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_25 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_1__2__const1_25 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_24 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_1__2__const1_24 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_80 ) ) ;
+endmodule
+
+
+module sb_1__2__const1_23 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_1__2__const1_23 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_78 ) ) ;
+endmodule
+
+
+module sb_1__2__const1_22 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_1__2__const1_22 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_21 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_1__2__const1_21 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_20 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_1__2__const1_20 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_19 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sb_1__2__const1_19 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_18 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sb_1__2__const1_18 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_17 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sb_1__2__const1_17 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_16 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_1__2__const1_16 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_76 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_15 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__2__const1_15 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_74 ) ) ;
+endmodule
+
+
+module sb_1__2__const1_14 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__2__const1_14 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_13 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__2__const1_13 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_72 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_12 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__2__const1_12 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_11 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__2__const1_11 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_86 ) ) ;
+endmodule
+
+
+module sb_1__2__const1_10 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__2__const1_10 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_9 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__2__const1_9 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_8 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_1__2__const1_8 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_7 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sb_1__2__const1_7 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .Y ( BUF_net_68 ) ) ;
+endmodule
+
+
+module sb_1__2__const1_6 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sb_1__2__const1_6 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_5 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__2__const1_5 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , 
+    .Y ( BUF_net_66 ) ) ;
+endmodule
+
+
+module sb_1__2__const1_4 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__2__const1_4 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__const1_3 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sb_1__2__const1_3 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .Y ( BUF_net_64 ) ) ;
+endmodule
+
+
+module sb_1__2__const1_2 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sb_1__2__const1_2 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .Y ( BUF_net_62 ) ) ;
+endmodule
+
+
+module sb_1__2__const1_1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sb_1__2__const1_1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_99 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1275 ( .A ( copt_net_96 ) , 
+    .X ( copt_net_94 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_97 ) , 
+    .X ( copt_net_95 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_96 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , 
+    .X ( copt_net_97 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_94 ) , 
+    .X ( copt_net_98 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_95 ) , 
+    .X ( copt_net_99 ) ) ;
+endmodule
+
+
+module sb_1__2__const1_0 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_1__2__const1_0 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2_ ( chanx_right_in , right_top_grid_pin_1_ , 
+    right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , 
+    right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , 
+    right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , 
+    right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , 
+    bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , 
+    bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , 
+    bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , 
+    bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , 
+    left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , 
+    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
+    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
+    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
+    left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , 
+    chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_BOT , SC_OUT_BOT , 
+    prog_clk_0_S_in ) ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_top_grid_pin_1_ ;
+input  [0:0] right_bottom_grid_pin_34_ ;
+input  [0:0] right_bottom_grid_pin_35_ ;
+input  [0:0] right_bottom_grid_pin_36_ ;
+input  [0:0] right_bottom_grid_pin_37_ ;
+input  [0:0] right_bottom_grid_pin_38_ ;
+input  [0:0] right_bottom_grid_pin_39_ ;
+input  [0:0] right_bottom_grid_pin_40_ ;
+input  [0:0] right_bottom_grid_pin_41_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_left_grid_pin_42_ ;
+input  [0:0] bottom_left_grid_pin_43_ ;
+input  [0:0] bottom_left_grid_pin_44_ ;
+input  [0:0] bottom_left_grid_pin_45_ ;
+input  [0:0] bottom_left_grid_pin_46_ ;
+input  [0:0] bottom_left_grid_pin_47_ ;
+input  [0:0] bottom_left_grid_pin_48_ ;
+input  [0:0] bottom_left_grid_pin_49_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_top_grid_pin_1_ ;
+input  [0:0] left_bottom_grid_pin_34_ ;
+input  [0:0] left_bottom_grid_pin_35_ ;
+input  [0:0] left_bottom_grid_pin_36_ ;
+input  [0:0] left_bottom_grid_pin_37_ ;
+input  [0:0] left_bottom_grid_pin_38_ ;
+input  [0:0] left_bottom_grid_pin_39_ ;
+input  [0:0] left_bottom_grid_pin_40_ ;
+input  [0:0] left_bottom_grid_pin_41_ ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  SC_IN_BOT ;
+output SC_OUT_BOT ;
+input  prog_clk_0_S_in ;
+
+wire ropt_net_115 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size14_0_sram ;
+wire [0:3] mux_tree_tapbuf_size14_1_sram ;
+wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:1] mux_tree_tapbuf_size3_5_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:2] mux_tree_tapbuf_size7_7_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:3] mux_tree_tapbuf_size9_1_sram ;
+wire [0:3] mux_tree_tapbuf_size9_2_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , 
+        chany_bottom_in[12] , chany_bottom_in[19] , chanx_right_out[3] , 
+        chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_91 ) ) ;
+sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_2 (
+    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , 
+        chanx_right_out[5] , chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_91 ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 (
+    .in ( { chanx_left_out[3] , chanx_left_out[13] , chany_bottom_in[6] , 
+        chany_bottom_in[13] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size9_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 (
+    .in ( { chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , 
+        chany_bottom_in[7] , chany_bottom_in[14] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size9_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_mem mem_left_track_3 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size14_0 mux_right_track_4 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , 
+        right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[3] , 
+        chany_bottom_in[10] , chany_bottom_in[17] , chanx_right_out[6] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size14_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 (
+    .in ( { chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] , 
+        chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , 
+        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , 
+        left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size14_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_92 ) ) ;
+sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size14_mem mem_left_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_8 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , 
+        chany_bottom_in[9] , chany_bottom_in[16] , chanx_right_out[7] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 (
+    .in ( { chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[2] , 
+        chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_16 (
+    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , 
+        chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , 
+        chanx_right_out[9] , chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 (
+    .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , 
+        chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , 
+        chanx_right_out[10] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , 
+        SYNOPSYS_UNCONNECTED_38 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 (
+    .in ( { chanx_left_out[3] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , 
+        bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_right_out[3] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 , 
+        SYNOPSYS_UNCONNECTED_41 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_92 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 (
+    .in ( { chanx_left_out[5] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_right_out[5] } ) ,
+    .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , 
+        SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 (
+    .in ( { chanx_left_out[6] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , 
+        bottom_left_grid_pin_48_[0] , chanx_right_out[6] , chanx_left_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_92 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 (
+    .in ( { chanx_left_out[7] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_right_out[7] , chanx_left_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , 
+        SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 (
+    .in ( { chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[3] , 
+        chany_bottom_in[10] , chany_bottom_in[17] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 , 
+        SYNOPSYS_UNCONNECTED_53 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 (
+    .in ( { chanx_left_out[10] , chanx_left_out[19] , chany_bottom_in[4] , 
+        chany_bottom_in[11] , chany_bottom_in[18] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , 
+        SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_bottom_track_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 (
+    .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[6] , chany_bottom_in[13] , chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_9 (
+    .in ( { chanx_left_out[9] , bottom_left_grid_pin_42_[0] , 
+        chanx_right_out[9] , chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , 
+        SYNOPSYS_UNCONNECTED_62 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_11 (
+    .in ( { chanx_left_out[10] , bottom_left_grid_pin_43_[0] , 
+        chanx_right_out[10] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , 
+        SYNOPSYS_UNCONNECTED_65 } ) ,
+    .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_25 (
+    .in ( { chanx_left_out[19] , chanx_right_in[19] , 
+        bottom_left_grid_pin_42_[0] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , 
+        SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 (
+    .in ( { chanx_left_out[11] , bottom_left_grid_pin_44_[0] , 
+        chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+    .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 (
+    .in ( { chanx_left_out[13] , bottom_left_grid_pin_45_[0] , 
+        chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 (
+    .in ( { chanx_left_out[14] , bottom_left_grid_pin_46_[0] , 
+        chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 (
+    .in ( { chanx_left_out[15] , bottom_left_grid_pin_47_[0] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 (
+    .in ( { chanx_left_out[17] , bottom_left_grid_pin_48_[0] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 (
+    .in ( { chanx_left_out[18] , bottom_left_grid_pin_49_[0] , 
+        chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size3_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+    .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 (
+    .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+    .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 (
+    .in ( { chanx_left_out[11] , chany_bottom_in[5] , chany_bottom_in[12] , 
+        chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , 
+        SYNOPSYS_UNCONNECTED_85 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ropt_net_134 } ) ,
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[0] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[1] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[3] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[7] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[11] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[0] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , 
+    .HI ( optlc_net_88 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , 
+    .HI ( optlc_net_89 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , 
+    .HI ( optlc_net_90 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , 
+    .HI ( optlc_net_91 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , 
+    .HI ( optlc_net_92 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , 
+    .HI ( optlc_net_93 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1314 ( .A ( ropt_net_134 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_115 ) , 
+    .X ( SC_OUT_BOT ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v
new file mode 100644
index 0000000..1a9debc
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v
@@ -0,0 +1,2596 @@
+//
+//
+//
+//
+//
+//
+module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+wire copt_net_105 ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_105 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_104 ) , 
+    .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_105 ) , 
+    .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_103 ) , 
+    .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_101 ) , 
+    .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_102 ) , 
+    .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_100 ) , 
+    .X ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_72 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , 
+    .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_99 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1275 ( .A ( copt_net_96 ) , 
+    .X ( copt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_97 ) , 
+    .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , 
+    .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_94 ) , 
+    .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_95 ) , 
+    .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_1__2_ ( chanx_right_in , right_top_grid_pin_1_ , 
+    right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , 
+    right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , 
+    right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , 
+    right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , 
+    bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , 
+    bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , 
+    bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , 
+    bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , 
+    left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , 
+    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
+    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
+    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
+    left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , 
+    chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_BOT , SC_OUT_BOT , 
+    prog_clk_0_S_in , VDD , VSS ) ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_top_grid_pin_1_ ;
+input  [0:0] right_bottom_grid_pin_34_ ;
+input  [0:0] right_bottom_grid_pin_35_ ;
+input  [0:0] right_bottom_grid_pin_36_ ;
+input  [0:0] right_bottom_grid_pin_37_ ;
+input  [0:0] right_bottom_grid_pin_38_ ;
+input  [0:0] right_bottom_grid_pin_39_ ;
+input  [0:0] right_bottom_grid_pin_40_ ;
+input  [0:0] right_bottom_grid_pin_41_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_left_grid_pin_42_ ;
+input  [0:0] bottom_left_grid_pin_43_ ;
+input  [0:0] bottom_left_grid_pin_44_ ;
+input  [0:0] bottom_left_grid_pin_45_ ;
+input  [0:0] bottom_left_grid_pin_46_ ;
+input  [0:0] bottom_left_grid_pin_47_ ;
+input  [0:0] bottom_left_grid_pin_48_ ;
+input  [0:0] bottom_left_grid_pin_49_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_top_grid_pin_1_ ;
+input  [0:0] left_bottom_grid_pin_34_ ;
+input  [0:0] left_bottom_grid_pin_35_ ;
+input  [0:0] left_bottom_grid_pin_36_ ;
+input  [0:0] left_bottom_grid_pin_37_ ;
+input  [0:0] left_bottom_grid_pin_38_ ;
+input  [0:0] left_bottom_grid_pin_39_ ;
+input  [0:0] left_bottom_grid_pin_40_ ;
+input  [0:0] left_bottom_grid_pin_41_ ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  SC_IN_BOT ;
+output SC_OUT_BOT ;
+input  prog_clk_0_S_in ;
+input  VDD ;
+input  VSS ;
+
+wire ropt_net_115 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size14_0_sram ;
+wire [0:3] mux_tree_tapbuf_size14_1_sram ;
+wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:1] mux_tree_tapbuf_size3_5_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:2] mux_tree_tapbuf_size7_7_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:3] mux_tree_tapbuf_size9_1_sram ;
+wire [0:3] mux_tree_tapbuf_size9_2_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , 
+        chany_bottom_in[12] , chany_bottom_in[19] , chanx_right_out[3] , 
+        chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
+sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_2 (
+    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , 
+        chanx_right_out[5] , chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 (
+    .in ( { chanx_left_out[3] , chanx_left_out[13] , chany_bottom_in[6] , 
+        chany_bottom_in[13] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size9_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 (
+    .in ( { chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , 
+        chany_bottom_in[7] , chany_bottom_in[14] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size9_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_mem mem_left_track_3 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size14_0 mux_right_track_4 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , 
+        right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[3] , 
+        chany_bottom_in[10] , chany_bottom_in[17] , chanx_right_out[6] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size14_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 (
+    .in ( { chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] , 
+        chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , 
+        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , 
+        left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size14_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
+sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size14_mem mem_left_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_8 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , 
+        chany_bottom_in[9] , chany_bottom_in[16] , chanx_right_out[7] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 (
+    .in ( { chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[2] , 
+        chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_16 (
+    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , 
+        chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , 
+        chanx_right_out[9] , chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 } ) ,
+    .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 (
+    .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , 
+        chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , 
+        chanx_right_out[10] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , 
+        SYNOPSYS_UNCONNECTED_38 } ) ,
+    .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 (
+    .in ( { chanx_left_out[3] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , 
+        bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_right_out[3] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 , 
+        SYNOPSYS_UNCONNECTED_41 } ) ,
+    .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 (
+    .in ( { chanx_left_out[5] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_right_out[5] } ) ,
+    .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , 
+        SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 (
+    .in ( { chanx_left_out[6] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , 
+        bottom_left_grid_pin_48_[0] , chanx_right_out[6] , chanx_left_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 } ) ,
+    .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 (
+    .in ( { chanx_left_out[7] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_right_out[7] , chanx_left_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , 
+        SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 (
+    .in ( { chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[3] , 
+        chany_bottom_in[10] , chany_bottom_in[17] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 , 
+        SYNOPSYS_UNCONNECTED_53 } ) ,
+    .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 (
+    .in ( { chanx_left_out[10] , chanx_left_out[19] , chany_bottom_in[4] , 
+        chany_bottom_in[11] , chany_bottom_in[18] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , 
+        SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_bottom_track_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 (
+    .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[6] , chany_bottom_in[13] , chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 } ) ,
+    .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_9 (
+    .in ( { chanx_left_out[9] , bottom_left_grid_pin_42_[0] , 
+        chanx_right_out[9] , chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , 
+        SYNOPSYS_UNCONNECTED_62 } ) ,
+    .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_11 (
+    .in ( { chanx_left_out[10] , bottom_left_grid_pin_43_[0] , 
+        chanx_right_out[10] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , 
+        SYNOPSYS_UNCONNECTED_65 } ) ,
+    .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_25 (
+    .in ( { chanx_left_out[19] , chanx_right_in[19] , 
+        bottom_left_grid_pin_42_[0] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , 
+        SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 (
+    .in ( { chanx_left_out[11] , bottom_left_grid_pin_44_[0] , 
+        chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+    .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 (
+    .in ( { chanx_left_out[13] , bottom_left_grid_pin_45_[0] , 
+        chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 (
+    .in ( { chanx_left_out[14] , bottom_left_grid_pin_46_[0] , 
+        chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 (
+    .in ( { chanx_left_out[15] , bottom_left_grid_pin_47_[0] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 (
+    .in ( { chanx_left_out[17] , bottom_left_grid_pin_48_[0] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 (
+    .in ( { chanx_left_out[18] , bottom_left_grid_pin_49_[0] , 
+        chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size3_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+    .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 (
+    .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+    .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 (
+    .in ( { chanx_left_out[11] , chany_bottom_in[5] , chany_bottom_in[12] , 
+        chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , 
+        SYNOPSYS_UNCONNECTED_85 } ) ,
+    .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ropt_net_134 } ) ,
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[0] ) , 
+    .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[1] ) , 
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[3] ) , 
+    .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[7] ) , 
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[11] ) , 
+    .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[0] ) , 
+    .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_115 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , 
+    .HI ( optlc_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , 
+    .HI ( optlc_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , 
+    .HI ( optlc_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , 
+    .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , 
+    .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , 
+    .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1314 ( .A ( ropt_net_134 ) , 
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_115 ) , 
+    .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v
new file mode 100644
index 0000000..8f5e6fb
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v
@@ -0,0 +1,2131 @@
+//
+//
+//
+//
+//
+//
+module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+wire copt_net_105 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_104 ) , 
+    .X ( copt_net_100 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_105 ) , 
+    .X ( copt_net_101 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_103 ) , 
+    .X ( copt_net_102 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_101 ) , 
+    .X ( copt_net_103 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_102 ) , 
+    .X ( copt_net_104 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_100 ) , 
+    .X ( mem_out[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_80 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_78 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_76 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_74 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_72 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_86 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .Y ( BUF_net_68 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , 
+    .Y ( BUF_net_66 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .Y ( BUF_net_64 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .Y ( BUF_net_62 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_99 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1275 ( .A ( copt_net_96 ) , 
+    .X ( copt_net_94 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_97 ) , 
+    .X ( copt_net_95 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_96 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , 
+    .X ( copt_net_97 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_94 ) , 
+    .X ( copt_net_98 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_95 ) , 
+    .X ( copt_net_99 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2_ ( chanx_right_in , right_top_grid_pin_1_ , 
+    right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , 
+    right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , 
+    right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , 
+    right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , 
+    bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , 
+    bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , 
+    bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , 
+    bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , 
+    left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , 
+    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
+    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
+    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
+    left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , 
+    chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_BOT , SC_OUT_BOT , 
+    prog_clk_0_S_in ) ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_top_grid_pin_1_ ;
+input  [0:0] right_bottom_grid_pin_34_ ;
+input  [0:0] right_bottom_grid_pin_35_ ;
+input  [0:0] right_bottom_grid_pin_36_ ;
+input  [0:0] right_bottom_grid_pin_37_ ;
+input  [0:0] right_bottom_grid_pin_38_ ;
+input  [0:0] right_bottom_grid_pin_39_ ;
+input  [0:0] right_bottom_grid_pin_40_ ;
+input  [0:0] right_bottom_grid_pin_41_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_left_grid_pin_42_ ;
+input  [0:0] bottom_left_grid_pin_43_ ;
+input  [0:0] bottom_left_grid_pin_44_ ;
+input  [0:0] bottom_left_grid_pin_45_ ;
+input  [0:0] bottom_left_grid_pin_46_ ;
+input  [0:0] bottom_left_grid_pin_47_ ;
+input  [0:0] bottom_left_grid_pin_48_ ;
+input  [0:0] bottom_left_grid_pin_49_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_top_grid_pin_1_ ;
+input  [0:0] left_bottom_grid_pin_34_ ;
+input  [0:0] left_bottom_grid_pin_35_ ;
+input  [0:0] left_bottom_grid_pin_36_ ;
+input  [0:0] left_bottom_grid_pin_37_ ;
+input  [0:0] left_bottom_grid_pin_38_ ;
+input  [0:0] left_bottom_grid_pin_39_ ;
+input  [0:0] left_bottom_grid_pin_40_ ;
+input  [0:0] left_bottom_grid_pin_41_ ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  SC_IN_BOT ;
+output SC_OUT_BOT ;
+input  prog_clk_0_S_in ;
+
+wire ropt_net_115 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size14_0_sram ;
+wire [0:3] mux_tree_tapbuf_size14_1_sram ;
+wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:1] mux_tree_tapbuf_size3_5_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:2] mux_tree_tapbuf_size7_7_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:3] mux_tree_tapbuf_size9_1_sram ;
+wire [0:3] mux_tree_tapbuf_size9_2_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , 
+        chany_bottom_in[12] , chany_bottom_in[19] , chanx_right_out[3] , 
+        chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_91 ) ) ;
+sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_2 (
+    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , 
+        chanx_right_out[5] , chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_91 ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 (
+    .in ( { chanx_left_out[3] , chanx_left_out[13] , chany_bottom_in[6] , 
+        chany_bottom_in[13] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size9_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 (
+    .in ( { chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , 
+        chany_bottom_in[7] , chany_bottom_in[14] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size9_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_mem mem_left_track_3 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size14_0 mux_right_track_4 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , 
+        right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[3] , 
+        chany_bottom_in[10] , chany_bottom_in[17] , chanx_right_out[6] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size14_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 (
+    .in ( { chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] , 
+        chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , 
+        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , 
+        left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size14_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_92 ) ) ;
+sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size14_mem mem_left_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_8 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , 
+        chany_bottom_in[9] , chany_bottom_in[16] , chanx_right_out[7] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 (
+    .in ( { chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[2] , 
+        chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_16 (
+    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , 
+        chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , 
+        chanx_right_out[9] , chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 (
+    .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , 
+        chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , 
+        chanx_right_out[10] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , 
+        SYNOPSYS_UNCONNECTED_38 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 (
+    .in ( { chanx_left_out[3] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , 
+        bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_right_out[3] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 , 
+        SYNOPSYS_UNCONNECTED_41 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_92 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 (
+    .in ( { chanx_left_out[5] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_right_out[5] } ) ,
+    .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , 
+        SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 (
+    .in ( { chanx_left_out[6] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , 
+        bottom_left_grid_pin_48_[0] , chanx_right_out[6] , chanx_left_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_92 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 (
+    .in ( { chanx_left_out[7] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_right_out[7] , chanx_left_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , 
+        SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 (
+    .in ( { chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[3] , 
+        chany_bottom_in[10] , chany_bottom_in[17] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 , 
+        SYNOPSYS_UNCONNECTED_53 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 (
+    .in ( { chanx_left_out[10] , chanx_left_out[19] , chany_bottom_in[4] , 
+        chany_bottom_in[11] , chany_bottom_in[18] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , 
+        SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_bottom_track_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 (
+    .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[6] , chany_bottom_in[13] , chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_9 (
+    .in ( { chanx_left_out[9] , bottom_left_grid_pin_42_[0] , 
+        chanx_right_out[9] , chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , 
+        SYNOPSYS_UNCONNECTED_62 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_11 (
+    .in ( { chanx_left_out[10] , bottom_left_grid_pin_43_[0] , 
+        chanx_right_out[10] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , 
+        SYNOPSYS_UNCONNECTED_65 } ) ,
+    .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_25 (
+    .in ( { chanx_left_out[19] , chanx_right_in[19] , 
+        bottom_left_grid_pin_42_[0] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , 
+        SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 (
+    .in ( { chanx_left_out[11] , bottom_left_grid_pin_44_[0] , 
+        chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+    .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 (
+    .in ( { chanx_left_out[13] , bottom_left_grid_pin_45_[0] , 
+        chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 (
+    .in ( { chanx_left_out[14] , bottom_left_grid_pin_46_[0] , 
+        chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 (
+    .in ( { chanx_left_out[15] , bottom_left_grid_pin_47_[0] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 (
+    .in ( { chanx_left_out[17] , bottom_left_grid_pin_48_[0] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 (
+    .in ( { chanx_left_out[18] , bottom_left_grid_pin_49_[0] , 
+        chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size3_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+    .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 (
+    .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+    .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 (
+    .in ( { chanx_left_out[11] , chany_bottom_in[5] , chany_bottom_in[12] , 
+        chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , 
+        SYNOPSYS_UNCONNECTED_85 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ropt_net_134 } ) ,
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[0] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[1] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[3] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[7] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[11] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[0] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , 
+    .HI ( optlc_net_88 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , 
+    .HI ( optlc_net_89 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , 
+    .HI ( optlc_net_90 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , 
+    .HI ( optlc_net_91 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , 
+    .HI ( optlc_net_92 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , 
+    .HI ( optlc_net_93 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1314 ( .A ( ropt_net_134 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_115 ) , 
+    .X ( SC_OUT_BOT ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.top_only.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..6f52cd6
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.top_only.pt.v
@@ -0,0 +1,562 @@
+//
+//
+//
+//
+//
+//
+module sb_1__2_ ( chanx_right_in , right_top_grid_pin_1_ , 
+    right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , 
+    right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , 
+    right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , 
+    right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , 
+    bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , 
+    bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , 
+    bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , 
+    bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , 
+    left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , 
+    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
+    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
+    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
+    left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , 
+    chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_BOT , SC_OUT_BOT , 
+    prog_clk_0_S_in ) ;
+input  [0:19] chanx_right_in ;
+input  [0:0] right_top_grid_pin_1_ ;
+input  [0:0] right_bottom_grid_pin_34_ ;
+input  [0:0] right_bottom_grid_pin_35_ ;
+input  [0:0] right_bottom_grid_pin_36_ ;
+input  [0:0] right_bottom_grid_pin_37_ ;
+input  [0:0] right_bottom_grid_pin_38_ ;
+input  [0:0] right_bottom_grid_pin_39_ ;
+input  [0:0] right_bottom_grid_pin_40_ ;
+input  [0:0] right_bottom_grid_pin_41_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_left_grid_pin_42_ ;
+input  [0:0] bottom_left_grid_pin_43_ ;
+input  [0:0] bottom_left_grid_pin_44_ ;
+input  [0:0] bottom_left_grid_pin_45_ ;
+input  [0:0] bottom_left_grid_pin_46_ ;
+input  [0:0] bottom_left_grid_pin_47_ ;
+input  [0:0] bottom_left_grid_pin_48_ ;
+input  [0:0] bottom_left_grid_pin_49_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_top_grid_pin_1_ ;
+input  [0:0] left_bottom_grid_pin_34_ ;
+input  [0:0] left_bottom_grid_pin_35_ ;
+input  [0:0] left_bottom_grid_pin_36_ ;
+input  [0:0] left_bottom_grid_pin_37_ ;
+input  [0:0] left_bottom_grid_pin_38_ ;
+input  [0:0] left_bottom_grid_pin_39_ ;
+input  [0:0] left_bottom_grid_pin_40_ ;
+input  [0:0] left_bottom_grid_pin_41_ ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  SC_IN_BOT ;
+output SC_OUT_BOT ;
+input  prog_clk_0_S_in ;
+
+wire ropt_net_115 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size14_0_sram ;
+wire [0:3] mux_tree_tapbuf_size14_1_sram ;
+wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:1] mux_tree_tapbuf_size3_5_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:2] mux_tree_tapbuf_size7_7_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:3] mux_tree_tapbuf_size9_1_sram ;
+wire [0:3] mux_tree_tapbuf_size9_2_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , 
+        chany_bottom_in[12] , chany_bottom_in[19] , chanx_right_out[3] , 
+        chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_91 ) ) ;
+sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_2 (
+    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , 
+        chanx_right_out[5] , chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_91 ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 (
+    .in ( { chanx_left_out[3] , chanx_left_out[13] , chany_bottom_in[6] , 
+        chany_bottom_in[13] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size9_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 (
+    .in ( { chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , 
+        chany_bottom_in[7] , chany_bottom_in[14] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size9_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_mem mem_left_track_3 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size14_0 mux_right_track_4 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , 
+        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , 
+        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , 
+        right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[3] , 
+        chany_bottom_in[10] , chany_bottom_in[17] , chanx_right_out[6] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size14_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 (
+    .in ( { chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] , 
+        chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , 
+        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , 
+        left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size14_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_92 ) ) ;
+sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size14_mem mem_left_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_8 (
+    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , 
+        right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , 
+        chany_bottom_in[9] , chany_bottom_in[16] , chanx_right_out[7] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 (
+    .in ( { chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[2] , 
+        chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_16 (
+    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , 
+        chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , 
+        chanx_right_out[9] , chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 } ) ,
+    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 (
+    .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , 
+        chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , 
+        chanx_right_out[10] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , 
+        SYNOPSYS_UNCONNECTED_38 } ) ,
+    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 (
+    .in ( { chanx_left_out[3] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , 
+        bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_right_out[3] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 , 
+        SYNOPSYS_UNCONNECTED_41 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_92 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 (
+    .in ( { chanx_left_out[5] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_right_out[5] } ) ,
+    .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , 
+        SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 (
+    .in ( { chanx_left_out[6] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , 
+        bottom_left_grid_pin_48_[0] , chanx_right_out[6] , chanx_left_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_92 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 (
+    .in ( { chanx_left_out[7] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_right_out[7] , chanx_left_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , 
+        SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 (
+    .in ( { chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[3] , 
+        chany_bottom_in[10] , chany_bottom_in[17] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 , 
+        SYNOPSYS_UNCONNECTED_53 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 (
+    .in ( { chanx_left_out[10] , chanx_left_out[19] , chany_bottom_in[4] , 
+        chany_bottom_in[11] , chany_bottom_in[18] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , 
+        SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_right_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_bottom_track_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 (
+    .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , 
+        chany_bottom_in[6] , chany_bottom_in[13] , chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 } ) ,
+    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_90 ) ) ;
+sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_9 (
+    .in ( { chanx_left_out[9] , bottom_left_grid_pin_42_[0] , 
+        chanx_right_out[9] , chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , 
+        SYNOPSYS_UNCONNECTED_62 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_11 (
+    .in ( { chanx_left_out[10] , bottom_left_grid_pin_43_[0] , 
+        chanx_right_out[10] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , 
+        SYNOPSYS_UNCONNECTED_65 } ) ,
+    .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_25 (
+    .in ( { chanx_left_out[19] , chanx_right_in[19] , 
+        bottom_left_grid_pin_42_[0] , chanx_right_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , 
+        SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 (
+    .in ( { chanx_left_out[11] , bottom_left_grid_pin_44_[0] , 
+        chanx_right_out[11] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+    .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 (
+    .in ( { chanx_left_out[13] , bottom_left_grid_pin_45_[0] , 
+        chanx_right_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 (
+    .in ( { chanx_left_out[14] , bottom_left_grid_pin_46_[0] , 
+        chanx_right_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 (
+    .in ( { chanx_left_out[15] , bottom_left_grid_pin_47_[0] , 
+        chanx_right_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 (
+    .in ( { chanx_left_out[17] , bottom_left_grid_pin_48_[0] , 
+        chanx_right_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 (
+    .in ( { chanx_left_out[18] , bottom_left_grid_pin_49_[0] , 
+        chanx_right_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size3_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+    .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 (
+    .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+    .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_89 ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 (
+    .in ( { chanx_left_out[11] , chany_bottom_in[5] , chany_bottom_in[12] , 
+        chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , 
+        SYNOPSYS_UNCONNECTED_85 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_88 ) ) ;
+sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ropt_net_134 } ) ,
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[0] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[1] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[3] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[7] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[11] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[0] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , 
+    .HI ( optlc_net_88 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , 
+    .HI ( optlc_net_89 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , 
+    .HI ( optlc_net_90 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , 
+    .HI ( optlc_net_91 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , 
+    .HI ( optlc_net_92 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , 
+    .HI ( optlc_net_93 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1314 ( .A ( ropt_net_134 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_115 ) , 
+    .X ( SC_OUT_BOT ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v
new file mode 100644
index 0000000..e9e57e7
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v
@@ -0,0 +1,2253 @@
+//
+//
+//
+//
+//
+//
+module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+wire copt_net_97 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_97 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_98 ) , 
+    .X ( copt_net_96 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , 
+    .X ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_97 ) , 
+    .X ( copt_net_98 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_68 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_32 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_32 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_66 ) ) ;
+endmodule
+
+
+module sb_2__0__const1_31 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_31 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_30 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_30 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_29 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_29 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_64 ) ) ;
+endmodule
+
+
+module sb_2__0__const1_28 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_28 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_62 ) ) ;
+endmodule
+
+
+module sb_2__0__const1_27 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_27 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_60 ) ) ;
+endmodule
+
+
+module sb_2__0__const1_26 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_26 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_25 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_25 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_24 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_24 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_57 ) ) ;
+endmodule
+
+
+module sb_2__0__const1_23 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_23 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_22 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_22 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_21 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_21 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_55 ) ) ;
+endmodule
+
+
+module sb_2__0__const1_20 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_20 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_19 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_19 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_18 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_18 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_17 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_17 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_16 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_16 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_15 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_15 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_14 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_14 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_13 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_13 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_12 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__0__const1_12 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_11 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_2__0__const1_11 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_10 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_2__0__const1_10 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_79 ) ) ;
+endmodule
+
+
+module sb_2__0__const1_9 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_2__0__const1_9 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_8 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_2__0__const1_8 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_7 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_2__0__const1_7 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_50 ) ) ;
+endmodule
+
+
+module sb_2__0__const1_6 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_2__0__const1_6 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_48 ) ) ;
+endmodule
+
+
+module sb_2__0__const1_5 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_2__0__const1_5 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_4 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_2__0__const1_4 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_46 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_114 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1250 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_87 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1251 ( .A ( copt_net_89 ) , 
+    .X ( copt_net_88 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_90 ) , 
+    .X ( copt_net_89 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_87 ) , 
+    .X ( copt_net_90 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_92 ) , 
+    .X ( copt_net_91 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_88 ) , 
+    .X ( copt_net_92 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( ropt_net_116 ) , 
+    .X ( ropt_net_114 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( copt_net_91 ) , 
+    .X ( ropt_net_115 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , 
+    .X ( ropt_net_116 ) ) ;
+endmodule
+
+
+module sb_2__0__const1_3 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_2__0__const1_3 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_77 ) ) ;
+endmodule
+
+
+module sb_2__0__const1_2 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_2__0__const1_2 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_43 ) ) ;
+endmodule
+
+
+module sb_2__0__const1_1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_2__0__const1_1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__const1_0 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_2__0__const1_0 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_40 ( .A ( BUF_net_41 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_41 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_41 ) ) ;
+endmodule
+
+
+module sb_2__0_ ( chany_top_in , top_left_grid_pin_42_ , 
+    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
+    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
+    top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in , 
+    left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , 
+    left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , 
+    left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , 
+    left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , 
+    left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_left_out , 
+    ccff_tail , prog_clk_0_N_in ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_42_ ;
+input  [0:0] top_left_grid_pin_43_ ;
+input  [0:0] top_left_grid_pin_44_ ;
+input  [0:0] top_left_grid_pin_45_ ;
+input  [0:0] top_left_grid_pin_46_ ;
+input  [0:0] top_left_grid_pin_47_ ;
+input  [0:0] top_left_grid_pin_48_ ;
+input  [0:0] top_left_grid_pin_49_ ;
+input  [0:0] top_right_grid_pin_1_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_bottom_grid_pin_1_ ;
+input  [0:0] left_bottom_grid_pin_3_ ;
+input  [0:0] left_bottom_grid_pin_5_ ;
+input  [0:0] left_bottom_grid_pin_7_ ;
+input  [0:0] left_bottom_grid_pin_9_ ;
+input  [0:0] left_bottom_grid_pin_11_ ;
+input  [0:0] left_bottom_grid_pin_13_ ;
+input  [0:0] left_bottom_grid_pin_15_ ;
+input  [0:0] left_bottom_grid_pin_17_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  prog_clk_0_N_in ;
+
+wire ropt_net_104 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_18_sram ;
+wire [0:1] mux_tree_tapbuf_size2_19_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_20_sram ;
+wire [0:1] mux_tree_tapbuf_size2_21_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        top_right_grid_pin_1_[0] , chanx_left_in[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        top_right_grid_pin_1_[0] , chanx_left_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , 
+        SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 (
+    .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , 
+        left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , 
+        SYNOPSYS_UNCONNECTED_9 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_83 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 (
+    .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , 
+        left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , 
+        SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem_1 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 } ) ,
+    .out ( chany_top_out[1] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_left_in[17] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , 
+        SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chany_top_out[3] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 (
+    .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , 
+        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , 
+        left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , 
+        SYNOPSYS_UNCONNECTED_21 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_83 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 (
+    .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , 
+        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , 
+        left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , 
+        SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_left_out[3] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem_1 mem_top_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_8 (
+    .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , 
+        chanx_left_in[16] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_24 (
+    .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , 
+        chanx_left_in[8] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_9 (
+    .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3 mux_left_track_25 (
+    .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_2 mem_left_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_10 (
+    .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chany_top_out[5] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_12 (
+    .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chany_top_out[6] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_14 (
+    .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+    .out ( chany_top_out[7] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_16 (
+    .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chany_top_out[8] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_18 (
+    .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chany_top_out[9] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_20 (
+    .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( chany_top_out[10] ) , .p0 ( optlc_net_83 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_22 (
+    .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) ,
+    .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+    .out ( chany_top_out[11] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_26 (
+    .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chany_top_out[13] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_11 (
+    .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chanx_left_out[5] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_13 (
+    .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chanx_left_out[6] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_15 (
+    .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
+    .out ( chanx_left_out[7] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_17 (
+    .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_12 mux_left_track_19 (
+    .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
+    .out ( chanx_left_out[9] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_13 mux_left_track_21 (
+    .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( chanx_left_out[10] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_14 mux_left_track_23 (
+    .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+    .out ( chanx_left_out[11] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_27 (
+    .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( chanx_left_out[13] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_29 (
+    .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
+    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_31 (
+    .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_left_out[15] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_33 (
+    .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_18_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_35 (
+    .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_19_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chanx_left_out[17] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_37 (
+    .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_20_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chanx_left_out[18] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2 mux_left_track_39 (
+    .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_21_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chanx_left_out[19] ) , .p0 ( optlc_net_83 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_26 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_left_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_left_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_left_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_left_track_27 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_left_track_29 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_left_track_31 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_19 mem_left_track_35 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_20 mem_left_track_37 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_39 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_left_in[1] ) , 
+    .X ( ropt_net_104 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_left_in[2] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[3] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[4] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[5] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[6] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , 
+    .HI ( optlc_net_83 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , 
+    .HI ( optlc_net_84 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , 
+    .HI ( optlc_net_85 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , 
+    .HI ( optlc_net_86 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_104 ) , 
+    .X ( chany_top_out[19] ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v
new file mode 100644
index 0000000..9277712
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v
@@ -0,0 +1,2377 @@
+//
+//
+//
+//
+//
+//
+module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+wire copt_net_97 ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_97 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_98 ) , 
+    .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , 
+    .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_97 ) , 
+    .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_46 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_114 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1250 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1251 ( .A ( copt_net_89 ) , 
+    .X ( copt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_90 ) , 
+    .X ( copt_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_87 ) , 
+    .X ( copt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_92 ) , 
+    .X ( copt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_88 ) , 
+    .X ( copt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( ropt_net_116 ) , 
+    .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( copt_net_91 ) , 
+    .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , 
+    .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_43 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_40 ( .A ( BUF_net_41 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_41 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_41 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__0_ ( chany_top_in , top_left_grid_pin_42_ , 
+    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
+    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
+    top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in , 
+    left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , 
+    left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , 
+    left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , 
+    left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , 
+    left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_left_out , 
+    ccff_tail , prog_clk_0_N_in , VDD , VSS ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_42_ ;
+input  [0:0] top_left_grid_pin_43_ ;
+input  [0:0] top_left_grid_pin_44_ ;
+input  [0:0] top_left_grid_pin_45_ ;
+input  [0:0] top_left_grid_pin_46_ ;
+input  [0:0] top_left_grid_pin_47_ ;
+input  [0:0] top_left_grid_pin_48_ ;
+input  [0:0] top_left_grid_pin_49_ ;
+input  [0:0] top_right_grid_pin_1_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_bottom_grid_pin_1_ ;
+input  [0:0] left_bottom_grid_pin_3_ ;
+input  [0:0] left_bottom_grid_pin_5_ ;
+input  [0:0] left_bottom_grid_pin_7_ ;
+input  [0:0] left_bottom_grid_pin_9_ ;
+input  [0:0] left_bottom_grid_pin_11_ ;
+input  [0:0] left_bottom_grid_pin_13_ ;
+input  [0:0] left_bottom_grid_pin_15_ ;
+input  [0:0] left_bottom_grid_pin_17_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  prog_clk_0_N_in ;
+input  VDD ;
+input  VSS ;
+
+wire ropt_net_104 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_18_sram ;
+wire [0:1] mux_tree_tapbuf_size2_19_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_20_sram ;
+wire [0:1] mux_tree_tapbuf_size2_21_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        top_right_grid_pin_1_[0] , chanx_left_in[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 } ) ,
+    .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        top_right_grid_pin_1_[0] , chanx_left_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , 
+        SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 (
+    .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , 
+        left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , 
+        SYNOPSYS_UNCONNECTED_9 } ) ,
+    .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_83 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 (
+    .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , 
+        left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , 
+        SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem_1 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 } ) ,
+    .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_left_in[17] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , 
+        SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 (
+    .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , 
+        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , 
+        left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , 
+        SYNOPSYS_UNCONNECTED_21 } ) ,
+    .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_83 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 (
+    .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , 
+        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , 
+        left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , 
+        SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem_1 mem_top_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_8 (
+    .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , 
+        chanx_left_in[16] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+    .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_24 (
+    .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , 
+        chanx_left_in[8] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_9 (
+    .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3 mux_left_track_25 (
+    .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_2 mem_left_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_10 (
+    .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_12 (
+    .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_14 (
+    .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+    .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_16 (
+    .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_18 (
+    .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_20 (
+    .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_83 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_22 (
+    .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) ,
+    .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+    .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_26 (
+    .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_11 (
+    .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_13 (
+    .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_15 (
+    .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
+    .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_17 (
+    .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_12 mux_left_track_19 (
+    .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
+    .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_13 mux_left_track_21 (
+    .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_14 mux_left_track_23 (
+    .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+    .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_27 (
+    .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_29 (
+    .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
+    .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_31 (
+    .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_33 (
+    .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_18_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+    .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_35 (
+    .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_19_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_37 (
+    .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_20_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2 mux_left_track_39 (
+    .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_21_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_83 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_26 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_left_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_left_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_left_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_left_track_27 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_left_track_29 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_left_track_31 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_19 mem_left_track_35 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_20 mem_left_track_37 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_39 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_21_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_left_in[1] ) , 
+    .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_left_in[2] ) , 
+    .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[3] ) , 
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[4] ) , 
+    .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[5] ) , 
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[6] ) , 
+    .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , 
+    .HI ( optlc_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , 
+    .HI ( optlc_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , 
+    .HI ( optlc_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , 
+    .HI ( optlc_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_104 ) , 
+    .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v
new file mode 100644
index 0000000..ca647ad
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v
@@ -0,0 +1,1879 @@
+//
+//
+//
+//
+//
+//
+module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+wire copt_net_97 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_97 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_98 ) , 
+    .X ( copt_net_96 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , 
+    .X ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_97 ) , 
+    .X ( copt_net_98 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_68 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_66 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_64 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_62 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_60 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_57 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_55 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_79 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_50 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_48 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_46 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_114 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1250 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_87 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1251 ( .A ( copt_net_89 ) , 
+    .X ( copt_net_88 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_90 ) , 
+    .X ( copt_net_89 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_87 ) , 
+    .X ( copt_net_90 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_92 ) , 
+    .X ( copt_net_91 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_88 ) , 
+    .X ( copt_net_92 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( ropt_net_116 ) , 
+    .X ( ropt_net_114 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( copt_net_91 ) , 
+    .X ( ropt_net_115 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , 
+    .X ( ropt_net_116 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_77 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_43 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_40 ( .A ( BUF_net_41 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_41 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_41 ) ) ;
+endmodule
+
+
+module sb_2__0_ ( chany_top_in , top_left_grid_pin_42_ , 
+    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
+    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
+    top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in , 
+    left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , 
+    left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , 
+    left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , 
+    left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , 
+    left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_left_out , 
+    ccff_tail , prog_clk_0_N_in ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_42_ ;
+input  [0:0] top_left_grid_pin_43_ ;
+input  [0:0] top_left_grid_pin_44_ ;
+input  [0:0] top_left_grid_pin_45_ ;
+input  [0:0] top_left_grid_pin_46_ ;
+input  [0:0] top_left_grid_pin_47_ ;
+input  [0:0] top_left_grid_pin_48_ ;
+input  [0:0] top_left_grid_pin_49_ ;
+input  [0:0] top_right_grid_pin_1_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_bottom_grid_pin_1_ ;
+input  [0:0] left_bottom_grid_pin_3_ ;
+input  [0:0] left_bottom_grid_pin_5_ ;
+input  [0:0] left_bottom_grid_pin_7_ ;
+input  [0:0] left_bottom_grid_pin_9_ ;
+input  [0:0] left_bottom_grid_pin_11_ ;
+input  [0:0] left_bottom_grid_pin_13_ ;
+input  [0:0] left_bottom_grid_pin_15_ ;
+input  [0:0] left_bottom_grid_pin_17_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  prog_clk_0_N_in ;
+
+wire ropt_net_104 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_18_sram ;
+wire [0:1] mux_tree_tapbuf_size2_19_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_20_sram ;
+wire [0:1] mux_tree_tapbuf_size2_21_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        top_right_grid_pin_1_[0] , chanx_left_in[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        top_right_grid_pin_1_[0] , chanx_left_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , 
+        SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 (
+    .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , 
+        left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , 
+        SYNOPSYS_UNCONNECTED_9 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_83 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 (
+    .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , 
+        left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , 
+        SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem_1 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 } ) ,
+    .out ( chany_top_out[1] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_left_in[17] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , 
+        SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chany_top_out[3] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 (
+    .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , 
+        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , 
+        left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , 
+        SYNOPSYS_UNCONNECTED_21 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_83 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 (
+    .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , 
+        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , 
+        left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , 
+        SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_left_out[3] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem_1 mem_top_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_8 (
+    .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , 
+        chanx_left_in[16] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_24 (
+    .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , 
+        chanx_left_in[8] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_9 (
+    .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3 mux_left_track_25 (
+    .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_2 mem_left_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_10 (
+    .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chany_top_out[5] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_12 (
+    .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chany_top_out[6] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_14 (
+    .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+    .out ( chany_top_out[7] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_16 (
+    .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chany_top_out[8] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_18 (
+    .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chany_top_out[9] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_20 (
+    .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( chany_top_out[10] ) , .p0 ( optlc_net_83 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_22 (
+    .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) ,
+    .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+    .out ( chany_top_out[11] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_26 (
+    .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chany_top_out[13] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_11 (
+    .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chanx_left_out[5] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_13 (
+    .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chanx_left_out[6] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_15 (
+    .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
+    .out ( chanx_left_out[7] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_17 (
+    .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_12 mux_left_track_19 (
+    .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
+    .out ( chanx_left_out[9] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_13 mux_left_track_21 (
+    .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( chanx_left_out[10] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_14 mux_left_track_23 (
+    .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+    .out ( chanx_left_out[11] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_27 (
+    .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( chanx_left_out[13] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_29 (
+    .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
+    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_31 (
+    .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_left_out[15] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_33 (
+    .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_18_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_35 (
+    .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_19_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chanx_left_out[17] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_37 (
+    .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_20_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chanx_left_out[18] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2 mux_left_track_39 (
+    .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_21_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chanx_left_out[19] ) , .p0 ( optlc_net_83 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_26 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_left_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_left_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_left_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_left_track_27 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_left_track_29 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_left_track_31 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_19 mem_left_track_35 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_20 mem_left_track_37 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_39 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_left_in[1] ) , 
+    .X ( ropt_net_104 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_left_in[2] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[3] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[4] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[5] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[6] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , 
+    .HI ( optlc_net_83 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , 
+    .HI ( optlc_net_84 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , 
+    .HI ( optlc_net_85 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , 
+    .HI ( optlc_net_86 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_104 ) , 
+    .X ( chany_top_out[19] ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.top_only.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..64bf52f
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.top_only.pt.v
@@ -0,0 +1,506 @@
+//
+//
+//
+//
+//
+//
+module sb_2__0_ ( chany_top_in , top_left_grid_pin_42_ , 
+    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
+    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
+    top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in , 
+    left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , 
+    left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , 
+    left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , 
+    left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , 
+    left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_left_out , 
+    ccff_tail , prog_clk_0_N_in ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_42_ ;
+input  [0:0] top_left_grid_pin_43_ ;
+input  [0:0] top_left_grid_pin_44_ ;
+input  [0:0] top_left_grid_pin_45_ ;
+input  [0:0] top_left_grid_pin_46_ ;
+input  [0:0] top_left_grid_pin_47_ ;
+input  [0:0] top_left_grid_pin_48_ ;
+input  [0:0] top_left_grid_pin_49_ ;
+input  [0:0] top_right_grid_pin_1_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_bottom_grid_pin_1_ ;
+input  [0:0] left_bottom_grid_pin_3_ ;
+input  [0:0] left_bottom_grid_pin_5_ ;
+input  [0:0] left_bottom_grid_pin_7_ ;
+input  [0:0] left_bottom_grid_pin_9_ ;
+input  [0:0] left_bottom_grid_pin_11_ ;
+input  [0:0] left_bottom_grid_pin_13_ ;
+input  [0:0] left_bottom_grid_pin_15_ ;
+input  [0:0] left_bottom_grid_pin_17_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  prog_clk_0_N_in ;
+
+wire ropt_net_104 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_18_sram ;
+wire [0:1] mux_tree_tapbuf_size2_19_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_20_sram ;
+wire [0:1] mux_tree_tapbuf_size2_21_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        top_right_grid_pin_1_[0] , chanx_left_in[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        top_right_grid_pin_1_[0] , chanx_left_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , 
+        SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 (
+    .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , 
+        left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , 
+        SYNOPSYS_UNCONNECTED_9 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_83 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 (
+    .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , 
+        left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , 
+        SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem_1 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 } ) ,
+    .out ( chany_top_out[1] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chanx_left_in[17] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , 
+        SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chany_top_out[3] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 (
+    .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , 
+        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , 
+        left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , 
+        SYNOPSYS_UNCONNECTED_21 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_83 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 (
+    .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , 
+        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , 
+        left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , 
+        SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_left_out[3] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem_1 mem_top_track_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_8 (
+    .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , 
+        chanx_left_in[16] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_24 (
+    .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , 
+        chanx_left_in[8] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_9 (
+    .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3 mux_left_track_25 (
+    .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , 
+        left_bottom_grid_pin_17_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_2 mem_left_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_10 (
+    .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chany_top_out[5] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_12 (
+    .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chany_top_out[6] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_14 (
+    .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+    .out ( chany_top_out[7] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_16 (
+    .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chany_top_out[8] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_18 (
+    .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chany_top_out[9] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_20 (
+    .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( chany_top_out[10] ) , .p0 ( optlc_net_83 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_22 (
+    .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) ,
+    .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+    .out ( chany_top_out[11] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_26 (
+    .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chany_top_out[13] ) , .p0 ( optlc_net_86 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_11 (
+    .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chanx_left_out[5] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_13 (
+    .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chanx_left_out[6] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_15 (
+    .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
+    .out ( chanx_left_out[7] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_17 (
+    .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_12 mux_left_track_19 (
+    .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
+    .out ( chanx_left_out[9] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_13 mux_left_track_21 (
+    .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( chanx_left_out[10] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_14 mux_left_track_23 (
+    .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+    .out ( chanx_left_out[11] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_27 (
+    .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( chanx_left_out[13] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_29 (
+    .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
+    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_31 (
+    .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_left_out[15] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_33 (
+    .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_18_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_84 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_35 (
+    .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_19_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chanx_left_out[17] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_37 (
+    .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_20_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chanx_left_out[18] ) , .p0 ( optlc_net_85 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2 mux_left_track_39 (
+    .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_21_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chanx_left_out[19] ) , .p0 ( optlc_net_83 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_18 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_20 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_22 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_26 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_left_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_left_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_left_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_left_track_27 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_left_track_29 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_left_track_31 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_19 mem_left_track_35 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_20 mem_left_track_37 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_39 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_left_in[1] ) , 
+    .X ( ropt_net_104 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_left_in[2] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[3] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[4] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[5] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[6] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , 
+    .HI ( optlc_net_83 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , 
+    .HI ( optlc_net_84 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , 
+    .HI ( optlc_net_85 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , 
+    .HI ( optlc_net_86 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_104 ) , 
+    .X ( chany_top_out[19] ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v
new file mode 100644
index 0000000..772e6bc
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v
@@ -0,0 +1,2721 @@
+//
+//
+//
+//
+//
+//
+module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+wire copt_net_106 ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_106 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_103 ) , 
+    .X ( copt_net_101 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_101 ) , 
+    .X ( copt_net_102 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_106 ) , 
+    .X ( copt_net_103 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_102 ) , 
+    .X ( copt_net_104 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_104 ) , 
+    .X ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_105 ) , 
+    .X ( mem_out[1] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__1__const1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_31 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__1__const1_31 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_30 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__1__const1_30 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_29 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__1__const1_29 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_28 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__1__const1_28 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_82 ) ) ;
+endmodule
+
+
+module sb_2__1__const1_27 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__1__const1_27 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_80 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_26 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_2__1__const1_26 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_25 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_2__1__const1_25 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_24 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_2__1__const1_24 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_23 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_2__1__const1_23 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_22 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_2__1__const1_22 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_21 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sb_2__1__const1_21 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_20 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sb_2__1__const1_20 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_19 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sb_2__1__const1_19 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .Y ( BUF_net_75 ) ) ;
+endmodule
+
+
+module sb_2__1__const1_18 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sb_2__1__const1_18 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_17 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sb_2__1__const1_17 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .Y ( BUF_net_73 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_16 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_2__1__const1_16 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_71 ) ) ;
+endmodule
+
+
+module sb_2__1__const1_15 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_2__1__const1_15 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_14 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_2__1__const1_14 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_69 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_13 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_2__1__const1_13 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_89 ) ) ;
+endmodule
+
+
+module sb_2__1__const1_12 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_2__1__const1_12 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_11 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_2__1__const1_11 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_10 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_2__1__const1_10 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_9 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_2__1__const1_9 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_63 ) ) ;
+endmodule
+
+
+module sb_2__1__const1_8 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_2__1__const1_8 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_61 ) ) ;
+endmodule
+
+
+module sb_2__1__const1_7 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sb_2__1__const1_7 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_6 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_2__1__const1_6 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_5 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_2__1__const1_5 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_4 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sb_2__1__const1_4 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_3 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sb_2__1__const1_3 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_2 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sb_2__1__const1_2 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_112 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_95 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_97 ) , 
+    .X ( copt_net_96 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_98 ) , 
+    .X ( copt_net_97 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_99 ) , 
+    .X ( copt_net_98 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_95 ) , 
+    .X ( copt_net_99 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_96 ) , 
+    .X ( copt_net_100 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1271 ( .A ( copt_net_100 ) , 
+    .X ( ropt_net_109 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1272 ( .A ( ropt_net_109 ) , 
+    .X ( ropt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1273 ( .A ( ropt_net_110 ) , 
+    .X ( ropt_net_111 ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1274 ( .A ( ropt_net_111 ) , 
+    .X ( ropt_net_112 ) ) ;
+endmodule
+
+
+module sb_2__1__const1_1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_2__1__const1_1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__const1_0 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sb_2__1__const1_0 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1_ ( chany_top_in , top_left_grid_pin_42_ , 
+    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
+    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
+    top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in , 
+    bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ , 
+    bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , 
+    bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , 
+    bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , 
+    bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , 
+    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
+    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
+    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
+    left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , 
+    chanx_left_out , ccff_tail , prog_clk_0_N_in ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_42_ ;
+input  [0:0] top_left_grid_pin_43_ ;
+input  [0:0] top_left_grid_pin_44_ ;
+input  [0:0] top_left_grid_pin_45_ ;
+input  [0:0] top_left_grid_pin_46_ ;
+input  [0:0] top_left_grid_pin_47_ ;
+input  [0:0] top_left_grid_pin_48_ ;
+input  [0:0] top_left_grid_pin_49_ ;
+input  [0:0] top_right_grid_pin_1_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_right_grid_pin_1_ ;
+input  [0:0] bottom_left_grid_pin_42_ ;
+input  [0:0] bottom_left_grid_pin_43_ ;
+input  [0:0] bottom_left_grid_pin_44_ ;
+input  [0:0] bottom_left_grid_pin_45_ ;
+input  [0:0] bottom_left_grid_pin_46_ ;
+input  [0:0] bottom_left_grid_pin_47_ ;
+input  [0:0] bottom_left_grid_pin_48_ ;
+input  [0:0] bottom_left_grid_pin_49_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_bottom_grid_pin_34_ ;
+input  [0:0] left_bottom_grid_pin_35_ ;
+input  [0:0] left_bottom_grid_pin_36_ ;
+input  [0:0] left_bottom_grid_pin_37_ ;
+input  [0:0] left_bottom_grid_pin_38_ ;
+input  [0:0] left_bottom_grid_pin_39_ ;
+input  [0:0] left_bottom_grid_pin_40_ ;
+input  [0:0] left_bottom_grid_pin_41_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  prog_clk_0_N_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size14_0_sram ;
+wire [0:3] mux_tree_tapbuf_size14_1_sram ;
+wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__1__mux_tree_tapbuf_size10_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        top_right_grid_pin_1_[0] , chany_top_out[3] , chany_top_out[13] , 
+        chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 (
+    .in ( { chany_bottom_out[3] , chany_bottom_out[13] , 
+        bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , 
+        chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size10_mem mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_2 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chany_top_out[5] , chany_top_out[14] , chanx_left_in[6] , 
+        chanx_left_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chany_top_out[1] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , 
+        top_right_grid_pin_1_[0] , chany_top_out[7] , chany_top_out[17] , 
+        chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 (
+    .in ( { chany_bottom_out[7] , chany_bottom_out[17] , 
+        bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , 
+        chanx_left_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size14_0 mux_top_track_4 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , 
+        top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , 
+        top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , 
+        top_right_grid_pin_1_[0] , chany_top_out[6] , chany_top_out[15] , 
+        chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size14_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_out[15] , 
+        bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , 
+        bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] , 
+        chanx_left_in[17] } ) ,
+    .sram ( mux_tree_tapbuf_size14_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size14_mem mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_16 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , 
+        chany_top_out[9] , chany_top_out[18] , chanx_left_in[3] , 
+        chanx_left_in[10] , chanx_left_in[17] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 } ) ,
+    .out ( chany_top_out[8] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 (
+    .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , 
+        chany_top_out[10] , chany_top_out[19] , chanx_left_in[2] , 
+        chanx_left_in[9] , chanx_left_in[16] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , 
+        SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 (
+    .in ( { chany_bottom_out[9] , chany_bottom_out[18] , 
+        bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , 
+        chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , 
+        SYNOPSYS_UNCONNECTED_37 } ) ,
+    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 (
+    .in ( { chany_top_in[0] , chany_bottom_out[3] , chany_top_out[3] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , 
+        SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_in[0] , chany_top_out[5] , 
+        chanx_left_out[13] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_in[1] , chany_top_out[6] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , 
+        SYNOPSYS_UNCONNECTED_46 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 (
+    .in ( { chany_bottom_out[7] , chany_bottom_in[3] , chany_top_out[7] , 
+        chanx_left_out[13] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 , 
+        SYNOPSYS_UNCONNECTED_49 } ) ,
+    .out ( chanx_left_out[3] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_left_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_0 mux_top_track_32 (
+    .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , 
+        chany_top_out[11] , chanx_left_in[1] , chanx_left_in[8] , 
+        chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , 
+        SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chany_top_out[16] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 (
+    .in ( { chany_bottom_out[10] , chany_bottom_out[19] , 
+        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , 
+        chanx_left_in[6] , chanx_left_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 (
+    .in ( { chany_bottom_out[11] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , 
+        chanx_left_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , 
+        SYNOPSYS_UNCONNECTED_58 } ) ,
+    .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem mem_bottom_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_out[14] , 
+        bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) ,
+    .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , 
+        SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_9 (
+    .in ( { chany_bottom_out[9] , chany_bottom_in[7] , chany_top_out[9] , 
+        left_bottom_grid_pin_34_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , 
+        SYNOPSYS_UNCONNECTED_65 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_11 (
+    .in ( { chany_bottom_out[10] , chany_top_out[10] , chany_bottom_in[11] , 
+        chanx_left_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , 
+        SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_left_out[5] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 (
+    .in ( { chany_bottom_out[11] , chany_top_out[11] , chany_bottom_in[15] , 
+        left_bottom_grid_pin_36_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , 
+        SYNOPSYS_UNCONNECTED_71 } ) ,
+    .out ( chanx_left_out[6] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4 mux_left_track_15 (
+    .in ( { chany_bottom_out[13] , chany_top_out[13] , chany_bottom_in[19] , 
+        left_bottom_grid_pin_37_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , 
+        SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chanx_left_out[7] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 (
+    .in ( { chany_bottom_out[14] , chany_top_out[14] , 
+        left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 (
+    .in ( { chany_bottom_out[15] , chany_top_out[15] , 
+        left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chanx_left_out[9] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 (
+    .in ( { chany_bottom_out[17] , chany_top_out[17] , 
+        left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+    .out ( chanx_left_out[10] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 (
+    .in ( { chany_bottom_out[18] , chany_top_out[18] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+    .out ( chanx_left_out[11] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 (
+    .in ( { chany_bottom_out[19] , chany_top_out[19] , 
+        left_bottom_grid_pin_34_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 (
+    .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
+    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 (
+    .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+    .out ( chanx_left_out[15] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 (
+    .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 (
+    .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+    .out ( chanx_left_out[17] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 (
+    .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) ,
+    .out ( chanx_left_out[18] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 (
+    .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+    .out ( chanx_left_out[19] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( left_bottom_grid_pin_35_[0] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , 
+    .HI ( optlc_net_91 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , 
+    .HI ( optlc_net_92 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , 
+    .HI ( optlc_net_93 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , 
+    .HI ( optlc_net_94 ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v
new file mode 100644
index 0000000..9f48e31
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v
@@ -0,0 +1,2887 @@
+//
+//
+//
+//
+//
+//
+module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+wire copt_net_106 ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_106 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_103 ) , 
+    .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_101 ) , 
+    .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_106 ) , 
+    .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_102 ) , 
+    .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_104 ) , 
+    .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_105 ) , 
+    .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .Y ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_112 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_97 ) , 
+    .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_98 ) , 
+    .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_99 ) , 
+    .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_95 ) , 
+    .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_96 ) , 
+    .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1271 ( .A ( copt_net_100 ) , 
+    .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1272 ( .A ( ropt_net_109 ) , 
+    .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1273 ( .A ( ropt_net_110 ) , 
+    .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1274 ( .A ( ropt_net_111 ) , 
+    .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__1_ ( chany_top_in , top_left_grid_pin_42_ , 
+    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
+    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
+    top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in , 
+    bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ , 
+    bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , 
+    bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , 
+    bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , 
+    bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , 
+    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
+    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
+    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
+    left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , 
+    chanx_left_out , ccff_tail , prog_clk_0_N_in , VDD , VSS ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_42_ ;
+input  [0:0] top_left_grid_pin_43_ ;
+input  [0:0] top_left_grid_pin_44_ ;
+input  [0:0] top_left_grid_pin_45_ ;
+input  [0:0] top_left_grid_pin_46_ ;
+input  [0:0] top_left_grid_pin_47_ ;
+input  [0:0] top_left_grid_pin_48_ ;
+input  [0:0] top_left_grid_pin_49_ ;
+input  [0:0] top_right_grid_pin_1_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_right_grid_pin_1_ ;
+input  [0:0] bottom_left_grid_pin_42_ ;
+input  [0:0] bottom_left_grid_pin_43_ ;
+input  [0:0] bottom_left_grid_pin_44_ ;
+input  [0:0] bottom_left_grid_pin_45_ ;
+input  [0:0] bottom_left_grid_pin_46_ ;
+input  [0:0] bottom_left_grid_pin_47_ ;
+input  [0:0] bottom_left_grid_pin_48_ ;
+input  [0:0] bottom_left_grid_pin_49_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_bottom_grid_pin_34_ ;
+input  [0:0] left_bottom_grid_pin_35_ ;
+input  [0:0] left_bottom_grid_pin_36_ ;
+input  [0:0] left_bottom_grid_pin_37_ ;
+input  [0:0] left_bottom_grid_pin_38_ ;
+input  [0:0] left_bottom_grid_pin_39_ ;
+input  [0:0] left_bottom_grid_pin_40_ ;
+input  [0:0] left_bottom_grid_pin_41_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  prog_clk_0_N_in ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size14_0_sram ;
+wire [0:3] mux_tree_tapbuf_size14_1_sram ;
+wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__1__mux_tree_tapbuf_size10_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        top_right_grid_pin_1_[0] , chany_top_out[3] , chany_top_out[13] , 
+        chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 (
+    .in ( { chany_bottom_out[3] , chany_bottom_out[13] , 
+        bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , 
+        chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size10_mem mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_2 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chany_top_out[5] , chany_top_out[14] , chanx_left_in[6] , 
+        chanx_left_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , 
+        top_right_grid_pin_1_[0] , chany_top_out[7] , chany_top_out[17] , 
+        chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 (
+    .in ( { chany_bottom_out[7] , chany_bottom_out[17] , 
+        bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , 
+        chanx_left_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size14_0 mux_top_track_4 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , 
+        top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , 
+        top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , 
+        top_right_grid_pin_1_[0] , chany_top_out[6] , chany_top_out[15] , 
+        chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size14_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_out[15] , 
+        bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , 
+        bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] , 
+        chanx_left_in[17] } ) ,
+    .sram ( mux_tree_tapbuf_size14_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size14_mem mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_16 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , 
+        chany_top_out[9] , chany_top_out[18] , chanx_left_in[3] , 
+        chanx_left_in[10] , chanx_left_in[17] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 } ) ,
+    .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 (
+    .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , 
+        chany_top_out[10] , chany_top_out[19] , chanx_left_in[2] , 
+        chanx_left_in[9] , chanx_left_in[16] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , 
+        SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 (
+    .in ( { chany_bottom_out[9] , chany_bottom_out[18] , 
+        bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , 
+        chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , 
+        SYNOPSYS_UNCONNECTED_37 } ) ,
+    .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 (
+    .in ( { chany_top_in[0] , chany_bottom_out[3] , chany_top_out[3] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , 
+        SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_in[0] , chany_top_out[5] , 
+        chanx_left_out[13] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 } ) ,
+    .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_in[1] , chany_top_out[6] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , 
+        SYNOPSYS_UNCONNECTED_46 } ) ,
+    .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 (
+    .in ( { chany_bottom_out[7] , chany_bottom_in[3] , chany_top_out[7] , 
+        chanx_left_out[13] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 , 
+        SYNOPSYS_UNCONNECTED_49 } ) ,
+    .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_left_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_0 mux_top_track_32 (
+    .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , 
+        chany_top_out[11] , chanx_left_in[1] , chanx_left_in[8] , 
+        chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , 
+        SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 (
+    .in ( { chany_bottom_out[10] , chany_bottom_out[19] , 
+        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , 
+        chanx_left_in[6] , chanx_left_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 } ) ,
+    .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 (
+    .in ( { chany_bottom_out[11] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , 
+        chanx_left_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , 
+        SYNOPSYS_UNCONNECTED_58 } ) ,
+    .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem mem_bottom_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_out[14] , 
+        bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) ,
+    .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , 
+        SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+    .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_9 (
+    .in ( { chany_bottom_out[9] , chany_bottom_in[7] , chany_top_out[9] , 
+        left_bottom_grid_pin_34_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , 
+        SYNOPSYS_UNCONNECTED_65 } ) ,
+    .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_11 (
+    .in ( { chany_bottom_out[10] , chany_top_out[10] , chany_bottom_in[11] , 
+        chanx_left_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , 
+        SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 (
+    .in ( { chany_bottom_out[11] , chany_top_out[11] , chany_bottom_in[15] , 
+        left_bottom_grid_pin_36_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , 
+        SYNOPSYS_UNCONNECTED_71 } ) ,
+    .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4 mux_left_track_15 (
+    .in ( { chany_bottom_out[13] , chany_top_out[13] , chany_bottom_in[19] , 
+        left_bottom_grid_pin_37_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , 
+        SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 (
+    .in ( { chany_bottom_out[14] , chany_top_out[14] , 
+        left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 (
+    .in ( { chany_bottom_out[15] , chany_top_out[15] , 
+        left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 (
+    .in ( { chany_bottom_out[17] , chany_top_out[17] , 
+        left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+    .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 (
+    .in ( { chany_bottom_out[18] , chany_top_out[18] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+    .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 (
+    .in ( { chany_bottom_out[19] , chany_top_out[19] , 
+        left_bottom_grid_pin_34_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+    .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 (
+    .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
+    .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 (
+    .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+    .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 (
+    .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) ,
+    .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 (
+    .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+    .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 (
+    .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) ,
+    .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 (
+    .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+    .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( left_bottom_grid_pin_35_[0] ) , 
+    .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , 
+    .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , 
+    .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , 
+    .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , 
+    .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v
new file mode 100644
index 0000000..eae86ad
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v
@@ -0,0 +1,2358 @@
+//
+//
+//
+//
+//
+//
+module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+wire copt_net_106 ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_106 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_103 ) , 
+    .X ( copt_net_101 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_101 ) , 
+    .X ( copt_net_102 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_106 ) , 
+    .X ( copt_net_103 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_102 ) , 
+    .X ( copt_net_104 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_104 ) , 
+    .X ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_105 ) , 
+    .X ( mem_out[1] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_82 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_80 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .Y ( BUF_net_75 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:3] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:8] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .Y ( BUF_net_73 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_71 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_69 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_89 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_63 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .Y ( BUF_net_61 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:6] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:13] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:7] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_112 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_95 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_97 ) , 
+    .X ( copt_net_96 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_98 ) , 
+    .X ( copt_net_97 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_99 ) , 
+    .X ( copt_net_98 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_95 ) , 
+    .X ( copt_net_99 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_96 ) , 
+    .X ( copt_net_100 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1271 ( .A ( copt_net_100 ) , 
+    .X ( ropt_net_109 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1272 ( .A ( ropt_net_109 ) , 
+    .X ( ropt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1273 ( .A ( ropt_net_110 ) , 
+    .X ( ropt_net_111 ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1274 ( .A ( ropt_net_111 ) , 
+    .X ( ropt_net_112 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1_ ( chany_top_in , top_left_grid_pin_42_ , 
+    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
+    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
+    top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in , 
+    bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ , 
+    bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , 
+    bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , 
+    bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , 
+    bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , 
+    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
+    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
+    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
+    left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , 
+    chanx_left_out , ccff_tail , prog_clk_0_N_in ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_42_ ;
+input  [0:0] top_left_grid_pin_43_ ;
+input  [0:0] top_left_grid_pin_44_ ;
+input  [0:0] top_left_grid_pin_45_ ;
+input  [0:0] top_left_grid_pin_46_ ;
+input  [0:0] top_left_grid_pin_47_ ;
+input  [0:0] top_left_grid_pin_48_ ;
+input  [0:0] top_left_grid_pin_49_ ;
+input  [0:0] top_right_grid_pin_1_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_right_grid_pin_1_ ;
+input  [0:0] bottom_left_grid_pin_42_ ;
+input  [0:0] bottom_left_grid_pin_43_ ;
+input  [0:0] bottom_left_grid_pin_44_ ;
+input  [0:0] bottom_left_grid_pin_45_ ;
+input  [0:0] bottom_left_grid_pin_46_ ;
+input  [0:0] bottom_left_grid_pin_47_ ;
+input  [0:0] bottom_left_grid_pin_48_ ;
+input  [0:0] bottom_left_grid_pin_49_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_bottom_grid_pin_34_ ;
+input  [0:0] left_bottom_grid_pin_35_ ;
+input  [0:0] left_bottom_grid_pin_36_ ;
+input  [0:0] left_bottom_grid_pin_37_ ;
+input  [0:0] left_bottom_grid_pin_38_ ;
+input  [0:0] left_bottom_grid_pin_39_ ;
+input  [0:0] left_bottom_grid_pin_40_ ;
+input  [0:0] left_bottom_grid_pin_41_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  prog_clk_0_N_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size14_0_sram ;
+wire [0:3] mux_tree_tapbuf_size14_1_sram ;
+wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__1__mux_tree_tapbuf_size10_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        top_right_grid_pin_1_[0] , chany_top_out[3] , chany_top_out[13] , 
+        chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 (
+    .in ( { chany_bottom_out[3] , chany_bottom_out[13] , 
+        bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , 
+        chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size10_mem mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_2 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chany_top_out[5] , chany_top_out[14] , chanx_left_in[6] , 
+        chanx_left_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chany_top_out[1] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , 
+        top_right_grid_pin_1_[0] , chany_top_out[7] , chany_top_out[17] , 
+        chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 (
+    .in ( { chany_bottom_out[7] , chany_bottom_out[17] , 
+        bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , 
+        chanx_left_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size14_0 mux_top_track_4 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , 
+        top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , 
+        top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , 
+        top_right_grid_pin_1_[0] , chany_top_out[6] , chany_top_out[15] , 
+        chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size14_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_out[15] , 
+        bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , 
+        bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] , 
+        chanx_left_in[17] } ) ,
+    .sram ( mux_tree_tapbuf_size14_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size14_mem mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_16 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , 
+        chany_top_out[9] , chany_top_out[18] , chanx_left_in[3] , 
+        chanx_left_in[10] , chanx_left_in[17] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 } ) ,
+    .out ( chany_top_out[8] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 (
+    .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , 
+        chany_top_out[10] , chany_top_out[19] , chanx_left_in[2] , 
+        chanx_left_in[9] , chanx_left_in[16] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , 
+        SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 (
+    .in ( { chany_bottom_out[9] , chany_bottom_out[18] , 
+        bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , 
+        chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , 
+        SYNOPSYS_UNCONNECTED_37 } ) ,
+    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 (
+    .in ( { chany_top_in[0] , chany_bottom_out[3] , chany_top_out[3] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , 
+        SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_in[0] , chany_top_out[5] , 
+        chanx_left_out[13] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_in[1] , chany_top_out[6] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , 
+        SYNOPSYS_UNCONNECTED_46 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 (
+    .in ( { chany_bottom_out[7] , chany_bottom_in[3] , chany_top_out[7] , 
+        chanx_left_out[13] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 , 
+        SYNOPSYS_UNCONNECTED_49 } ) ,
+    .out ( chanx_left_out[3] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_left_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_0 mux_top_track_32 (
+    .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , 
+        chany_top_out[11] , chanx_left_in[1] , chanx_left_in[8] , 
+        chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , 
+        SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chany_top_out[16] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 (
+    .in ( { chany_bottom_out[10] , chany_bottom_out[19] , 
+        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , 
+        chanx_left_in[6] , chanx_left_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 (
+    .in ( { chany_bottom_out[11] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , 
+        chanx_left_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , 
+        SYNOPSYS_UNCONNECTED_58 } ) ,
+    .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem mem_bottom_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_out[14] , 
+        bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) ,
+    .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , 
+        SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_9 (
+    .in ( { chany_bottom_out[9] , chany_bottom_in[7] , chany_top_out[9] , 
+        left_bottom_grid_pin_34_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , 
+        SYNOPSYS_UNCONNECTED_65 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_11 (
+    .in ( { chany_bottom_out[10] , chany_top_out[10] , chany_bottom_in[11] , 
+        chanx_left_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , 
+        SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_left_out[5] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 (
+    .in ( { chany_bottom_out[11] , chany_top_out[11] , chany_bottom_in[15] , 
+        left_bottom_grid_pin_36_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , 
+        SYNOPSYS_UNCONNECTED_71 } ) ,
+    .out ( chanx_left_out[6] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4 mux_left_track_15 (
+    .in ( { chany_bottom_out[13] , chany_top_out[13] , chany_bottom_in[19] , 
+        left_bottom_grid_pin_37_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , 
+        SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chanx_left_out[7] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 (
+    .in ( { chany_bottom_out[14] , chany_top_out[14] , 
+        left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 (
+    .in ( { chany_bottom_out[15] , chany_top_out[15] , 
+        left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chanx_left_out[9] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 (
+    .in ( { chany_bottom_out[17] , chany_top_out[17] , 
+        left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+    .out ( chanx_left_out[10] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 (
+    .in ( { chany_bottom_out[18] , chany_top_out[18] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+    .out ( chanx_left_out[11] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 (
+    .in ( { chany_bottom_out[19] , chany_top_out[19] , 
+        left_bottom_grid_pin_34_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 (
+    .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
+    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 (
+    .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+    .out ( chanx_left_out[15] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 (
+    .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 (
+    .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+    .out ( chanx_left_out[17] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 (
+    .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) ,
+    .out ( chanx_left_out[18] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 (
+    .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+    .out ( chanx_left_out[19] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( left_bottom_grid_pin_35_[0] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , 
+    .HI ( optlc_net_91 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , 
+    .HI ( optlc_net_92 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , 
+    .HI ( optlc_net_93 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , 
+    .HI ( optlc_net_94 ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.top_only.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..ca4919d
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.top_only.pt.v
@@ -0,0 +1,600 @@
+//
+//
+//
+//
+//
+//
+module sb_2__1_ ( chany_top_in , top_left_grid_pin_42_ , 
+    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
+    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
+    top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in , 
+    bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ , 
+    bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , 
+    bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , 
+    bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , 
+    bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , 
+    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
+    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
+    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
+    left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , 
+    chanx_left_out , ccff_tail , prog_clk_0_N_in ) ;
+input  [0:19] chany_top_in ;
+input  [0:0] top_left_grid_pin_42_ ;
+input  [0:0] top_left_grid_pin_43_ ;
+input  [0:0] top_left_grid_pin_44_ ;
+input  [0:0] top_left_grid_pin_45_ ;
+input  [0:0] top_left_grid_pin_46_ ;
+input  [0:0] top_left_grid_pin_47_ ;
+input  [0:0] top_left_grid_pin_48_ ;
+input  [0:0] top_left_grid_pin_49_ ;
+input  [0:0] top_right_grid_pin_1_ ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_right_grid_pin_1_ ;
+input  [0:0] bottom_left_grid_pin_42_ ;
+input  [0:0] bottom_left_grid_pin_43_ ;
+input  [0:0] bottom_left_grid_pin_44_ ;
+input  [0:0] bottom_left_grid_pin_45_ ;
+input  [0:0] bottom_left_grid_pin_46_ ;
+input  [0:0] bottom_left_grid_pin_47_ ;
+input  [0:0] bottom_left_grid_pin_48_ ;
+input  [0:0] bottom_left_grid_pin_49_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_bottom_grid_pin_34_ ;
+input  [0:0] left_bottom_grid_pin_35_ ;
+input  [0:0] left_bottom_grid_pin_36_ ;
+input  [0:0] left_bottom_grid_pin_37_ ;
+input  [0:0] left_bottom_grid_pin_38_ ;
+input  [0:0] left_bottom_grid_pin_39_ ;
+input  [0:0] left_bottom_grid_pin_40_ ;
+input  [0:0] left_bottom_grid_pin_41_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  prog_clk_0_N_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size14_0_sram ;
+wire [0:3] mux_tree_tapbuf_size14_1_sram ;
+wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__1__mux_tree_tapbuf_size10_0 mux_top_track_0 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
+        top_right_grid_pin_1_[0] , chany_top_out[3] , chany_top_out[13] , 
+        chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( chany_top_out[0] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 (
+    .in ( { chany_bottom_out[3] , chany_bottom_out[13] , 
+        bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , 
+        chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size10_mem mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_2 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
+        chany_top_out[5] , chany_top_out[14] , chanx_left_in[6] , 
+        chanx_left_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chany_top_out[1] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , 
+        top_right_grid_pin_1_[0] , chany_top_out[7] , chany_top_out[17] , 
+        chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( chany_top_out[4] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 (
+    .in ( { chany_bottom_out[7] , chany_bottom_out[17] , 
+        bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , 
+        chanx_left_in[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size14_0 mux_top_track_4 (
+    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , 
+        top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , 
+        top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , 
+        top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , 
+        top_right_grid_pin_1_[0] , chany_top_out[6] , chany_top_out[15] , 
+        chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size14_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chany_top_out[2] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_out[15] , 
+        bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , 
+        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , 
+        bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] , 
+        chanx_left_in[17] } ) ,
+    .sram ( mux_tree_tapbuf_size14_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_top_track_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size14_mem mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_16 (
+    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , 
+        chany_top_out[9] , chany_top_out[18] , chanx_left_in[3] , 
+        chanx_left_in[10] , chanx_left_in[17] } ) ,
+    .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 } ) ,
+    .out ( chany_top_out[8] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 (
+    .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , 
+        chany_top_out[10] , chany_top_out[19] , chanx_left_in[2] , 
+        chanx_left_in[9] , chanx_left_in[16] } ) ,
+    .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , 
+        SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chany_top_out[12] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 (
+    .in ( { chany_bottom_out[9] , chany_bottom_out[18] , 
+        bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , 
+        chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) ,
+    .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , 
+        SYNOPSYS_UNCONNECTED_37 } ) ,
+    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 (
+    .in ( { chany_top_in[0] , chany_bottom_out[3] , chany_top_out[3] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , 
+        SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_in[0] , chany_top_out[5] , 
+        chanx_left_out[13] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 (
+    .in ( { chany_bottom_out[6] , chany_bottom_in[1] , chany_top_out[6] , 
+        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
+        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , 
+        SYNOPSYS_UNCONNECTED_46 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 (
+    .in ( { chany_bottom_out[7] , chany_bottom_in[3] , chany_top_out[7] , 
+        chanx_left_out[13] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 , 
+        SYNOPSYS_UNCONNECTED_49 } ) ,
+    .out ( chanx_left_out[3] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_16 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_top_track_24 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_left_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_0 mux_top_track_32 (
+    .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , 
+        chany_top_out[11] , chanx_left_in[1] , chanx_left_in[8] , 
+        chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , 
+        SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chany_top_out[16] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 (
+    .in ( { chany_bottom_out[10] , chany_bottom_out[19] , 
+        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , 
+        chanx_left_in[6] , chanx_left_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 (
+    .in ( { chany_bottom_out[11] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , 
+        chanx_left_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , 
+        SYNOPSYS_UNCONNECTED_58 } ) ,
+    .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_32 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem mem_bottom_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 (
+    .in ( { chany_bottom_out[5] , chany_bottom_out[14] , 
+        bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) ,
+    .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , 
+        SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_9 (
+    .in ( { chany_bottom_out[9] , chany_bottom_in[7] , chany_top_out[9] , 
+        left_bottom_grid_pin_34_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , 
+        SYNOPSYS_UNCONNECTED_65 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_11 (
+    .in ( { chany_bottom_out[10] , chany_top_out[10] , chany_bottom_in[11] , 
+        chanx_left_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , 
+        SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_left_out[5] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 (
+    .in ( { chany_bottom_out[11] , chany_top_out[11] , chany_bottom_in[15] , 
+        left_bottom_grid_pin_36_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , 
+        SYNOPSYS_UNCONNECTED_71 } ) ,
+    .out ( chanx_left_out[6] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4 mux_left_track_15 (
+    .in ( { chany_bottom_out[13] , chany_top_out[13] , chany_bottom_in[19] , 
+        left_bottom_grid_pin_37_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , 
+        SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chanx_left_out[7] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 (
+    .in ( { chany_bottom_out[14] , chany_top_out[14] , 
+        left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 (
+    .in ( { chany_bottom_out[15] , chany_top_out[15] , 
+        left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chanx_left_out[9] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 (
+    .in ( { chany_bottom_out[17] , chany_top_out[17] , 
+        left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+    .out ( chanx_left_out[10] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 (
+    .in ( { chany_bottom_out[18] , chany_top_out[18] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+    .out ( chanx_left_out[11] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 (
+    .in ( { chany_bottom_out[19] , chany_top_out[19] , 
+        left_bottom_grid_pin_34_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 (
+    .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
+    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 (
+    .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+    .out ( chanx_left_out[15] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 (
+    .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 (
+    .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+    .out ( chanx_left_out[17] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 (
+    .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) ,
+    .out ( chanx_left_out[18] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 (
+    .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+    .out ( chanx_left_out[19] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( left_bottom_grid_pin_35_[0] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , 
+    .HI ( optlc_net_91 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , 
+    .HI ( optlc_net_92 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , 
+    .HI ( optlc_net_93 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , 
+    .HI ( optlc_net_94 ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v
new file mode 100644
index 0000000..3aae9b6
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v
@@ -0,0 +1,2315 @@
+//
+//
+//
+//
+//
+//
+module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__const1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_2__2__const1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_91 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_33 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_2__2__const1_33 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_89 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_32 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sb_2__2__const1_32 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+wire copt_net_102 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_102 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_107 ) , 
+    .X ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_105 ) , 
+    .X ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1271 ( .A ( copt_net_102 ) , 
+    .X ( copt_net_107 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__const1_31 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_31 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__const1_30 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_30 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_86 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_29 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_29 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__const1_28 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_28 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__const1_27 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_27 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_84 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_26 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_26 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__const1_25 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_25 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__const1_24 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_24 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__const1_23 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_23 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__const1_22 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_22 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_81 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_21 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_21 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__const1_20 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_20 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_78 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_19 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_19 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_76 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_18 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_18 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__const1_17 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_17 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_73 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_16 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_16 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__const1_15 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_15 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__const1_14 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_14 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_70 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_13 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_13 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_68 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_12 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_12 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_66 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_11 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_11 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_64 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_10 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_10 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_62 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_9 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_9 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_60 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_8 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sb_2__2__const1_8 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_58 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__const1_7 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_2__2__const1_7 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_55 ( .A ( BUF_net_56 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_56 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_6 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_2__2__const1_6 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_53 ( .A ( BUF_net_54 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_54 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_54 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_5 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_2__2__const1_5 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_52 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_4 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sb_2__2__const1_4 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_50 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_96 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_96 ) , 
+    .X ( copt_net_97 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_97 ) , 
+    .X ( copt_net_98 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_100 ) , 
+    .X ( copt_net_99 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_98 ) , 
+    .X ( copt_net_100 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_99 ) , 
+    .X ( copt_net_101 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( copt_net_101 ) , 
+    .X ( ropt_net_115 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( ropt_net_117 ) , 
+    .X ( ropt_net_116 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , 
+    .X ( ropt_net_117 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_3 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_2__2__const1_3 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_48 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_2 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_2__2__const1_2 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_46 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_2__2__const1_1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_43 ( .A ( BUF_net_44 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_44 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_44 ) ) ;
+endmodule
+
+
+module sb_2__2__const1_0 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sb_2__2__const1_0 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_41 ( .A ( BUF_net_42 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_42 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_42 ) ) ;
+endmodule
+
+
+module sb_2__2_ ( chany_bottom_in , bottom_right_grid_pin_1_ , 
+    bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , 
+    bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , 
+    bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , 
+    bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , 
+    left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , 
+    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
+    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
+    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
+    left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out , 
+    ccff_tail , SC_IN_BOT , SC_OUT_BOT , prog_clk_0_S_in ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_right_grid_pin_1_ ;
+input  [0:0] bottom_left_grid_pin_42_ ;
+input  [0:0] bottom_left_grid_pin_43_ ;
+input  [0:0] bottom_left_grid_pin_44_ ;
+input  [0:0] bottom_left_grid_pin_45_ ;
+input  [0:0] bottom_left_grid_pin_46_ ;
+input  [0:0] bottom_left_grid_pin_47_ ;
+input  [0:0] bottom_left_grid_pin_48_ ;
+input  [0:0] bottom_left_grid_pin_49_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_top_grid_pin_1_ ;
+input  [0:0] left_bottom_grid_pin_34_ ;
+input  [0:0] left_bottom_grid_pin_35_ ;
+input  [0:0] left_bottom_grid_pin_36_ ;
+input  [0:0] left_bottom_grid_pin_37_ ;
+input  [0:0] left_bottom_grid_pin_38_ ;
+input  [0:0] left_bottom_grid_pin_39_ ;
+input  [0:0] left_bottom_grid_pin_40_ ;
+input  [0:0] left_bottom_grid_pin_41_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  SC_IN_BOT ;
+output SC_OUT_BOT ;
+input  prog_clk_0_S_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_18_sram ;
+wire [0:1] mux_tree_tapbuf_size2_19_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_20_sram ;
+wire [0:1] mux_tree_tapbuf_size2_21_sram ;
+wire [0:1] mux_tree_tapbuf_size2_22_sram ;
+wire [0:1] mux_tree_tapbuf_size2_23_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 (
+    .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 (
+    .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , 
+        SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 (
+    .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , 
+        SYNOPSYS_UNCONNECTED_9 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 (
+    .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , 
+        SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 (
+    .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_left_in[2] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 } ) ,
+    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 (
+    .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_left_in[4] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , 
+        SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 (
+    .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , 
+        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , 
+        left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , 
+        SYNOPSYS_UNCONNECTED_21 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 (
+    .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , 
+        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , 
+        left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , 
+        SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_left_out[3] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_9 (
+    .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_11 (
+    .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_13 (
+    .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_15 (
+    .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_17 (
+    .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_19 (
+    .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_21 (
+    .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+    .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_23 (
+    .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) ,
+    .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_27 (
+    .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_29 (
+    .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 (
+    .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+    .out ( chanx_left_out[5] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 (
+    .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chanx_left_out[6] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 (
+    .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chanx_left_out[7] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 (
+    .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 (
+    .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
+    .out ( chanx_left_out[9] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 (
+    .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( chanx_left_out[10] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 (
+    .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
+    .out ( chanx_left_out[11] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 (
+    .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( chanx_left_out[13] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 (
+    .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_18_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 (
+    .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_19_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( chanx_left_out[15] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 (
+    .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_20_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 (
+    .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_21_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_left_out[17] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 (
+    .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_22_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+    .out ( chanx_left_out[18] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 (
+    .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_23_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chanx_left_out[19] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_27 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_29 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 (
+    .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , 
+        chanx_left_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_9 (
+    .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3 mux_left_track_25 (
+    .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[0] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[16] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[17] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[18] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[19] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , 
+    .HI ( optlc_net_92 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , 
+    .HI ( optlc_net_93 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , 
+    .HI ( optlc_net_94 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , 
+    .HI ( optlc_net_95 ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v
new file mode 100644
index 0000000..b2dab06
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v
@@ -0,0 +1,2440 @@
+//
+//
+//
+//
+//
+//
+module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+wire copt_net_102 ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_102 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_107 ) , 
+    .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_105 ) , 
+    .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1271 ( .A ( copt_net_102 ) , 
+    .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_55 ( .A ( BUF_net_56 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_53 ( .A ( BUF_net_54 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_54 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_54 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_96 ) , 
+    .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_97 ) , 
+    .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_100 ) , 
+    .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_98 ) , 
+    .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_99 ) , 
+    .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( copt_net_101 ) , 
+    .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( ropt_net_117 ) , 
+    .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , 
+    .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_43 ( .A ( BUF_net_44 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_44 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_44 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_41 ( .A ( BUF_net_42 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_42 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_42 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module sb_2__2_ ( chany_bottom_in , bottom_right_grid_pin_1_ , 
+    bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , 
+    bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , 
+    bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , 
+    bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , 
+    left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , 
+    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
+    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
+    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
+    left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out , 
+    ccff_tail , SC_IN_BOT , SC_OUT_BOT , prog_clk_0_S_in , VDD , VSS ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_right_grid_pin_1_ ;
+input  [0:0] bottom_left_grid_pin_42_ ;
+input  [0:0] bottom_left_grid_pin_43_ ;
+input  [0:0] bottom_left_grid_pin_44_ ;
+input  [0:0] bottom_left_grid_pin_45_ ;
+input  [0:0] bottom_left_grid_pin_46_ ;
+input  [0:0] bottom_left_grid_pin_47_ ;
+input  [0:0] bottom_left_grid_pin_48_ ;
+input  [0:0] bottom_left_grid_pin_49_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_top_grid_pin_1_ ;
+input  [0:0] left_bottom_grid_pin_34_ ;
+input  [0:0] left_bottom_grid_pin_35_ ;
+input  [0:0] left_bottom_grid_pin_36_ ;
+input  [0:0] left_bottom_grid_pin_37_ ;
+input  [0:0] left_bottom_grid_pin_38_ ;
+input  [0:0] left_bottom_grid_pin_39_ ;
+input  [0:0] left_bottom_grid_pin_40_ ;
+input  [0:0] left_bottom_grid_pin_41_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  SC_IN_BOT ;
+output SC_OUT_BOT ;
+input  prog_clk_0_S_in ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_18_sram ;
+wire [0:1] mux_tree_tapbuf_size2_19_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_20_sram ;
+wire [0:1] mux_tree_tapbuf_size2_21_sram ;
+wire [0:1] mux_tree_tapbuf_size2_22_sram ;
+wire [0:1] mux_tree_tapbuf_size2_23_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 (
+    .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 } ) ,
+    .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 (
+    .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , 
+        SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 (
+    .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , 
+        SYNOPSYS_UNCONNECTED_9 } ) ,
+    .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 (
+    .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , 
+        SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 (
+    .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_left_in[2] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 } ) ,
+    .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 (
+    .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_left_in[4] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , 
+        SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 (
+    .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , 
+        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , 
+        left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , 
+        SYNOPSYS_UNCONNECTED_21 } ) ,
+    .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 (
+    .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , 
+        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , 
+        left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , 
+        SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_9 (
+    .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+    .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_11 (
+    .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_13 (
+    .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_15 (
+    .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_17 (
+    .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_19 (
+    .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_21 (
+    .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+    .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_23 (
+    .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) ,
+    .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_27 (
+    .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_29 (
+    .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 (
+    .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+    .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 (
+    .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 (
+    .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 (
+    .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 (
+    .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
+    .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 (
+    .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 (
+    .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
+    .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 (
+    .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 (
+    .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_18_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+    .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 (
+    .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_19_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 (
+    .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_20_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
+    .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 (
+    .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_21_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 (
+    .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_22_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+    .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 (
+    .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_23_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_27 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_29 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_23_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 (
+    .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , 
+        chanx_left_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_9 (
+    .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3 mux_left_track_25 (
+    .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[0] ) , 
+    .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[16] ) , 
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[17] ) , 
+    .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[18] ) , 
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[19] ) , 
+    .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , 
+    .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , 
+    .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , 
+    .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , 
+    .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v
new file mode 100644
index 0000000..57e0e57
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v
@@ -0,0 +1,1930 @@
+//
+//
+//
+//
+//
+//
+module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_91 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .Y ( BUF_net_89 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:2] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+wire copt_net_102 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_102 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_107 ) , 
+    .X ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_105 ) , 
+    .X ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1271 ( .A ( copt_net_102 ) , 
+    .X ( copt_net_107 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_86 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_84 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_81 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_78 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_76 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_73 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
+    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_70 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_68 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_66 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_64 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_62 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_60 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .Y ( BUF_net_58 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_55 ( .A ( BUF_net_56 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_56 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_53 ( .A ( BUF_net_54 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_54 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_54 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_52 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:4] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .Y ( BUF_net_50 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
+    mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_96 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_96 ) , 
+    .X ( copt_net_97 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_97 ) , 
+    .X ( copt_net_98 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_100 ) , 
+    .X ( copt_net_99 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_98 ) , 
+    .X ( copt_net_100 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_99 ) , 
+    .X ( copt_net_101 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( copt_net_101 ) , 
+    .X ( ropt_net_115 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( ropt_net_117 ) , 
+    .X ( ropt_net_116 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , 
+    .X ( ropt_net_117 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_48 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_46 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_43 ( .A ( BUF_net_44 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_44 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_44 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:5] in ;
+input  [0:2] sram ;
+input  [0:2] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_41 ( .A ( BUF_net_42 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_42 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
+    .Y ( BUF_net_42 ) ) ;
+endmodule
+
+
+module sb_2__2_ ( chany_bottom_in , bottom_right_grid_pin_1_ , 
+    bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , 
+    bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , 
+    bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , 
+    bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , 
+    left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , 
+    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
+    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
+    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
+    left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out , 
+    ccff_tail , SC_IN_BOT , SC_OUT_BOT , prog_clk_0_S_in ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_right_grid_pin_1_ ;
+input  [0:0] bottom_left_grid_pin_42_ ;
+input  [0:0] bottom_left_grid_pin_43_ ;
+input  [0:0] bottom_left_grid_pin_44_ ;
+input  [0:0] bottom_left_grid_pin_45_ ;
+input  [0:0] bottom_left_grid_pin_46_ ;
+input  [0:0] bottom_left_grid_pin_47_ ;
+input  [0:0] bottom_left_grid_pin_48_ ;
+input  [0:0] bottom_left_grid_pin_49_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_top_grid_pin_1_ ;
+input  [0:0] left_bottom_grid_pin_34_ ;
+input  [0:0] left_bottom_grid_pin_35_ ;
+input  [0:0] left_bottom_grid_pin_36_ ;
+input  [0:0] left_bottom_grid_pin_37_ ;
+input  [0:0] left_bottom_grid_pin_38_ ;
+input  [0:0] left_bottom_grid_pin_39_ ;
+input  [0:0] left_bottom_grid_pin_40_ ;
+input  [0:0] left_bottom_grid_pin_41_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  SC_IN_BOT ;
+output SC_OUT_BOT ;
+input  prog_clk_0_S_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_18_sram ;
+wire [0:1] mux_tree_tapbuf_size2_19_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_20_sram ;
+wire [0:1] mux_tree_tapbuf_size2_21_sram ;
+wire [0:1] mux_tree_tapbuf_size2_22_sram ;
+wire [0:1] mux_tree_tapbuf_size2_23_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 (
+    .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 (
+    .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , 
+        SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 (
+    .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , 
+        SYNOPSYS_UNCONNECTED_9 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 (
+    .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , 
+        SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 (
+    .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_left_in[2] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 } ) ,
+    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 (
+    .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_left_in[4] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , 
+        SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 (
+    .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , 
+        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , 
+        left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , 
+        SYNOPSYS_UNCONNECTED_21 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 (
+    .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , 
+        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , 
+        left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , 
+        SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_left_out[3] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_9 (
+    .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_11 (
+    .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_13 (
+    .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_15 (
+    .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_17 (
+    .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_19 (
+    .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_21 (
+    .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+    .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_23 (
+    .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) ,
+    .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_27 (
+    .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_29 (
+    .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 (
+    .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+    .out ( chanx_left_out[5] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 (
+    .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chanx_left_out[6] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 (
+    .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chanx_left_out[7] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 (
+    .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 (
+    .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
+    .out ( chanx_left_out[9] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 (
+    .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( chanx_left_out[10] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 (
+    .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
+    .out ( chanx_left_out[11] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 (
+    .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( chanx_left_out[13] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 (
+    .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_18_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 (
+    .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_19_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( chanx_left_out[15] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 (
+    .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_20_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 (
+    .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_21_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_left_out[17] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 (
+    .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_22_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+    .out ( chanx_left_out[18] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 (
+    .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_23_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chanx_left_out[19] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_27 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_29 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 (
+    .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , 
+        chanx_left_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_9 (
+    .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3 mux_left_track_25 (
+    .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[0] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[16] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[17] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[18] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[19] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , 
+    .HI ( optlc_net_92 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , 
+    .HI ( optlc_net_93 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , 
+    .HI ( optlc_net_94 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , 
+    .HI ( optlc_net_95 ) ) ;
+endmodule
+
+
diff --git a/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.top_only.pt.v b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..6b643cc
--- /dev/null
+++ b/FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.top_only.pt.v
@@ -0,0 +1,516 @@
+//
+//
+//
+//
+//
+//
+module sb_2__2_ ( chany_bottom_in , bottom_right_grid_pin_1_ , 
+    bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , 
+    bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , 
+    bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , 
+    bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , 
+    left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , 
+    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
+    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
+    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
+    left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out , 
+    ccff_tail , SC_IN_BOT , SC_OUT_BOT , prog_clk_0_S_in ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:0] bottom_right_grid_pin_1_ ;
+input  [0:0] bottom_left_grid_pin_42_ ;
+input  [0:0] bottom_left_grid_pin_43_ ;
+input  [0:0] bottom_left_grid_pin_44_ ;
+input  [0:0] bottom_left_grid_pin_45_ ;
+input  [0:0] bottom_left_grid_pin_46_ ;
+input  [0:0] bottom_left_grid_pin_47_ ;
+input  [0:0] bottom_left_grid_pin_48_ ;
+input  [0:0] bottom_left_grid_pin_49_ ;
+input  [0:19] chanx_left_in ;
+input  [0:0] left_top_grid_pin_1_ ;
+input  [0:0] left_bottom_grid_pin_34_ ;
+input  [0:0] left_bottom_grid_pin_35_ ;
+input  [0:0] left_bottom_grid_pin_36_ ;
+input  [0:0] left_bottom_grid_pin_37_ ;
+input  [0:0] left_bottom_grid_pin_38_ ;
+input  [0:0] left_bottom_grid_pin_39_ ;
+input  [0:0] left_bottom_grid_pin_40_ ;
+input  [0:0] left_bottom_grid_pin_41_ ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input  SC_IN_BOT ;
+output SC_OUT_BOT ;
+input  prog_clk_0_S_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_18_sram ;
+wire [0:1] mux_tree_tapbuf_size2_19_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_20_sram ;
+wire [0:1] mux_tree_tapbuf_size2_21_sram ;
+wire [0:1] mux_tree_tapbuf_size2_22_sram ;
+wire [0:1] mux_tree_tapbuf_size2_23_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 (
+    .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) ,
+    .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 } ) ,
+    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 (
+    .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , 
+        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
+        bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) ,
+    .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , 
+        SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 (
+    .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , 
+        SYNOPSYS_UNCONNECTED_9 } ) ,
+    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 (
+    .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
+        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , 
+        SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 (
+    .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_left_in[2] } ) ,
+    .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 } ) ,
+    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 (
+    .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
+        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
+        chanx_left_in[4] } ) ,
+    .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , 
+        SYNOPSYS_UNCONNECTED_18 } ) ,
+    .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 (
+    .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , 
+        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , 
+        left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , 
+        SYNOPSYS_UNCONNECTED_21 } ) ,
+    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 (
+    .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , 
+        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , 
+        left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , 
+        SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( chanx_left_out[3] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_9 (
+    .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) ,
+    .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_11 (
+    .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) ,
+    .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_13 (
+    .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) ,
+    .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+    .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_15 (
+    .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) ,
+    .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_17 (
+    .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) ,
+    .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_19 (
+    .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) ,
+    .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_21 (
+    .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) ,
+    .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+    .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_95 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_23 (
+    .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) ,
+    .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_27 (
+    .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) ,
+    .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+    .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_29 (
+    .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) ,
+    .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 (
+    .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+    .out ( chanx_left_out[5] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 (
+    .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( chanx_left_out[6] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 (
+    .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+    .out ( chanx_left_out[7] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 (
+    .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 (
+    .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
+    .out ( chanx_left_out[9] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 (
+    .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( chanx_left_out[10] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 (
+    .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
+    .out ( chanx_left_out[11] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 (
+    .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( chanx_left_out[13] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 (
+    .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_18_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 (
+    .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_19_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( chanx_left_out[15] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 (
+    .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_20_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
+    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 (
+    .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_21_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( chanx_left_out[17] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 (
+    .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_22_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+    .out ( chanx_left_out[18] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 (
+    .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size2_23_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+    .out ( chanx_left_out[19] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_27 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_29 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 (
+    .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , 
+        chanx_left_in[13] } ) ,
+    .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_9 (
+    .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_94 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3 mux_left_track_25 (
+    .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , 
+        left_bottom_grid_pin_41_[0] } ) ,
+    .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_25 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[0] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[16] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[17] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[18] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[19] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , 
+    .HI ( optlc_net_92 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , 
+    .HI ( optlc_net_93 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , 
+    .HI ( optlc_net_94 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , 
+    .HI ( optlc_net_95 ) ) ;
+endmodule
+
+