diff --git a/TESTBENCH/common/post_pnr_fpga_cells.v b/TESTBENCH/common/post_pnr_fpga_cells.v index cebd223..5bfa734 100644 --- a/TESTBENCH/common/post_pnr_fpga_cells.v +++ b/TESTBENCH/common/post_pnr_fpga_cells.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4ae0fb278944fcfc542a395b998e06e1c5d473df8d7d192ff9a386f1ba596ee4 -size 7630 +oid sha256:89b4703e97499ddd03efb70998f547462d7a8fa5d27e2c2d2af132b2050e195d +size 7942 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v index 3891371..e40f43e 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v @@ -1,29 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_latch_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:3140f41d14f1046308ebd07b6527c4ec781ab3c18e63b237aba9b435b9c044de +size 1239 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v index 3486b82..2781b69 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v @@ -1,31 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_latch_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:9d2003a31c42e9558a77f3891b6284affed509e22d38dbb150f475db968c5f8e +size 1343 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v index 5e8fe9c..731e086 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v @@ -1,29 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Nov 22 13:37:06 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_or2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:6395e2f33f3dcb8dad1c92fa0659bc4b842b3495d683add90e50d942e28b6ef1 +size 1235 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v index 45cf601..f9dd991 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v @@ -1,31 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_or2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:ec87f38ebc0e4f795a0a72b760f6181288ef6f7cc72f7708ec21d77a1ea8c28d +size 1339 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v index 3bb3a24..bf40134 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -1,29 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:0168df4405980eb7be0f0231735794d86c514199126d0941f043ba38905d0c4f +size 1227 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v index 3db9134..1e21a4f 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v @@ -1,31 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:3fc3f03b263ff267b9543c09f338222e9e9950978915a10a16825decd8deab4c +size 1331 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v index 9ae6575..704f7a0 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v @@ -1,28 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 144 - -// Design parameter for FPGA bitstream sizes -`define FPGA_BITSTREAM_SIZE 67960 - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/ccff_test_post_pnr.v" +version https://git-lfs.github.com/spec/v1 +oid sha256:c67a41b0721d08ca8fbc02d2b9c105717cfd1cf8f596c392ce97a253315d5e3e +size 1194 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v index 1946f9c..386cac1 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v @@ -1,30 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 144 - -// Design parameter for FPGA bitstream sizes -`define FPGA_BITSTREAM_SIZE 67960 - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v" +version https://git-lfs.github.com/spec/v1 +oid sha256:f5fe62252b7eae6cd437a4fde8a18dcdcc61e629ab847b6bffa2d8d0d8dc60b4 +size 1353 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v index 3a4654c..79c523c 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v @@ -1,29 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Fri Nov 20 15:48:54 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "routing_test_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:9a2a5d743a10211cd55496c15a559690e5a09a328edcb0942d901ba5e5df48b8 +size 1243 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v index e4a342c..e440cab 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v @@ -1,31 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "routing_test_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:a18b7fab25c736e3d465a51353672d7bc5dc7e693145fee2837afc1d11b78289 +size 1347 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v index e2a7f73..3b63c78 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -1,28 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 144 - -// Design parameter for FPGA bitstream sizes -`define FPGA_SCANCHAIN_SIZE 2304 - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/scff_test_post_pnr.v" +version https://git-lfs.github.com/spec/v1 +oid sha256:0f73b27a645609f040e12548f221f24cce4054ed6bff9d74664a2f3c6dc70bb5 +size 1193 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v index 9b12e2c..8783bb0 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v @@ -1,30 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 144 - -// Design parameter for FPGA bitstream sizes -`define FPGA_SCANCHAIN_SIZE 2304 - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v" +version https://git-lfs.github.com/spec/v1 +oid sha256:5dd9f4ffe36c1f5ac05ff49da29ec5541913f2e2efce7cf7a4c7e1cb9120264e +size 1352 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v index 9d4b256..ca377b7 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v @@ -1,29 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_latch_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:32e7a27472ef1501fec8765f8a7beb44ab61c84c514a5f63801840cfdec20eb7 +size 1272 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v index 540d182..5d0b93a 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v @@ -1,31 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_latch_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:c2067d21d21d3666ebe52b8de512bf06020ab395b65304387709e166e1d43a23 +size 1376 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v index 7b2d42a..b93bc4a 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v @@ -1,29 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Nov 22 13:37:06 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_or2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:ee2934fe5c3048ac3655a3cc6213f176d83c3495aef7428904ad229f39d424a0 +size 1268 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v index cf3bb8f..c87613f 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v @@ -1,31 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_or2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:1707e2d2da1c2eba04f17079d9d9144b71be24bf19b9d99c83ceefc5d46d6afd +size 1372 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v index 3d84fa3..0fe63cd 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -1,29 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:35a893d7106b66061ef6c45570ba26c5eb2cc31c1ba667193e01003e1a3c8294 +size 1260 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v index 4a7d602..d6c6337 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v @@ -1,31 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:3cfd0b49a75dbcc308f61212ed162d2c74c9343bffe35d78cb39fa553507b559 +size 1364 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v index b1183c5..cabcdba 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v @@ -1,28 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 144 - -// Design parameter for FPGA bitstream sizes -`define FPGA_BITSTREAM_SIZE 78765 - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/ccff_test_post_pnr.v" +version https://git-lfs.github.com/spec/v1 +oid sha256:a6da97988b4c39f03920feae95a4f07c9b382d4be3687a656eaef8f75126d615 +size 1211 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v index 0b6a7f4..222f122 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v @@ -1,30 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 144 - -// Design parameter for FPGA bitstream sizes -`define FPGA_BITSTREAM_SIZE 78765 - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v" +version https://git-lfs.github.com/spec/v1 +oid sha256:cedd3fbe2dc2158e46da28ab3b630b45571f7015b89f29391b092bb3860fdbcc +size 1386 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v index 8acf961..a37047e 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v @@ -1,29 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Fri Nov 20 15:48:54 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "routing_test_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:7dbfbefcae891ea972982503967a7dc838843bd86ff134873a38da4a1c4b4a1f +size 1276 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v index 74e2be5..d5bbb87 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v @@ -1,31 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "routing_test_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:b5388c9df5e22b40644563abea84f530445b17a43673499bcfcb9680acf5aa66 +size 1380 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v index 84b99ba..f24381f 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -1,28 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 144 - -// Design parameter for FPGA bitstream sizes -`define FPGA_SCANCHAIN_SIZE 2304 - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/scff_test_post_pnr.v" +version https://git-lfs.github.com/spec/v1 +oid sha256:31aeb268b252e6defeec5d00e777ec417acc65697a5dbdad6b73d211db85be36 +size 1210 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v index 4822ff7..73ead6b 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v @@ -1,30 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 144 - -// Design parameter for FPGA bitstream sizes -`define FPGA_SCANCHAIN_SIZE 2304 - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v" +version https://git-lfs.github.com/spec/v1 +oid sha256:e7a163317878eb9295a02108efc9a8e7c3f4a5485aa05e03bd29b40445d88d88 +size 1385