diff --git a/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml new file mode 100644 index 0000000..fc8e81d --- /dev/null +++ b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml @@ -0,0 +1,26 @@ +L1_SB_MUX_DELAY: 1.61e-9 +L2_SB_MUX_DELAY: 1.61e-9 +L4_SB_MUX_DELAY: 1.61e-9 +CB_MUX_DELAY: 1.38e-9 +L1_WIRE_R: 100 +L1_WIRE_C: 1e-12 +L2_WIRE_R: 100 +L2_WIRE_C: 1e-12 +L4_WIRE_R: 100 +L4_WIRE_C: 1e-12 +INPAD_DELAY: 0.11e-9 +OUTPAD_DELAY: 0.11e-9 +FF_T_SETUP: 0.39e-9 +FF_T_CLK2Q: 0.43e-9 +LUT_OUT0_TO_FF_D_DELAY: 1.14e-9 +LUT_OUT1_TO_FF_D_DELAY: 0.56e-9 +LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 +FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 +LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 +FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 +LUT3_DELAY: 2.31e-9 +LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9 +LUT4_DELAY: 2.6e-9 +LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9 +REGIN_TO_FF0_DELAY: 0.58e-9 +FF0_TO_FF1_DELAY: 0.56e-9 diff --git a/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml b/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml new file mode 100644 index 0000000..a7eb774 --- /dev/null +++ b/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml @@ -0,0 +1,26 @@ +L1_SB_MUX_DELAY: 1.44e-9 +L2_SB_MUX_DELAY: 1.44e-9 +L4_SB_MUX_DELAY: 1.44e-9 +CB_MUX_DELAY: 1.38e-9 +L1_WIRE_R: 100 +L1_WIRE_C: 1e-12 +L2_WIRE_R: 100 +L2_WIRE_C: 1e-12 +L4_WIRE_R: 100 +L4_WIRE_C: 1e-12 +INPAD_DELAY: 0.11e-9 +OUTPAD_DELAY: 0.11e-9 +FF_T_SETUP: 0.39e-9 +FF_T_CLK2Q: 0.43e-9 +LUT_OUT0_TO_FF_D_DELAY: 1.14e-9 +LUT_OUT1_TO_FF_D_DELAY: 0.56e-9 +LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 +FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 +LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 +FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 +LUT3_DELAY: 2.31e-9 +LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9 +LUT4_DELAY: 2.6e-9 +LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9 +REGIN_TO_FF0_DELAY: 1.12e-9 +FF0_TO_FF1_DELAY: 0.56e-9 diff --git a/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml b/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml new file mode 100644 index 0000000..a7eb774 --- /dev/null +++ b/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml @@ -0,0 +1,26 @@ +L1_SB_MUX_DELAY: 1.44e-9 +L2_SB_MUX_DELAY: 1.44e-9 +L4_SB_MUX_DELAY: 1.44e-9 +CB_MUX_DELAY: 1.38e-9 +L1_WIRE_R: 100 +L1_WIRE_C: 1e-12 +L2_WIRE_R: 100 +L2_WIRE_C: 1e-12 +L4_WIRE_R: 100 +L4_WIRE_C: 1e-12 +INPAD_DELAY: 0.11e-9 +OUTPAD_DELAY: 0.11e-9 +FF_T_SETUP: 0.39e-9 +FF_T_CLK2Q: 0.43e-9 +LUT_OUT0_TO_FF_D_DELAY: 1.14e-9 +LUT_OUT1_TO_FF_D_DELAY: 0.56e-9 +LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 +FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 +LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 +FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 +LUT3_DELAY: 2.31e-9 +LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9 +LUT4_DELAY: 2.6e-9 +LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9 +REGIN_TO_FF0_DELAY: 1.12e-9 +FF0_TO_FF1_DELAY: 0.56e-9 diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index 21f4189..78852d0 100644 --- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -1,5 +1,5 @@ @@ -186,21 +188,6 @@ - - - - + + + + - + - + - + 1 1 1 - + 1 1 1 1 1 - + 1 1 1 1 1 1 1 1 1 @@ -277,18 +255,17 @@ - + - + @@ -296,7 +273,7 @@ - + @@ -306,7 +283,7 @@ - + @@ -386,9 +363,9 @@ - - - + + + @@ -398,22 +375,22 @@ - - + + - - + + - - + + - - + + @@ -443,18 +420,10 @@ - - 235e-12 - 235e-12 - 235e-12 + ${LUT3_DELAY} + ${LUT3_DELAY} + ${LUT3_DELAY} @@ -462,20 +431,22 @@ - - + + + + - - - + + + @@ -505,20 +476,11 @@ - - 261e-12 - 261e-12 - 261e-12 - 261e-12 + ${LUT4_DELAY} + ${LUT4_DELAY} + ${LUT4_DELAY} + ${LUT4_DELAY} @@ -526,20 +488,22 @@ - - + + + + - - - + + + @@ -561,15 +525,27 @@ - - + + - - + + + + + + + + - - + + + + + + + + @@ -591,52 +567,36 @@ I[0] should be connected to in[0] --> - - - - - - - - - - - - - - - - @@ -650,7 +610,7 @@ - + @@ -662,7 +622,7 @@ - + diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index b7c3089..fa538ba 100644 --- a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -1,5 +1,5 @@ - - - + + + - + - - + 1 1 1 - + 1 1 1 1 1 - + 1 1 1 1 1 1 1 1 1 @@ -296,10 +265,10 @@ - + - + @@ -315,7 +284,7 @@ - + @@ -325,7 +294,7 @@ - + @@ -430,10 +399,10 @@ - - - - + + + + @@ -446,22 +415,22 @@ - - + + - - + + - - + + - - + + @@ -494,18 +463,10 @@ - - 235e-12 - 235e-12 - 235e-12 + ${LUT3_DELAY} + ${LUT3_DELAY} + ${LUT3_DELAY} @@ -513,8 +474,8 @@ - - + + @@ -525,8 +486,8 @@ - - + + @@ -556,20 +517,11 @@ - - 261e-12 - 261e-12 - 261e-12 - 261e-12 + ${LUT4_DELAY} + ${LUT4_DELAY} + ${LUT4_DELAY} + ${LUT4_DELAY} @@ -577,20 +529,21 @@ - - + + + - - + + @@ -612,15 +565,23 @@ - - + + - - + + + + + + - - + + + + + + @@ -642,52 +603,36 @@ I[0] should be connected to in[0] --> - - - - - - - - - - - - - - - - @@ -703,7 +648,7 @@ - + @@ -715,7 +660,7 @@ - + @@ -724,7 +669,7 @@ - + diff --git a/DOC/requirements.txt b/DOC/requirements.txt index 314f232..c3e7e66 100644 --- a/DOC/requirements.txt +++ b/DOC/requirements.txt @@ -9,6 +9,12 @@ sphinxcontrib-bibtex<2.0.0 sphinxcontrib-tikz +# Package required to embed youtube video +sphinxcontrib-yt + +# Package required to convert SVG for latex building +sphinxcontrib-svg2pdfconverter + #Work-around bug "AttributeError: 'Values' object has no attribute 'character_level_inline_markup'" with docutils 0.13.1 #See: # * https://github.com/sphinx-doc/sphinx/issues/3951 diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg new file mode 100644 index 0000000..8b7cb01 --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg @@ -0,0 +1,397 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.4\n2021-04-02 20:35:25 +0000 + + schematic_timing + + 图层 1 + + + + + + + + + + + + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + + + + + FF + [0] + + + + + + + + + + + + + + + + + + + + + + + out[0] + + + + + + + + + M + U + X + + + + + + + + + + + + + + + FF + [1] + + + + + + + + + + + + + + + + + + + + + + + out[1] + + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + scin + + + + + + + + + + + scout + + + + + + + + + + + + + + + + + + + + regin + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + + + regout + + + + + CLK + + + + + + + + + + + + + + + + + + + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + + + + + + + cin + + + + + + + + + M + U + X + + + + + LUT2_out[1] + + + + + + + + + + + + + + + MUX + + + + + LUT2_out[0] + + + + + + + + + + + + + + + cout + + + + + + + + Reset + + + + + + + + + + + + A + + + + + diff --git a/DOC/source/datasheet/qlsofa_hd/index.rst b/DOC/source/datasheet/qlsofa_hd/index.rst index b736ea8..bbaf130 100644 --- a/DOC/source/datasheet/qlsofa_hd/index.rst +++ b/DOC/source/datasheet/qlsofa_hd/index.rst @@ -14,3 +14,5 @@ QLSOFA HD qlsofa_hd_clb_arch qlsofa_hd_circuit_design + + qlsofa_hd_timing diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst index c05e1c7..8c204ed 100644 --- a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst @@ -46,6 +46,32 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra | | | cells. | +------+----------+----------------------------------------------+ +.. _qlsofa_hd_fpga_arch_routing_arch: + +Routing Architecture +^^^^^^^^^^^^^^^^^^^^ + +The routing architecture shares the same principle as the SOFA HD routing architecture (See details in :ref:`sofa_hd_fpga_arch_routing_arch`). + +.. note:: Different from SOFA HD, each routing channel consists of 60 routing tracks. See details in :numref:`table_qlsofa_hd_fpga_arch_routing_track_distribution`. + +.. _table_qlsofa_hd_fpga_arch_routing_track_distribution: + +.. table:: Routing track distribution of QLSOFA HD FPGA + + +------------+------------------------------+ + | Track type | Number of tracks per channel | + +============+==============================+ + | Length-1 | 6 (10%) | + +------------+------------------------------+ + | Length-2 | 6 (10%) | + +------------+------------------------------+ + | Length-4 | 48 (80%) | + +------------+------------------------------+ + | Total | 60 | + +------------+------------------------------+ + + .. _qlsofa_hd_fpga_arch_scan_chain: Scan-chain diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst new file mode 100644 index 0000000..c5cfbf4 --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst @@ -0,0 +1,100 @@ +.. _qlsofa_hd_timing: + +Timing Annotation +----------------- + +.. _qlsofa_hd_timing_clb: + +Configurable Logic Block +^^^^^^^^^^^^^^^^^^^^^^^^ + +The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`. + +.. _fig_qlsofa_hd_fle_arch_timing: + +.. figure:: ./figures/qlsofa_hd_fle_arch_timing.svg + :scale: 30% + :alt: Schematic of a logic element used in QLSOFA HD FPGA + + Schematic of a logic element used in QLSOFA HD FPGA + +.. _table_qlsofa_hd_fle_arch_timing: + +.. table:: Path delays of logic element in the QLSOFA HD FPGA + + +-------------------------+------------------------------+ + | Path / Delay | TT (unit: ns) | + +=========================+==============================+ + | in0 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in1 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in2 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in0 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in1 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in2 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in0 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in1 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in2 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in3 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | LUT3_out[0] -> A | 0.56 | + +-------------------------+------------------------------+ + | LUT4_out[0] -> A | 0.58 | + +-------------------------+------------------------------+ + | A -> out[0] | 0.88 | + +-------------------------+------------------------------+ + | A -> FF[0] | 0.56 | + +-------------------------+------------------------------+ + | FF[0] -> out[0] | 0.88 | + +-------------------------+------------------------------+ + | LUT3_out[1] -> out[1] | 0.89 | + +-------------------------+------------------------------+ + | LUT3_out[1] -> FF[1] | 0.56 | + +-------------------------+------------------------------+ + | FF[1] -> out[1] | 0.89 | + +-------------------------+------------------------------+ + | regin -> FF[0] | 0.58 | + +-------------------------+------------------------------+ + | FF[0] -> FF[1] | 0.56 | + +-------------------------+------------------------------+ + +.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques. + +.. _qlsofa_hd_timing_io: + +I/O Block +^^^^^^^^^ + +The path delays of I/O blocks in QLSOFA HD FPGA is same as the SOFA HD FPGA. See details in :ref:`sofa_hd_timing_io`. + +.. _qlsofa_hd_timing_routing: + +Routing Architecture +^^^^^^^^^^^^^^^^^^^^ + +The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`table_qlsofa_hd_routing_arch_timing`. + +.. _table_qlsofa_hd_routing_arch_timing: + +.. table:: Path delays of routing blocks in the QLSOFA HD FPGA + + +---------------------------+------------------------------+ + | Path / Delay | TT (unit: ns) | + +===========================+==============================+ + | A -> B | 1.44 | + +---------------------------+------------------------------+ + | A -> C | 1.44 | + +---------------------------+------------------------------+ + | A -> D | 1.44 | + +---------------------------+------------------------------+ + | B -> E | 1.38 | + +---------------------------+------------------------------+ + diff --git a/DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg b/DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg new file mode 100644 index 0000000..8b7cb01 --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg @@ -0,0 +1,397 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.4\n2021-04-02 20:35:25 +0000 + + schematic_timing + + 图层 1 + + + + + + + + + + + + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + + + + + FF + [0] + + + + + + + + + + + + + + + + + + + + + + + out[0] + + + + + + + + + M + U + X + + + + + + + + + + + + + + + FF + [1] + + + + + + + + + + + + + + + + + + + + + + + out[1] + + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + scin + + + + + + + + + + + scout + + + + + + + + + + + + + + + + + + + + regin + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + + + regout + + + + + CLK + + + + + + + + + + + + + + + + + + + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + + + + + + + cin + + + + + + + + + M + U + X + + + + + LUT2_out[1] + + + + + + + + + + + + + + + MUX + + + + + LUT2_out[0] + + + + + + + + + + + + + + + cout + + + + + + + + Reset + + + + + + + + + + + + A + + + + + diff --git a/DOC/source/datasheet/sofa_chd/index.rst b/DOC/source/datasheet/sofa_chd/index.rst index a35e5fe..6a29d92 100644 --- a/DOC/source/datasheet/sofa_chd/index.rst +++ b/DOC/source/datasheet/sofa_chd/index.rst @@ -14,3 +14,5 @@ SOFA CHD sofa_chd_clb_arch sofa_chd_circuit_design + + sofa_chd_timing diff --git a/DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst b/DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst new file mode 100644 index 0000000..65fef7a --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst @@ -0,0 +1,100 @@ +.. _sofa_chd_timing: + +Timing Annotation +----------------- + +.. _sofa_chd_timing_clb: + +Configurable Logic Block +^^^^^^^^^^^^^^^^^^^^^^^^ + +The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref:`table_sofa_chd_fle_arch_timing`. + +.. _fig_sofa_chd_fle_arch_timing: + +.. figure:: ./figures/sofa_chd_fle_arch_timing.svg + :scale: 30% + :alt: Schematic of a logic element used in SOFA CHD FPGA + + Schematic of a logic element used in SOFA CHD FPGA + +.. _table_sofa_chd_fle_arch_timing: + +.. table:: Path delays of logic element in the SOFA CHD FPGA + + +-------------------------+------------------------------+ + | Path / Delay | TT (unit: ns) | + +=========================+==============================+ + | in0 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in1 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in2 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in0 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in1 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in2 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in0 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in1 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in2 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in3 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | LUT3_out[0] -> A | 0.56 | + +-------------------------+------------------------------+ + | LUT4_out[0] -> A | 0.58 | + +-------------------------+------------------------------+ + | A -> out[0] | 0.88 | + +-------------------------+------------------------------+ + | A -> FF[0] | 0.56 | + +-------------------------+------------------------------+ + | FF[0] -> out[0] | 0.88 | + +-------------------------+------------------------------+ + | LUT3_out[1] -> out[1] | 0.89 | + +-------------------------+------------------------------+ + | LUT3_out[1] -> FF[1] | 0.56 | + +-------------------------+------------------------------+ + | FF[1] -> out[1] | 0.89 | + +-------------------------+------------------------------+ + | regin -> FF[0] | 0.58 | + +-------------------------+------------------------------+ + | FF[0] -> FF[1] | 0.56 | + +-------------------------+------------------------------+ + +.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques. + +.. _sofa_chd_timing_io: + +I/O Block +^^^^^^^^^ + +The path delays of I/O blocks in SOFA CHD FPGA is same as the SOFA HD FPGA. See details in :ref:`sofa_hd_timing_io`. + +.. _sofa_chd_timing_routing: + +Routing Architecture +^^^^^^^^^^^^^^^^^^^^ + +The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`table_sofa_chd_routing_arch_timing`. + +.. _table_sofa_chd_routing_arch_timing: + +.. table:: Path delays of routing blocks in the SOFA CHD FPGA + + +---------------------------+------------------------------+ + | Path / Delay | TT (unit: ns) | + +===========================+==============================+ + | A -> B | 1.44 | + +---------------------------+------------------------------+ + | A -> C | 1.44 | + +---------------------------+------------------------------+ + | A -> D | 1.44 | + +---------------------------+------------------------------+ + | B -> E | 1.38 | + +---------------------------+------------------------------+ + diff --git a/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch_timing.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch_timing.svg new file mode 100644 index 0000000..78d1013 --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch_timing.svg @@ -0,0 +1,328 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.4\n2021-04-02 20:32:49 +0000 + + frac_lut4_timing_points + + 图层 1 + + + + + + + + + + + + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + + + + + FF + [0] + + + + + + + + + + + + + + + + + + + + + + + out[0] + + + + + + + + + M + U + X + + + + + + + + + + + + + + + FF + [1] + + + + + + + + + + + + + + + + + + + + + + + out[1] + + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + scin + + + + + + + + + + + scout + + + + + + + + + + + + + + + + + + + + regin + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + + + regout + + + + + CLK + + + + + + + + + + + + + + + + + + + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + + + + A + + + + + diff --git a/DOC/source/datasheet/sofa_hd/figures/sofa_hd_routing_arch.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_routing_arch.svg new file mode 100644 index 0000000..c8464f2 --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_routing_arch.svg @@ -0,0 +1,365 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.4\n2021-04-03 00:25:42 +0000 + + Canvas 1 + + Layer 1 + + + + + + + + + + + Input Pin + + + + + Output Pin + + + + + + + + + + + + + SB MUX + + + + + CB MUX + + + + + Track + + + + + + + + + + CLB + [2][1] + + + + + + + + + + + + + + + + + + + + + + + + + CLB + [1][1] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CLB + [3][1] + + + + + + + + + + + + + + + + + + + + + CLB + [4][1] + + + + + + + + + + + + + + + + + + CLB + [5][1] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + L4 Wire + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + L2 Wire + + + + + L1 Wire + + + + + A + + + + + B + + + + + + + + + C + + + + + D + + + + + E + + + + + diff --git a/DOC/source/datasheet/sofa_hd/index.rst b/DOC/source/datasheet/sofa_hd/index.rst index 8bff100..3b82f44 100644 --- a/DOC/source/datasheet/sofa_hd/index.rst +++ b/DOC/source/datasheet/sofa_hd/index.rst @@ -14,3 +14,5 @@ SOFA HD sofa_hd_clb_arch sofa_hd_circuit_design + + sofa_hd_timing diff --git a/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst b/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst index 5f503c9..9854a4a 100644 --- a/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst +++ b/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst @@ -59,6 +59,47 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra | | | cells. | +------+----------+----------------------------------------------+ +.. _sofa_hd_fpga_arch_routing_arch: + +Routing Architecture +^^^^^^^^^^^^^^^^^^^^ + +The routing architecture is based on uni-directional routing tracks, which are interconnected by routing multiplexers. +:numref:`fig_sofa_hd_routing_arch` illustrates the detailed organization of the routing architecture. + +.. _fig_sofa_hd_routing_arch: + +.. figure:: ./figures/sofa_hd_routing_arch.svg + :width: 80% + :alt: Detailed routing architecture + + Detailed routing architecture + +The routing architecture consists the following type of routing tracks: + +- Length-1 wires (``L1 wires``), which hop over 1 logic block (including I/O block) +- Length-2 wires (``L2 wires``), which hop over 2 logic block (including I/O block) +- Length-4 wires (``L4 wires``), which hop over 4 logic block (including I/O block) + +Each tile includes two routing channels, i.e., the X-direction routing channel and the Y-direction routing channel, providing horizental and vertical connections to adjacent tiles. +Each routing channel consists of 40 routing tracks. See details in :numref:`table_sofa_hd_fpga_arch_routing_track_distribution`. + +.. _table_sofa_hd_fpga_arch_routing_track_distribution: + +.. table:: Routing track distribution of SOFA HD FPGA + + +------------+------------------------------+ + | Track type | Number of tracks per channel | + +============+==============================+ + | Length-1 | 4 (10%) | + +------------+------------------------------+ + | Length-2 | 4 (10%) | + +------------+------------------------------+ + | Length-4 | 32 (80%) | + +------------+------------------------------+ + | Total | 40 | + +------------+------------------------------+ + .. _sofa_hd_fpga_arch_scan_chain: Scan-chain diff --git a/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst b/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst new file mode 100644 index 0000000..731eb72 --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst @@ -0,0 +1,112 @@ +.. _sofa_hd_timing: + +Timing Annotation +----------------- + +.. _sofa_hd_timing_clb: + +Configurable Logic Block +^^^^^^^^^^^^^^^^^^^^^^^^ + +The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`. + +.. _fig_sofa_hd_fle_arch_timing: + +.. figure:: ./figures/sofa_hd_fle_arch_timing.svg + :scale: 30% + :alt: Schematic of a logic element used in SOFA HD FPGA + + Schematic of a logic element used in SOFA HD FPGA + +.. _table_sofa_hd_fle_arch_timing: + +.. table:: Path delays of logic element in the SOFA HD FPGA + + +-------------------------+------------------------------+ + | Path / Delay | TT (unit: ns) | + +=========================+==============================+ + | in0 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in1 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in2 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in0 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in1 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in2 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in0 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in1 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in2 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in3 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | LUT3_out[0] -> A | 0.56 | + +-------------------------+------------------------------+ + | LUT4_out[0] -> A | 0.58 | + +-------------------------+------------------------------+ + | A -> out[0] | 0.88 | + +-------------------------+------------------------------+ + | A -> FF[0] | 0.56 | + +-------------------------+------------------------------+ + | FF[0] -> out[0] | 0.88 | + +-------------------------+------------------------------+ + | LUT3_out[1] -> out[1] | 0.89 | + +-------------------------+------------------------------+ + | LUT3_out[1] -> FF[1] | 0.56 | + +-------------------------+------------------------------+ + | FF[1] -> out[1] | 0.89 | + +-------------------------+------------------------------+ + | regin -> FF[0] | 0.58 | + +-------------------------+------------------------------+ + | FF[0] -> FF[1] | 0.56 | + +-------------------------+------------------------------+ + +.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques. + +.. _sofa_hd_timing_io: + +I/O Block +^^^^^^^^^ + +The path delays in :numref:`fig_sofa_hd_embedded_io_schematic` are listed in :numref:`table_sofa_hd_io_timing`. + +.. _table_sofa_hd_io_timing: + +.. table:: Path delays of I/O circuit in the SOFA HD FPGA + + +-------------------------+------------------------------+ + | Path / Delay | TT (unit: ns) | + +=========================+==============================+ + | SOC_IN -> FPGA_IN | 0.11 | + +-------------------------+------------------------------+ + | FPGA_OUT -> SOC_OUT | 0.11 | + +-------------------------+------------------------------+ + +.. _sofa_hd_timing_routing: + +Routing Architecture +^^^^^^^^^^^^^^^^^^^^ + +The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`table_sofa_hd_routing_arch_timing`. + +.. _table_sofa_hd_routing_arch_timing: + +.. table:: Path delays of routing blocks in the SOFA HD FPGA + + +---------------------------+------------------------------+ + | Path / Delay | TT (unit: ns) | + +===========================+==============================+ + | A -> B | 1.61 | + +---------------------------+------------------------------+ + | A -> C | 1.61 | + +---------------------------+------------------------------+ + | A -> D | 1.61 | + +---------------------------+------------------------------+ + | B -> E | 1.38 | + +---------------------------+------------------------------+ + diff --git a/DOC/source/device/hd_fpga/figures/qlsofa_hd_layout.png b/DOC/source/device/hd_fpga/figures/qlsofa_hd_layout.png new file mode 100644 index 0000000..61d666f Binary files /dev/null and b/DOC/source/device/hd_fpga/figures/qlsofa_hd_layout.png differ diff --git a/DOC/source/device/hd_fpga/figures/sofa_chd_layout.png b/DOC/source/device/hd_fpga/figures/sofa_chd_layout.png new file mode 100644 index 0000000..a8672b5 Binary files /dev/null and b/DOC/source/device/hd_fpga/figures/sofa_chd_layout.png differ diff --git a/DOC/source/device/hd_fpga/figures/sofa_hd_layout.png b/DOC/source/device/hd_fpga/figures/sofa_hd_layout.png new file mode 100644 index 0000000..579c431 Binary files /dev/null and b/DOC/source/device/hd_fpga/figures/sofa_hd_layout.png differ diff --git a/DOC/source/device/hd_fpga/hd_device_gallery.rst b/DOC/source/device/hd_fpga/hd_device_gallery.rst new file mode 100644 index 0000000..fc5e43d --- /dev/null +++ b/DOC/source/device/hd_fpga/hd_device_gallery.rst @@ -0,0 +1,39 @@ +.. _hd_fpga_device_gallery: + +Chip Gallery +------------ + +Here lists the images of each HD FPGA chips + +SOFA HD +^^^^^^^ + +SOFA HD is the base design of the SOFA high-density eFPGA IPs + +.. figure:: ./figures/sofa_hd_layout.png + :scale: 100% + :alt: Layout view of SOFA HD device in Caravel SoC + + Layout view of SOFA HD device in Caravel SoC + +QLSOFA HD +^^^^^^^^^ + +QLSOFA HD is the arithmetic-enhanced design of the SOFA high-density eFPGA IPs + +.. figure:: ./figures/qlsofa_hd_layout.png + :scale: 100% + :alt: Layout view of QLSOFA HD device in Caravel SoC + + Layout view of QLSOFA HD device in Caravel SoC + +SOFA CHD +^^^^^^^^ + +SOFA CHD is the performance-optimized design of the SOFA high-density eFPGA IPs + +.. figure:: ./figures/sofa_chd_layout.png + :scale: 100% + :alt: Layout view of SOFA CHD device in Caravel SoC + + Layout view of SOFA CHD device in Caravel SoC diff --git a/DOC/source/device/hd_fpga/index.rst b/DOC/source/device/hd_fpga/index.rst index a6802e3..dc6f0d1 100644 --- a/DOC/source/device/hd_fpga/index.rst +++ b/DOC/source/device/hd_fpga/index.rst @@ -10,3 +10,5 @@ HD FPGAs hd_device_comp hd_device_dcac + + hd_device_gallery diff --git a/DOC/source/device/introduction.rst b/DOC/source/device/introduction.rst index 8c43329..6bda114 100644 --- a/DOC/source/device/introduction.rst +++ b/DOC/source/device/introduction.rst @@ -17,4 +17,3 @@ We aims to empower embedded applications with its low-cost design approach but h :alt: 24-hour FPGA IP development: from PDK to production-ready layout 24-hour FPGA IP development: from PDK to production-ready layout - diff --git a/README.md b/README.md index b7e40f0..5640f1c 100644 --- a/README.md +++ b/README.md @@ -4,7 +4,20 @@ ## Introduction -SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework +SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework. + +This repository provide the following support for the eFPGA IPs +- **Architecture description file** : Users can inspect architecture details and try architecture evalution using the [VTR project](https://github.com/verilog-to-routing/vtr-verilog-to-routing) and the [OpenFPGA project](https://github.com/lnis-uofu/OpenFPGA). +- **Fabrication-ready GDSII layouts**: Users can integrate to their chip designs. +- **Post-layout Verilog Netlists**: Users can run HDL simulations on the eFPGA IPs to validate their applications +- **Benchmark suites**: An example benchmarking suite with which users can run quick examples on the eFPGA IPs +- **Documentation**: Datasheets for each eFPGA IPs downto circuit-level details + +

+ + + +

## Quick Start @@ -22,6 +35,11 @@ python3 SCRIPT/repo_setup.py --openfpga_root_path ${OPENFPGA_PROJECT_DIRECTORY} Otherwise, you should provide full path using the option _--openfpga\_root\_path_ + +## Chip Gallery + +You can find a chip gallery in the online documentation. + ## Directory Organization * Keep this folder clean and organized as follows diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga new file mode 100644 index 0000000..295c863 --- /dev/null +++ b/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga @@ -0,0 +1,49 @@ +# This script is designed to generate bitstream +# with a fixed device layout, which can be used for bitstream loaders +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup #--verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +# - Enabled frame view creation to save runtime and memory +# Note that this is turned on when bitstream generation +# is the ONLY purpose of the flow!!! +build_fabric --compress_routing --duplicate_grid_pin --frame_view --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file arch_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.txt --format plain_text +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Finish and exit OpenFPGA +exit diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_bitstream/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_bitstream/config/task_template.conf new file mode 100644 index 0000000..da59633 --- /dev/null +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_bitstream/config/task_template.conf @@ -0,0 +1,53 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml + +[OpenFPGA_SHELL] +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga +openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml +openfpga_vpr_device_layout=12x12 +openfpga_vpr_route_chan_width=40 +external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml + +[ARCHITECTURES] +arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v +bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v +bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v +bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v +bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v +# RS decoder needs 1.5k LUT4, exceeding device capacity +#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v +bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v +bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench1_top = and2_latch +bench2_top = bin2bcd +bench3_top = counter +bench4_top = routing_test +# RS decoder needs 1.5k LUT4, exceeding device capacity +#bench5_top = rs_decoder_top +bench6_top = top_module +bench7_top = and2_or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf index 222aee6..83177c0 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf index 24bc072..4e4f773 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf index 8ffa663..8549248 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf index 5c2cfba..63edfe6 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf index 78f595f..5a0c479 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf index fced52c..1e0ba61 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_bitstream/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_bitstream/config/task_template.conf new file mode 100644 index 0000000..770d490 --- /dev/null +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_bitstream/config/task_template.conf @@ -0,0 +1,53 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml + +[OpenFPGA_SHELL] +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga +openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml +openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml +openfpga_vpr_device_layout=12x12 +openfpga_vpr_route_chan_width=60 +external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml + +[ARCHITECTURES] +arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v +bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v +bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v +bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v +bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v +# RS decoder needs 1.5k LUT4, exceeding device capacity +#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v +bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v +bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench1_top = and2_latch +bench2_top = bin2bcd +bench3_top = counter +bench4_top = routing_test +# RS decoder needs 1.5k LUT4, exceeding device capacity +#bench5_top = rs_decoder_top +bench6_top = top_module +bench7_top = and2_or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf index cd63b08..313ec0a 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf index 4c9c449..f9ce99e 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf index 10575fb..91083ef 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_bitstream/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_bitstream/config/task_template.conf new file mode 100644 index 0000000..9a4a1a0 --- /dev/null +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_bitstream/config/task_template.conf @@ -0,0 +1,53 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml + +[OpenFPGA_SHELL] +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga +openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml +openfpga_vpr_device_layout=12x12 +openfpga_vpr_route_chan_width=60 +external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml + +[ARCHITECTURES] +arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v +bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v +bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v +bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v +bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v +# RS decoder needs 1.5k LUT4, exceeding device capacity +#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v +bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v +bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench1_top = and2_latch +bench2_top = bin2bcd +bench3_top = counter +bench4_top = routing_test +# RS decoder needs 1.5k LUT4, exceeding device capacity +#bench5_top = rs_decoder_top +bench6_top = top_module +bench7_top = and2_or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf index cb4179f..c91fba3 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf index ce0d515..53e507b 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf index 8af1f08..0ac1d09 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task_template.conf index cbd69be..e688b5b 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task_template.conf @@ -23,6 +23,8 @@ openfpga_vpr_device_layout=32x32 openfpga_vpr_route_chan_width=60 openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32x32.xml +# Yosys parameters +yosys_args = -no_adder -family qlf_k4n8 -no_ff_map [ARCHITECTURES] arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -32,7 +34,7 @@ bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/io_reg/io_reg.v [SYNTHESIS_PARAM] bench0_top = io_reg -bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] #end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf index fce1c3d..4ea34af 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf @@ -24,6 +24,8 @@ openfpga_vpr_route_chan_width=60 openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc/prepnr openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc/SRC/fabric_netlists.v external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32x32.xml +# Yosys parameters +yosys_args = -no_adder -family qlf_k4n8 -no_ff_map [ARCHITECTURES] arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -38,7 +40,8 @@ bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v -bench8=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/cavlc_top/rtl/*.v +# Skip cavlc benchmark because current yosys script failed in DFF mapping; Problem should be solved once the yosys script is updated +#bench8=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/cavlc_top/rtl/*.v #bench9=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/cf_fft_256_8/rtl/*.v bench10=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter120bitx5/rtl/*.v bench11=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter_16bit/rtl/*.v @@ -47,7 +50,8 @@ bench12=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/dct_mac/rtl/*.v bench14=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/diffeq_f_systemC/rtl/*.v #bench15=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/i2c_master_top/rtl/*.v #bench16=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/iir/rtl/*.v -bench17=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/jpeg_qnr/rtl/*.v +# Skip jpeg_qnr benchmark because current yosys script failed in DFF mapping; Problem should be solved once the yosys script is updated +#bench17=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/jpeg_qnr/rtl/*.v bench18=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/multi_enc_decx2x4/rtl/*.v #bench19=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/sdc_controller/rtl/*.v bench20=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/sha256/rtl/*.v @@ -56,47 +60,47 @@ bench22=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/io_tc1/rtl/*.v [SYNTHESIS_PARAM] bench0_top = and2 -bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench1_top = and2_latch -bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench2_top = bin2bcd -bench2_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench2_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench3_top = counter -bench3_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench3_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench4_top = routing_test -bench4_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench4_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys # RS decoder needs 1.5k LUT4, exceeding device capacity bench5_top = rs_decoder_top -bench5_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench5_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench6_top = top_module -bench6_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench6_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench7_top = and2_or2 -bench7_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench7_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench8_top = cavlc_top -bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys #bench9_top = cf_fft_256_8 bench10_top = counter120bitx5 -bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench11_top = top -bench11_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench11_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench12_top = dct_mac -bench12_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench12_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys #bench13_top = des_perf bench14_top = diffeq_f_systemC -bench14_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench14_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys #bench15_top = i2c_master_top #bench16_top = iir bench17_top = jpeg_qnr -bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench18_top = multi_enc_decx2x4 -#bench18_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +#bench18_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys #bench19_top = sdc_controller bench20_top = sha256 -bench20_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench20_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench21_top = unsigned_mult_80 -bench21_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench21_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench22_top = io_tc1 -bench22_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +bench22_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] #end_flow_with_test= diff --git a/SNPS_PT/SCRIPT/report_timing_cb.tcl b/SNPS_PT/SCRIPT/report_timing_cb.tcl new file mode 100644 index 0000000..fd5fb73 --- /dev/null +++ b/SNPS_PT/SCRIPT/report_timing_cb.tcl @@ -0,0 +1,85 @@ +##################################################################### +# A template script to report timing for Connection Blocks from post-PnR results +# using Synopsys PrimeTime +##################################################################### +# +################################## +# Define environment variables +set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; + +#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; +set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; +#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; + +#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; +#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; + +#set DEVICE_NAME "SOFA_HD" +set DEVICE_NAME "QLSOFA_HD" +#set DEVICE_NAME "SOFA_CHD" + +set TIMING_REPORT_HOME "../TIMING_REPORTS/"; + +# Enable preprocessing in Verilog parser +set_app_var svr_enable_vpp true +# Enable reporting ALL the timing paths even those are NOT constrained +set_app_var timing_report_unconstrained_paths true + +set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" + +set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" + +set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" + +################################## +# Sweep all the CB design +set DESIGN_NAMES {"cbx_1__0_" "cbx_1__1_" "cbx_1__2_" "cby_0__1_" "cby_1__1_" "cby_2__1_"}; +foreach DESIGN_NAME ${DESIGN_NAMES} { + + ################################## + # Ensure a clean start + remove_design -all + remove_lib -all + + ################################## + # Read timing libraries + read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" + + ################################## + # Read post-PnR netlists + read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES} + link_design ${DESIGN_NAME} + + ######################################### + # Setup constraints to break combinational loops + #source ${SDC_HOME}/disable_configurable_memory_outputs.sdc + set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D + + ######################################### + # Setup constraints for clocks + #source ${SDC_HOME}/global_ports.sdc + + ######################################### + # Setup constraints for paths + # Connection block name + set CB_CHAN_NAME "chan*"; + set CB_PIN_NAME "*grid_pin*"; + set_max_delay -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} 6.02e-11 + set_max_delay -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} 6.02e-11 + + ################################## + # Read post-PnR parasitics + read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef + + ################################## + # Report timing of Connect block + report_timing -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt + report_timing -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt + +} + +################################## +# Finish and quit +# Comment it out if you want to debug +exit diff --git a/SNPS_PT/SCRIPT/report_timing_clb.tcl b/SNPS_PT/SCRIPT/report_timing_clb.tcl new file mode 100644 index 0000000..91a7314 --- /dev/null +++ b/SNPS_PT/SCRIPT/report_timing_clb.tcl @@ -0,0 +1,95 @@ +##################################################################### +# A template script to report timing for A CLB from post-PnR results +# using Synopsys PrimeTime +##################################################################### + +################################## +# Define environment variables +set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; + +#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; +set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; +#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; + +#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; +#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; + +#set DEVICE_NAME "SOFA_HD" +set DEVICE_NAME "QLSOFA_HD" +#set DEVICE_NAME "SOFA_CHD" + +set TIMING_REPORT_HOME "../TIMING_REPORTS/"; + +# Enable preprocessing in Verilog parser +set_app_var svr_enable_vpp true +# Enable reporting ALL the timing paths even those are NOT constrained +set_app_var timing_report_unconstrained_paths tr + +set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" + +set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" + +set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" + +################################## +# Ensure a clean start +remove_design -all +remove_lib -all + +################################## +# Read timing libraries +read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" + +################################## +# Read post-PnR netlists +read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES} +# Top-level module name +set DESIGN_NAME "grid_clb"; + +link_design ${DESIGN_NAME} + +######################################### +# Setup constraints to break combinational loops +if {${DEVICE_NAME} eq "SOFA_HD"} { + set_disable_timing */*/*/mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q +} else { + # QLSOFA and SOFA CHD use a LUT with carry logic, the memory is deeper in hierarchy + # Also QLSOFA and SOFA CHD use a different FF cell as configuration memory + set_disable_timing */*/*/*/*/*mem/sky*_fd_sc_hd__dfrtp_*_*_/Q +} +# +########################################## +## Setup constraints for clocks + +########################################## +## Setup constraints for paths + +################################## +# Read post-PnR parasitics +read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef + +################################## +# Report timing of Connect block +# LUT4 output timing +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/in -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut4_out > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut4_timing.rpt +# LUT3 output timing +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/in -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut3_timing.rpt + +# Output selector timing +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[1] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt + +# LUT output to FF input timing +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut4_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt + +# TODO: Carry logic timing + +################################## +# Finish and quit +# Comment it out if you want to debug +exit diff --git a/SNPS_PT/SCRIPT/report_timing_io.tcl b/SNPS_PT/SCRIPT/report_timing_io.tcl new file mode 100644 index 0000000..5714dfc --- /dev/null +++ b/SNPS_PT/SCRIPT/report_timing_io.tcl @@ -0,0 +1,76 @@ +##################################################################### +# A template script to report timing for A CLB from post-PnR results +# using Synopsys PrimeTime +##################################################################### + +################################## +# Define environment variables +set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; + +#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; +set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; +#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; + +#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; +#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; + +#set DEVICE_NAME "SOFA_HD" +set DEVICE_NAME "QLSOFA_HD" +#set DEVICE_NAME "SOFA_CHD" + +set TIMING_REPORT_HOME "../TIMING_REPORTS/"; + +# Enable preprocessing in Verilog parser +set_app_var svr_enable_vpp true +# Enable reporting ALL the timing paths even those are NOT constrained +set_app_var timing_report_unconstrained_paths tr + +set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" + +set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" + +set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" + +################################## +# Ensure a clean start +remove_design -all +remove_lib -all + +################################## +# Read timing libraries +read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" + +################################## +# Read post-PnR netlists +read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES} +# Top-level module name +# May sweep for all the io modules +set DESIGN_NAME "cbx_1__0__logical_tile_io_mode_physical__iopad_0"; + +link_design ${DESIGN_NAME} + +######################################### +# Setup constraints to break combinational loops +set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q +# +########################################## +## Setup constraints for clocks + +########################################## +## Setup constraints for paths + +################################## +# Read post-PnR parasitics +read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef + +################################## +# Report timing of Connect block +# Inpad -> FPGA timing +report_timing -from gfpga_pad_EMBEDDED_IO_HD_SOC_IN -to iopad_inpad > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt +report_timing -from iopad_outpad -to gfpga_pad_EMBEDDED_IO_HD_SOC_OUT >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt + +################################## +# Finish and quit +# Comment it out if you want to debug +exit diff --git a/SNPS_PT/SCRIPT/report_timing_sb.tcl b/SNPS_PT/SCRIPT/report_timing_sb.tcl new file mode 100644 index 0000000..9e426b7 --- /dev/null +++ b/SNPS_PT/SCRIPT/report_timing_sb.tcl @@ -0,0 +1,83 @@ +##################################################################### +# A template script to report timing for Connection Blocks from post-PnR results +# using Synopsys PrimeTime +##################################################################### + +################################## +# Define environment variables +set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; + +#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; +set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; +#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; + +#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; +#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; + +#set DEVICE_NAME "SOFA_HD" +set DEVICE_NAME "QLSOFA_HD" +#set DEVICE_NAME "SOFA_CHD" + +set TIMING_REPORT_HOME "../TIMING_REPORTS/"; +# Enable preprocessing in Verilog parser +set_app_var svr_enable_vpp true +# Enable reporting ALL the timing paths even those are NOT constrained +set_app_var timing_report_unconstrained_paths tr + +set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" + +set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" + +set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" + +################################## +# Sweep all the SB designs +set DESIGN_NAMES {"sb_1__1_" "sb_0__0_" "sb_0__2_" "sb_0__1_" "sb_2__0_" "sb_2__2_" "sb_2__1_" "sb_1__0_" "sb_1__2_"}; + +foreach DESIGN_NAME ${DESIGN_NAMES} { + + ################################## + # Ensure a clean start + remove_design -all + remove_lib -all + + ################################## + # Read timing libraries + read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" + + ################################## + # Read post-PnR netlists + read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES} + + link_design ${DESIGN_NAME} + + ######################################### + # Setup constraints to break combinational loops + set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D + # + ########################################## + ## Setup constraints for clocks + + ########################################## + ## Setup constraints for paths + ## Switch block name + set SB_CHAN_NAME "chan*"; + set SB_PIN_NAME "*grid_pin*"; + set_max_delay -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} 2.272500113e-12 + set_max_delay -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} 7.247000222e-11 + + ################################## + # Read post-PnR parasitics + read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef + + ################################## + # Report timing of Connect block + report_timing -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt + report_timing -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt +} + +################################## +# Finish and quit +# Comment it out if you want to debug +exit