From 128e8e6aa3a0ddc16f938a0d311b2199b2ec239e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 31 Mar 2021 19:40:36 -0600 Subject: [PATCH 01/24] [Script] Add report timing script for connection blocks --- SNPS_PT/SCRIPT/report_timing_cb.tcl | 87 +++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 SNPS_PT/SCRIPT/report_timing_cb.tcl diff --git a/SNPS_PT/SCRIPT/report_timing_cb.tcl b/SNPS_PT/SCRIPT/report_timing_cb.tcl new file mode 100644 index 0000000..948fcdb --- /dev/null +++ b/SNPS_PT/SCRIPT/report_timing_cb.tcl @@ -0,0 +1,87 @@ +##################################################################### +# A template script to report timing for Connection Blocks from post-PnR results +# using Synopsys PrimeTime +##################################################################### + +################################## +# Ensure a clean start +remove_design -all +remove_lib -all + +################################## +# Define environment variables +set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; +set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; +set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +set DEVICE_NAME "SOFA" +set TIMING_REPORT_HOME "../TIMING_REPORTS/"; +# Enable preprocessing in Verilog parser +set_app_var svr_enable_vpp true +# Enable reporting ALL the timing paths even those are NOT constrained +set_app_var timing_report_unconstrained_paths tr + +set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" + +set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" + + +set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" + +################################## +# Read timing libraries +read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" + +################################## +# Read post-PnR netlists +read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES} +# Top-level module name +set DESIGN_NAME fpga_top; +#set DESIGN_NAME fpga_core; +link_design ${DESIGN_NAME} + +######################################### +# Setup constraints to break combinational loops +#source ${SDC_HOME}/disable_configurable_memory_outputs.sdc +set_disable_timing [get_pins */*/*chan*] +set_disable_timing [get_pins */*/*grid_pin*] + +######################################### +# Setup constraints for clocks +#source ${SDC_HOME}/global_ports.sdc + +################################################## +# Create programmable clock +################################################## +create_clock -name prog_clk[0] -period 1.999999988e-08 -waveform {0 9.999999939e-09} [get_ports {io_in[37]}] +################################################## +# Create clock +################################################## +create_clock -name clk[0] -period 1.999999988e-08 -waveform {0 9.999999939e-09} [get_ports {io_in[36]}] + +######################################### +# Setup constraints for paths +# Connection block name +set CB_NAME "cbx_1__0_"; +#set CB_NAME "cbx_1__1_"; +#set CB_NAME "cbx_1__12_"; +#set CB_NAME "cby_0__1_"; +#set CB_NAME "cby_1__1_"; +#set CB_NAME "cby_12__1_"; +set CB_CHAN_NAME "chan*"; +set CB_PIN_NAME "*grid_pin*"; +set_max_delay -from fpga_core_uut/${CB_NAME}/${CB_CHAN_NAME} -to fpga_core_uut/${CB_NAME}/${CB_CHAN_NAME} 2.272500113e-12 +set_max_delay -from fpga_core_uut/${CB_NAME}/${CB_CHAN_NAME} -to fpga_core_uut/${CB_NAME}/${CB_PIN_NAME} 7.247000222e-11 + +################################## +# Read post-PnR parasitics +#read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef + +################################## +# Report timing of Connect block +report_timing -from fpga_core_uut/${CB_NAME}/${CB_CHAN_NAME} -to fpga_core_uut/${CB_NAME}/${CB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${CB_NAME}_timing.rpt +report_timing -from fpga_core_uut/${CB_NAME}/${CB_CHAN_NAME} -to fpga_core_uut/${CB_NAME}/${CB_PIN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${CB_NAME}_timing.rpt + +################################## +# Finish and quit +# Comment it out if you want to debug +#exit From 17033730fef0f609e573321c71eb63bbc91e0e37 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 14:38:07 -0600 Subject: [PATCH 02/24] [Script] Update report timing script for CBs --- SNPS_PT/SCRIPT/report_timing_cb.tcl | 38 ++++++++++------------------- 1 file changed, 13 insertions(+), 25 deletions(-) diff --git a/SNPS_PT/SCRIPT/report_timing_cb.tcl b/SNPS_PT/SCRIPT/report_timing_cb.tcl index 948fcdb..4e34ef4 100644 --- a/SNPS_PT/SCRIPT/report_timing_cb.tcl +++ b/SNPS_PT/SCRIPT/report_timing_cb.tcl @@ -35,53 +35,41 @@ read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm # Read post-PnR netlists read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES} # Top-level module name -set DESIGN_NAME fpga_top; -#set DESIGN_NAME fpga_core; +#set DESIGN_NAME "cbx_1__0_"; +#set DESIGN_NAME "cbx_1__1_"; +#set DESIGN_NAME "cbx_1__12_"; +#set DESIGN_NAME "cby_0__1_"; +#set DESIGN_NAME "cby_1__1_"; +set DESIGN_NAME "cby_12__1_"; link_design ${DESIGN_NAME} ######################################### # Setup constraints to break combinational loops #source ${SDC_HOME}/disable_configurable_memory_outputs.sdc -set_disable_timing [get_pins */*/*chan*] -set_disable_timing [get_pins */*/*grid_pin*] +set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D ######################################### # Setup constraints for clocks #source ${SDC_HOME}/global_ports.sdc -################################################## -# Create programmable clock -################################################## -create_clock -name prog_clk[0] -period 1.999999988e-08 -waveform {0 9.999999939e-09} [get_ports {io_in[37]}] -################################################## -# Create clock -################################################## -create_clock -name clk[0] -period 1.999999988e-08 -waveform {0 9.999999939e-09} [get_ports {io_in[36]}] - ######################################### # Setup constraints for paths # Connection block name -set CB_NAME "cbx_1__0_"; -#set CB_NAME "cbx_1__1_"; -#set CB_NAME "cbx_1__12_"; -#set CB_NAME "cby_0__1_"; -#set CB_NAME "cby_1__1_"; -#set CB_NAME "cby_12__1_"; set CB_CHAN_NAME "chan*"; set CB_PIN_NAME "*grid_pin*"; -set_max_delay -from fpga_core_uut/${CB_NAME}/${CB_CHAN_NAME} -to fpga_core_uut/${CB_NAME}/${CB_CHAN_NAME} 2.272500113e-12 -set_max_delay -from fpga_core_uut/${CB_NAME}/${CB_CHAN_NAME} -to fpga_core_uut/${CB_NAME}/${CB_PIN_NAME} 7.247000222e-11 +set_max_delay -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} 6.02e-11 +set_max_delay -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} 6.02e-11 ################################## # Read post-PnR parasitics -#read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef +read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef ################################## # Report timing of Connect block -report_timing -from fpga_core_uut/${CB_NAME}/${CB_CHAN_NAME} -to fpga_core_uut/${CB_NAME}/${CB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${CB_NAME}_timing.rpt -report_timing -from fpga_core_uut/${CB_NAME}/${CB_CHAN_NAME} -to fpga_core_uut/${CB_NAME}/${CB_PIN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${CB_NAME}_timing.rpt +report_timing -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt +report_timing -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt ################################## # Finish and quit # Comment it out if you want to debug -#exit +exit From a640f589eaac4bf59d152d89dbd74ba516700a10 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 14:45:00 -0600 Subject: [PATCH 03/24] [Script] Add report timing script for switch blocks --- SNPS_PT/SCRIPT/report_timing_sb.tcl | 76 +++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 SNPS_PT/SCRIPT/report_timing_sb.tcl diff --git a/SNPS_PT/SCRIPT/report_timing_sb.tcl b/SNPS_PT/SCRIPT/report_timing_sb.tcl new file mode 100644 index 0000000..5a6c846 --- /dev/null +++ b/SNPS_PT/SCRIPT/report_timing_sb.tcl @@ -0,0 +1,76 @@ +##################################################################### +# A template script to report timing for Connection Blocks from post-PnR results +# using Synopsys PrimeTime +##################################################################### + +################################## +# Ensure a clean start +remove_design -all +remove_lib -all + +################################## +# Define environment variables +set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; +set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; +set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +set DEVICE_NAME "SOFA" +set TIMING_REPORT_HOME "../TIMING_REPORTS/"; +# Enable preprocessing in Verilog parser +set_app_var svr_enable_vpp true +# Enable reporting ALL the timing paths even those are NOT constrained +set_app_var timing_report_unconstrained_paths tr + +set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" + +set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" + +set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" + +################################## +# Read timing libraries +read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" + +################################## +# Read post-PnR netlists +read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES} +# Top-level module name +#set DESIGN_NAME sb_1__1_; +#set DESIGN_NAME "sb_0__0_"; +#set DESIGN_NAME "sb_0__2_"; +#set DESIGN_NAME "sb_0__1_"; +#set DESIGN_NAME "sb_2__0_"; +#set DESIGN_NAME "sb_2__2_"; +#set DESIGN_NAME "sb_2__1_"; +#set DESIGN_NAME "sb_1__0_"; +set DESIGN_NAME "sb_1__2_"; + +link_design ${DESIGN_NAME} + +######################################### +# Setup constraints to break combinational loops +set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D +# +########################################## +## Setup constraints for clocks + +########################################## +## Setup constraints for paths +## Switch block name +set SB_CHAN_NAME "chan*"; +set SB_PIN_NAME "*grid_pin*"; +set_max_delay -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} 2.272500113e-12 +set_max_delay -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} 7.247000222e-11 + +################################## +# Read post-PnR parasitics +read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef + +################################## +# Report timing of Connect block +report_timing -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt +report_timing -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt + +################################## +# Finish and quit +# Comment it out if you want to debug +exit From 3ed41a47047150cfc588d1522a976f9d88c78668 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 15:43:51 -0600 Subject: [PATCH 04/24] [Script] Add report timing script for CLB --- SNPS_PT/SCRIPT/report_timing_clb.tcl | 76 ++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 SNPS_PT/SCRIPT/report_timing_clb.tcl diff --git a/SNPS_PT/SCRIPT/report_timing_clb.tcl b/SNPS_PT/SCRIPT/report_timing_clb.tcl new file mode 100644 index 0000000..80afddd --- /dev/null +++ b/SNPS_PT/SCRIPT/report_timing_clb.tcl @@ -0,0 +1,76 @@ +##################################################################### +# A template script to report timing for A CLB from post-PnR results +# using Synopsys PrimeTime +##################################################################### + +################################## +# Ensure a clean start +remove_design -all +remove_lib -all + +################################## +# Define environment variables +set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; +set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; +set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +set DEVICE_NAME "SOFA" +set TIMING_REPORT_HOME "../TIMING_REPORTS/"; +# Enable preprocessing in Verilog parser +set_app_var svr_enable_vpp true +# Enable reporting ALL the timing paths even those are NOT constrained +set_app_var timing_report_unconstrained_paths tr + +set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" + +set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" + +set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" + +################################## +# Read timing libraries +read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" + +################################## +# Read post-PnR netlists +read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES} +# Top-level module name +set DESIGN_NAME "grid_clb"; + +link_design ${DESIGN_NAME} + +######################################### +# Setup constraints to break combinational loops +set_disable_timing */*/*/mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q +# +########################################## +## Setup constraints for clocks + +########################################## +## Setup constraints for paths + +################################## +# Read post-PnR parasitics +read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef + +################################## +# Report timing of Connect block +# LUT4 output timing +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/in -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut4_out > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut4_timing.rpt +# LUT3 output timing +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/in -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut3_timing.rpt + +# Output selector timing +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[1] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt + +# LUT output to FF input timing +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut4_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt +report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt + +################################## +# Finish and quit +# Comment it out if you want to debug +exit From 0ba5ec9b93f8056afe39b2a97d3f4550f7144f17 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 15:58:54 -0600 Subject: [PATCH 05/24] [Script] Add report timing script for I/O --- SNPS_PT/SCRIPT/report_timing_io.tcl | 64 +++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 SNPS_PT/SCRIPT/report_timing_io.tcl diff --git a/SNPS_PT/SCRIPT/report_timing_io.tcl b/SNPS_PT/SCRIPT/report_timing_io.tcl new file mode 100644 index 0000000..7586457 --- /dev/null +++ b/SNPS_PT/SCRIPT/report_timing_io.tcl @@ -0,0 +1,64 @@ +##################################################################### +# A template script to report timing for A CLB from post-PnR results +# using Synopsys PrimeTime +##################################################################### + +################################## +# Ensure a clean start +remove_design -all +remove_lib -all + +################################## +# Define environment variables +set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; +set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; +set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +set DEVICE_NAME "SOFA" +set TIMING_REPORT_HOME "../TIMING_REPORTS/"; +# Enable preprocessing in Verilog parser +set_app_var svr_enable_vpp true +# Enable reporting ALL the timing paths even those are NOT constrained +set_app_var timing_report_unconstrained_paths tr + +set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" + +set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" + +set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" + +################################## +# Read timing libraries +read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" + +################################## +# Read post-PnR netlists +read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES} +# Top-level module name +set DESIGN_NAME "cbx_1__0__logical_tile_io_mode_physical__iopad_0"; + +link_design ${DESIGN_NAME} + +######################################### +# Setup constraints to break combinational loops +set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q +# +########################################## +## Setup constraints for clocks + +########################################## +## Setup constraints for paths + +################################## +# Read post-PnR parasitics +read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef + +################################## +# Report timing of Connect block +# Inpad -> FPGA timing +report_timing -from gfpga_pad_EMBEDDED_IO_HD_SOC_IN -to iopad_inpad > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt +report_timing -from iopad_outpad -to gfpga_pad_EMBEDDED_IO_HD_SOC_OUT >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt + +################################## +# Finish and quit +# Comment it out if you want to debug +exit From 1b59daebc6591301d06c65a46934262bc6815648 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 15:59:33 -0600 Subject: [PATCH 06/24] [Script] Add comments --- SNPS_PT/SCRIPT/report_timing_io.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/SNPS_PT/SCRIPT/report_timing_io.tcl b/SNPS_PT/SCRIPT/report_timing_io.tcl index 7586457..57f0465 100644 --- a/SNPS_PT/SCRIPT/report_timing_io.tcl +++ b/SNPS_PT/SCRIPT/report_timing_io.tcl @@ -34,6 +34,7 @@ read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm # Read post-PnR netlists read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES} # Top-level module name +# May sweep for all the io modules set DESIGN_NAME "cbx_1__0__logical_tile_io_mode_physical__iopad_0"; link_design ${DESIGN_NAME} From 062120ffd9c9e6e301a20425c90a8ddd06232055 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 16:39:19 -0600 Subject: [PATCH 07/24] [Arch] Update timing for SOFA architecture --- ...n_chain_nonLR_caravel_io_skywater130nm.xml | 189 +++++++----------- 1 file changed, 75 insertions(+), 114 deletions(-) diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index 21f4189..622dd8b 100644 --- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -11,6 +11,9 @@ - 80% L = 4, fc_in = 0.15, Fc_out = 0.10 - 100 routing tracks per channel + - The timing is extracted from a TT corner (1.8V, 25C) + - TODO: Add multi-corners, in particular, SS corner + Authors: Xifan Tang --> @@ -186,21 +189,6 @@ - - - - + + + + - + - + - + 1 1 1 - + 1 1 1 1 1 - + 1 1 1 1 1 1 1 1 1 @@ -277,18 +256,17 @@ - + - + @@ -296,7 +274,7 @@ - + @@ -306,7 +284,7 @@ - + @@ -386,9 +364,9 @@ - - - + + + @@ -398,22 +376,22 @@ - - + + - - + + - - + + - - + + @@ -443,18 +421,10 @@ - - 235e-12 - 235e-12 - 235e-12 + 2.31e-9 + 2.31e-9 + 2.31e-9 @@ -462,20 +432,22 @@ - - + + + + - - - + + + @@ -505,20 +477,11 @@ - - 261e-12 - 261e-12 - 261e-12 - 261e-12 + 2.6e-9 + 2.6e-9 + 2.6e-9 + 2.6e-9 @@ -526,20 +489,22 @@ - - + + + + - - - + + + @@ -561,15 +526,27 @@ - - + + - - + + + + + + + + - - + + + + + + + + @@ -591,52 +568,36 @@ I[0] should be connected to in[0] --> - - - - - - - - - - - - - - - - @@ -650,7 +611,7 @@ - + @@ -662,7 +623,7 @@ - + From 7b49fa06842e1ef540bb737321dfa7d0db4dd7bb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 17:53:53 -0600 Subject: [PATCH 08/24] [Script] Update report timing script for connection blocks so that timing reports are generated in 1 shot --- SNPS_PT/SCRIPT/report_timing_cb.tcl | 107 +++++++++++++++------------- 1 file changed, 56 insertions(+), 51 deletions(-) diff --git a/SNPS_PT/SCRIPT/report_timing_cb.tcl b/SNPS_PT/SCRIPT/report_timing_cb.tcl index 4e34ef4..c507922 100644 --- a/SNPS_PT/SCRIPT/report_timing_cb.tcl +++ b/SNPS_PT/SCRIPT/report_timing_cb.tcl @@ -2,72 +2,77 @@ # A template script to report timing for Connection Blocks from post-PnR results # using Synopsys PrimeTime ##################################################################### - -################################## -# Ensure a clean start -remove_design -all -remove_lib -all - +# ################################## # Define environment variables set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; -set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; -set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; -set DEVICE_NAME "SOFA" +#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; +set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; +#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; +#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; +#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; +#set DEVICE_NAME "SOFA_HD" +set DEVICE_NAME "QLSOFA_HD" +#set DEVICE_NAME "SOFA_CHD" set TIMING_REPORT_HOME "../TIMING_REPORTS/"; # Enable preprocessing in Verilog parser set_app_var svr_enable_vpp true # Enable reporting ALL the timing paths even those are NOT constrained -set_app_var timing_report_unconstrained_paths tr +set_app_var timing_report_unconstrained_paths true set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" - set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" - + ################################## -# Read timing libraries -read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" +# Sweep all the CB design +set DESIGN_NAMES {"cbx_1__0_" "cbx_1__1_" "cbx_1__2_" "cby_0__1_" "cby_1__1_" "cby_2__1_"}; +foreach DESIGN_NAME ${DESIGN_NAMES} { + + ################################## + # Ensure a clean start + remove_design -all + remove_lib -all + + ################################## + # Read timing libraries + read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" + + ################################## + # Read post-PnR netlists + read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES} + link_design ${DESIGN_NAME} + + ######################################### + # Setup constraints to break combinational loops + #source ${SDC_HOME}/disable_configurable_memory_outputs.sdc + set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D + + ######################################### + # Setup constraints for clocks + #source ${SDC_HOME}/global_ports.sdc + + ######################################### + # Setup constraints for paths + # Connection block name + set CB_CHAN_NAME "chan*"; + set CB_PIN_NAME "*grid_pin*"; + set_max_delay -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} 6.02e-11 + set_max_delay -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} 6.02e-11 + + ################################## + # Read post-PnR parasitics + read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef + + ################################## + # Report timing of Connect block + report_timing -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt + report_timing -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt -################################## -# Read post-PnR netlists -read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES} -# Top-level module name -#set DESIGN_NAME "cbx_1__0_"; -#set DESIGN_NAME "cbx_1__1_"; -#set DESIGN_NAME "cbx_1__12_"; -#set DESIGN_NAME "cby_0__1_"; -#set DESIGN_NAME "cby_1__1_"; -set DESIGN_NAME "cby_12__1_"; -link_design ${DESIGN_NAME} - -######################################### -# Setup constraints to break combinational loops -#source ${SDC_HOME}/disable_configurable_memory_outputs.sdc -set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D - -######################################### -# Setup constraints for clocks -#source ${SDC_HOME}/global_ports.sdc - -######################################### -# Setup constraints for paths -# Connection block name -set CB_CHAN_NAME "chan*"; -set CB_PIN_NAME "*grid_pin*"; -set_max_delay -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} 6.02e-11 -set_max_delay -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} 6.02e-11 - -################################## -# Read post-PnR parasitics -read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef - -################################## -# Report timing of Connect block -report_timing -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt -report_timing -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt +} ################################## # Finish and quit From db203b369030d5189f50cd94996ae6df76b038ea Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 18:04:56 -0600 Subject: [PATCH 09/24] [Script] Update report timing script for switch blocks in the purpose of one-shot report generation --- SNPS_PT/SCRIPT/report_timing_sb.tcl | 103 +++++++++++++++------------- 1 file changed, 55 insertions(+), 48 deletions(-) diff --git a/SNPS_PT/SCRIPT/report_timing_sb.tcl b/SNPS_PT/SCRIPT/report_timing_sb.tcl index 5a6c846..9e426b7 100644 --- a/SNPS_PT/SCRIPT/report_timing_sb.tcl +++ b/SNPS_PT/SCRIPT/report_timing_sb.tcl @@ -3,17 +3,22 @@ # using Synopsys PrimeTime ##################################################################### -################################## -# Ensure a clean start -remove_design -all -remove_lib -all - ################################## # Define environment variables set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; -set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; -set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; -set DEVICE_NAME "SOFA" + +#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; +set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; +#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; + +#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; +#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; + +#set DEVICE_NAME "SOFA_HD" +set DEVICE_NAME "QLSOFA_HD" +#set DEVICE_NAME "SOFA_CHD" + set TIMING_REPORT_HOME "../TIMING_REPORTS/"; # Enable preprocessing in Verilog parser set_app_var svr_enable_vpp true @@ -27,48 +32,50 @@ set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" ################################## -# Read timing libraries -read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" +# Sweep all the SB designs +set DESIGN_NAMES {"sb_1__1_" "sb_0__0_" "sb_0__2_" "sb_0__1_" "sb_2__0_" "sb_2__2_" "sb_2__1_" "sb_1__0_" "sb_1__2_"}; -################################## -# Read post-PnR netlists -read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES} -# Top-level module name -#set DESIGN_NAME sb_1__1_; -#set DESIGN_NAME "sb_0__0_"; -#set DESIGN_NAME "sb_0__2_"; -#set DESIGN_NAME "sb_0__1_"; -#set DESIGN_NAME "sb_2__0_"; -#set DESIGN_NAME "sb_2__2_"; -#set DESIGN_NAME "sb_2__1_"; -#set DESIGN_NAME "sb_1__0_"; -set DESIGN_NAME "sb_1__2_"; +foreach DESIGN_NAME ${DESIGN_NAMES} { -link_design ${DESIGN_NAME} - -######################################### -# Setup constraints to break combinational loops -set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D -# -########################################## -## Setup constraints for clocks - -########################################## -## Setup constraints for paths -## Switch block name -set SB_CHAN_NAME "chan*"; -set SB_PIN_NAME "*grid_pin*"; -set_max_delay -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} 2.272500113e-12 -set_max_delay -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} 7.247000222e-11 - -################################## -# Read post-PnR parasitics -read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef - -################################## -# Report timing of Connect block -report_timing -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt -report_timing -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt + ################################## + # Ensure a clean start + remove_design -all + remove_lib -all + + ################################## + # Read timing libraries + read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" + + ################################## + # Read post-PnR netlists + read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES} + + link_design ${DESIGN_NAME} + + ######################################### + # Setup constraints to break combinational loops + set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D + # + ########################################## + ## Setup constraints for clocks + + ########################################## + ## Setup constraints for paths + ## Switch block name + set SB_CHAN_NAME "chan*"; + set SB_PIN_NAME "*grid_pin*"; + set_max_delay -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} 2.272500113e-12 + set_max_delay -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} 7.247000222e-11 + + ################################## + # Read post-PnR parasitics + read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef + + ################################## + # Report timing of Connect block + report_timing -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt + report_timing -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt +} ################################## # Finish and quit From fdb37e05592dd75a921247b60a43c54c6d0e495b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 18:09:17 -0600 Subject: [PATCH 10/24] [Script] formatting --- SNPS_PT/SCRIPT/report_timing_cb.tcl | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/SNPS_PT/SCRIPT/report_timing_cb.tcl b/SNPS_PT/SCRIPT/report_timing_cb.tcl index c507922..fd5fb73 100644 --- a/SNPS_PT/SCRIPT/report_timing_cb.tcl +++ b/SNPS_PT/SCRIPT/report_timing_cb.tcl @@ -6,16 +6,21 @@ ################################## # Define environment variables set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; + #set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; #set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; + #set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; #set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; + #set DEVICE_NAME "SOFA_HD" set DEVICE_NAME "QLSOFA_HD" #set DEVICE_NAME "SOFA_CHD" + set TIMING_REPORT_HOME "../TIMING_REPORTS/"; + # Enable preprocessing in Verilog parser set_app_var svr_enable_vpp true # Enable reporting ALL the timing paths even those are NOT constrained From 12af3b5fa3f722224cbaf8810615d0705ee9ec4b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 18:09:31 -0600 Subject: [PATCH 11/24] [Script] Update report timing script for I/O --- SNPS_PT/SCRIPT/report_timing_io.tcl | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/SNPS_PT/SCRIPT/report_timing_io.tcl b/SNPS_PT/SCRIPT/report_timing_io.tcl index 57f0465..5714dfc 100644 --- a/SNPS_PT/SCRIPT/report_timing_io.tcl +++ b/SNPS_PT/SCRIPT/report_timing_io.tcl @@ -3,18 +3,24 @@ # using Synopsys PrimeTime ##################################################################### -################################## -# Ensure a clean start -remove_design -all -remove_lib -all - ################################## # Define environment variables set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; -set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; -set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; -set DEVICE_NAME "SOFA" + +#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; +set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; +#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; + +#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; +#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; + +#set DEVICE_NAME "SOFA_HD" +set DEVICE_NAME "QLSOFA_HD" +#set DEVICE_NAME "SOFA_CHD" + set TIMING_REPORT_HOME "../TIMING_REPORTS/"; + # Enable preprocessing in Verilog parser set_app_var svr_enable_vpp true # Enable reporting ALL the timing paths even those are NOT constrained @@ -26,6 +32,11 @@ set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" +################################## +# Ensure a clean start +remove_design -all +remove_lib -all + ################################## # Read timing libraries read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" From 514dbf045d36dfea58f47e2cd5e1d796b0886a44 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 18:10:06 -0600 Subject: [PATCH 12/24] [Script] Update report timinig script for CLB --- SNPS_PT/SCRIPT/report_timing_clb.tcl | 29 ++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/SNPS_PT/SCRIPT/report_timing_clb.tcl b/SNPS_PT/SCRIPT/report_timing_clb.tcl index 80afddd..502a9bb 100644 --- a/SNPS_PT/SCRIPT/report_timing_clb.tcl +++ b/SNPS_PT/SCRIPT/report_timing_clb.tcl @@ -3,18 +3,24 @@ # using Synopsys PrimeTime ##################################################################### -################################## -# Ensure a clean start -remove_design -all -remove_lib -all - ################################## # Define environment variables set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; -set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; -set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; -set DEVICE_NAME "SOFA" + +#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; +set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; +#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; + +#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; +#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; + +#set DEVICE_NAME "SOFA_HD" +set DEVICE_NAME "QLSOFA_HD" +#set DEVICE_NAME "SOFA_CHD" + set TIMING_REPORT_HOME "../TIMING_REPORTS/"; + # Enable preprocessing in Verilog parser set_app_var svr_enable_vpp true # Enable reporting ALL the timing paths even those are NOT constrained @@ -26,6 +32,11 @@ set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" +################################## +# Ensure a clean start +remove_design -all +remove_lib -all + ################################## # Read timing libraries read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" @@ -70,6 +81,8 @@ report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__ report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt +# TODO: Carry logic timing + ################################## # Finish and quit # Comment it out if you want to debug From f28ff97b8b5c5b290cda66ecfac4a82dc7cb4df6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 20:28:38 -0600 Subject: [PATCH 13/24] [Arch] Move timing values to design variable yml so that we can reuse arch XML to model timing in different corners --- ...l_io_skywater130nm_timing_tt_025C_1v80.yml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml diff --git a/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml new file mode 100644 index 0000000..98481e8 --- /dev/null +++ b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml @@ -0,0 +1,26 @@ +L1_SB_MUX_DELAY: 1.61e-9 +L2_SB_MUX_DELAY: 1.61e-9 +L4_SB_MUX_DELAY: 1.61e-9 +CB_MUX_DELAY: 1.38e-9 +L1_WIRE_R: 100 +L1_WIRE_C: 1e-12 +L2_WIRE_R: 100 +L2_WIRE_C: 1e-12 +L4_WIRE_R: 100 +L4_WIRE_C: 1e-12 +INPAD_DELAY: 0.11e-9 +OUTPAD_DELAY: 0.11e-9 +FF_T_SETUP: 0.39e-9 +FF_CLK2Q_DELAY: 0.43e-9 +LUT_OUT0_TO_FF_D_DELAY: 1.14e-9 +LUT_OUT1_TO_FF_D_DELAY: 0.56e-9 +LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 +FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 +LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 +FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 +LUT3_DELAY: 2.31e-9 +LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9 +LUT4_DELAY: 2.6e-9 +LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9 +REGIN_TO_FF0_DELAY: 1.12e-9 +FF0_TO_FF1_DELAY: 0.56e-9 From 54df2a4f9777e9c3e73d7a8762e2d393d12db391 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 20:29:13 -0600 Subject: [PATCH 14/24] [Arch] Update SOFA HD arch to use timing variables --- ...n_chain_nonLR_caravel_io_skywater130nm.xml | 93 +++++++++---------- 1 file changed, 46 insertions(+), 47 deletions(-) diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index 622dd8b..84b2fbe 100644 --- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -11,8 +11,7 @@ - 80% L = 4, fc_in = 0.15, Fc_out = 0.10 - 100 routing tracks per channel - - The timing is extracted from a TT corner (1.8V, 25C) - - TODO: Add multi-corners, in particular, SS corner + - Timing is loaded through an external yml file, so that we can model multiple corners Authors: Xifan Tang --> @@ -205,11 +204,11 @@ - - - + + + - + - + 1 1 1 - + 1 1 1 1 1 - + 1 1 1 1 1 1 1 1 1 @@ -256,10 +255,10 @@ - + - + @@ -274,7 +273,7 @@ - + @@ -284,7 +283,7 @@ - + @@ -364,9 +363,9 @@ - - - + + + @@ -376,22 +375,22 @@ - - + + - - + + - - + + - - + + @@ -422,9 +421,9 @@ - 2.31e-9 - 2.31e-9 - 2.31e-9 + ${LUT3_DELAY} + ${LUT3_DELAY} + ${LUT3_DELAY} @@ -432,8 +431,8 @@ - - + + @@ -441,13 +440,13 @@ - + - - + + @@ -478,10 +477,10 @@ - 2.6e-9 - 2.6e-9 - 2.6e-9 - 2.6e-9 + ${LUT4_DELAY} + ${LUT4_DELAY} + ${LUT4_DELAY} + ${LUT4_DELAY} @@ -489,8 +488,8 @@ - - + + @@ -498,13 +497,13 @@ - + - - + + @@ -526,26 +525,26 @@ - - + + - + - + - + - + From 7e4595068a382f98f31100529233bfb2b426dd12 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 20:29:30 -0600 Subject: [PATCH 15/24] [Script] Add design variables to task configuration files --- .../generate_fabric/config/task_template.conf | 1 + .../generate_sdc/config/task_template.conf | 1 + .../generate_testbench/config/task_template.conf | 1 + SNPS_PT/SCRIPT/report_timing_clb.tcl | 8 +++++++- 4 files changed, 10 insertions(+), 1 deletion(-) diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf index 222aee6..1a8d96d 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf index 24bc072..9f8fc0d 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf index 8ffa663..9ace75d 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga diff --git a/SNPS_PT/SCRIPT/report_timing_clb.tcl b/SNPS_PT/SCRIPT/report_timing_clb.tcl index 502a9bb..91a7314 100644 --- a/SNPS_PT/SCRIPT/report_timing_clb.tcl +++ b/SNPS_PT/SCRIPT/report_timing_clb.tcl @@ -51,7 +51,13 @@ link_design ${DESIGN_NAME} ######################################### # Setup constraints to break combinational loops -set_disable_timing */*/*/mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q +if {${DEVICE_NAME} eq "SOFA_HD"} { + set_disable_timing */*/*/mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q +} else { + # QLSOFA and SOFA CHD use a LUT with carry logic, the memory is deeper in hierarchy + # Also QLSOFA and SOFA CHD use a different FF cell as configuration memory + set_disable_timing */*/*/*/*/*mem/sky*_fd_sc_hd__dfrtp_*_*_/Q +} # ########################################## ## Setup constraints for clocks From 2afd42bb45b8fb0f0f752420b816518328cafdd6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 20:31:13 -0600 Subject: [PATCH 16/24] [Arch] Explicit comment SOFA HD arch --- ...eable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index 84b2fbe..b5632c3 100644 --- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -1,5 +1,5 @@ - - - + + + - + - - + 1 1 1 - + 1 1 1 1 1 - + 1 1 1 1 1 1 1 1 1 @@ -296,10 +265,10 @@ - + - + @@ -315,7 +284,7 @@ - + @@ -325,7 +294,7 @@ - + @@ -430,10 +399,10 @@ - - - - + + + + @@ -446,22 +415,22 @@ - - + + - - + + - - + + - - + + @@ -494,18 +463,10 @@ - - 235e-12 - 235e-12 - 235e-12 + ${LUT3_DELAY} + ${LUT3_DELAY} + ${LUT3_DELAY} @@ -513,8 +474,8 @@ - - + + @@ -525,8 +486,8 @@ - - + + @@ -556,20 +517,11 @@ - - 261e-12 - 261e-12 - 261e-12 - 261e-12 + ${LUT4_DELAY} + ${LUT4_DELAY} + ${LUT4_DELAY} + ${LUT4_DELAY} @@ -577,20 +529,21 @@ - - + + + - - + + @@ -612,15 +565,23 @@ - - + + - - + + + + + + - - + + + + + + @@ -642,52 +603,36 @@ I[0] should be connected to in[0] --> - - - - - - - - - - - - - - - - @@ -703,7 +648,7 @@ - + @@ -715,7 +660,7 @@ - + @@ -724,7 +669,7 @@ - + From 36b871bcbbb87b9fb1033bd33691316ec8be02d9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 21:00:53 -0600 Subject: [PATCH 20/24] [Arch] Name change for FF CLK2Q vairable --- ...nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml | 2 +- ...register_scan_chain_nonLR_caravel_io_skywater130nm.xml | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml index 98481e8..82c1658 100644 --- a/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml +++ b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml @@ -11,7 +11,7 @@ L4_WIRE_C: 1e-12 INPAD_DELAY: 0.11e-9 OUTPAD_DELAY: 0.11e-9 FF_T_SETUP: 0.39e-9 -FF_CLK2Q_DELAY: 0.43e-9 +FF_T_CLK2Q: 0.43e-9 LUT_OUT0_TO_FF_D_DELAY: 1.14e-9 LUT_OUT1_TO_FF_D_DELAY: 0.56e-9 LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index 838f202..1730839 100644 --- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -365,7 +365,7 @@ - + @@ -432,7 +432,7 @@ - + @@ -489,7 +489,7 @@ - + @@ -526,7 +526,7 @@ - + From 7059c6a014634ea09777d0488b58941dadce89c1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 21:05:53 -0600 Subject: [PATCH 21/24] [Arch] Add timing variables for CHD arch but will update later --- ..._skywater130nm_chd_timing_tt_025C_1v80.yml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml diff --git a/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml b/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml new file mode 100644 index 0000000..a7eb774 --- /dev/null +++ b/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml @@ -0,0 +1,26 @@ +L1_SB_MUX_DELAY: 1.44e-9 +L2_SB_MUX_DELAY: 1.44e-9 +L4_SB_MUX_DELAY: 1.44e-9 +CB_MUX_DELAY: 1.38e-9 +L1_WIRE_R: 100 +L1_WIRE_C: 1e-12 +L2_WIRE_R: 100 +L2_WIRE_C: 1e-12 +L4_WIRE_R: 100 +L4_WIRE_C: 1e-12 +INPAD_DELAY: 0.11e-9 +OUTPAD_DELAY: 0.11e-9 +FF_T_SETUP: 0.39e-9 +FF_T_CLK2Q: 0.43e-9 +LUT_OUT0_TO_FF_D_DELAY: 1.14e-9 +LUT_OUT1_TO_FF_D_DELAY: 0.56e-9 +LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 +FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 +LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 +FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 +LUT3_DELAY: 2.31e-9 +LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9 +LUT4_DELAY: 2.6e-9 +LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9 +REGIN_TO_FF0_DELAY: 1.12e-9 +FF0_TO_FF1_DELAY: 0.56e-9 From 4aea849cf915f201c357092d00d089bee91c207f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 21:06:22 -0600 Subject: [PATCH 22/24] [Script] Add design varaibles to task configuration files --- .../generate_fabric/config/task_template.conf | 1 + .../generate_sdc/config/task_template.conf | 1 + .../generate_testbench/config/task_template.conf | 1 + .../generate_fabric/config/task_template.conf | 1 + .../generate_sdc/config/task_template.conf | 1 + .../generate_testbench/config/task_template.conf | 1 + 6 files changed, 6 insertions(+) diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf index cd63b08..2e59019 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf index 4c9c449..5c237ef 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf index 10575fb..4c1b999 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf index cb4179f..23d93bd 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf index ce0d515..8df8e62 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf index 8af1f08..3d61334 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga From b22584e7a19802a1631d2862f6623281a86cbb67 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 21:16:08 -0600 Subject: [PATCH 23/24] [MISC] Bug fixes for wrong paths in task configuration files; typo in arch files --- ...eable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml | 2 +- .../generate_fabric/config/task_template.conf | 2 +- .../generate_sdc/config/task_template.conf | 2 +- .../generate_testbench/config/task_template.conf | 2 +- .../generate_fabric/config/task_template.conf | 1 + .../generate_sdc/config/task_template.conf | 1 + .../generate_testbench/config/task_template.conf | 1 + .../generate_fabric/config/task_template.conf | 2 +- .../generate_sdc/config/task_template.conf | 2 +- .../generate_testbench/config/task_template.conf | 2 +- .../generate_fabric/config/task_template.conf | 2 +- .../generate_sdc/config/task_template.conf | 2 +- .../generate_testbench/config/task_template.conf | 2 +- 13 files changed, 13 insertions(+), 10 deletions(-) diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index 1730839..78852d0 100644 --- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -503,7 +503,7 @@ - + diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf index 1a8d96d..83177c0 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf @@ -14,7 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr -arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf index 9f8fc0d..4e4f773 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf @@ -14,7 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr -arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf index 9ace75d..8549248 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf @@ -14,7 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr -arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf index 5c2cfba..63edfe6 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf index 78f595f..5a0c479 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf index fced52c..1e0ba61 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf index 2e59019..313ec0a 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf @@ -14,7 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr -arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf index 5c237ef..f9ce99e 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf @@ -14,7 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr -arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf index 4c1b999..91083ef 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf @@ -14,7 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr -arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf index 23d93bd..c91fba3 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf @@ -14,7 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr -arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf index 8df8e62..53e507b 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf @@ -14,7 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr -arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf index 3d61334..0ac1d09 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf @@ -14,7 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr -arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga From 8196514c2699d61931bfcc9d84a56cfc986e6fac Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 22:16:44 -0600 Subject: [PATCH 24/24] [Arch] Bug fix --- ...adder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index d107281..fa538ba 100644 --- a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -530,7 +530,7 @@ - +