diff --git a/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
new file mode 100644
index 0000000..82c1658
--- /dev/null
+++ b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
@@ -0,0 +1,26 @@
+L1_SB_MUX_DELAY: 1.61e-9
+L2_SB_MUX_DELAY: 1.61e-9
+L4_SB_MUX_DELAY: 1.61e-9
+CB_MUX_DELAY: 1.38e-9
+L1_WIRE_R: 100
+L1_WIRE_C: 1e-12
+L2_WIRE_R: 100
+L2_WIRE_C: 1e-12
+L4_WIRE_R: 100
+L4_WIRE_C: 1e-12
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
+LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT3_DELAY: 2.31e-9
+LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9
+LUT4_DELAY: 2.6e-9
+LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9
+REGIN_TO_FF0_DELAY: 1.12e-9
+FF0_TO_FF1_DELAY: 0.56e-9
diff --git a/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml b/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
new file mode 100644
index 0000000..a7eb774
--- /dev/null
+++ b/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
@@ -0,0 +1,26 @@
+L1_SB_MUX_DELAY: 1.44e-9
+L2_SB_MUX_DELAY: 1.44e-9
+L4_SB_MUX_DELAY: 1.44e-9
+CB_MUX_DELAY: 1.38e-9
+L1_WIRE_R: 100
+L1_WIRE_C: 1e-12
+L2_WIRE_R: 100
+L2_WIRE_C: 1e-12
+L4_WIRE_R: 100
+L4_WIRE_C: 1e-12
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
+LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT3_DELAY: 2.31e-9
+LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9
+LUT4_DELAY: 2.6e-9
+LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9
+REGIN_TO_FF0_DELAY: 1.12e-9
+FF0_TO_FF1_DELAY: 0.56e-9
diff --git a/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml b/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
new file mode 100644
index 0000000..a7eb774
--- /dev/null
+++ b/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
@@ -0,0 +1,26 @@
+L1_SB_MUX_DELAY: 1.44e-9
+L2_SB_MUX_DELAY: 1.44e-9
+L4_SB_MUX_DELAY: 1.44e-9
+CB_MUX_DELAY: 1.38e-9
+L1_WIRE_R: 100
+L1_WIRE_C: 1e-12
+L2_WIRE_R: 100
+L2_WIRE_C: 1e-12
+L4_WIRE_R: 100
+L4_WIRE_C: 1e-12
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
+LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT3_DELAY: 2.31e-9
+LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9
+LUT4_DELAY: 2.6e-9
+LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9
+REGIN_TO_FF0_DELAY: 1.12e-9
+FF0_TO_FF1_DELAY: 0.56e-9
diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index 21f4189..78852d0 100644
--- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -1,5 +1,5 @@
 <!-- 
-  Low-cost homogeneous FPGA Architecture.
+  Low-cost homogeneous FPGA Architecture: SOFA HD
 
   - Skywater 130 nm technology
   - General purpose logic block: 
@@ -11,6 +11,8 @@
       - 80% L = 4, fc_in = 0.15, Fc_out = 0.10
       - 100 routing tracks per channel
 
+  - Timing is loaded through an external yml file, so that we can model multiple corners
+
   Authors: Xifan Tang
 -->
 <architecture>
@@ -186,21 +188,6 @@
     </fixed_layout>
   </layout>
   <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
     <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
     <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
      	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
@@ -214,41 +201,32 @@
     <connection_block input_switch_name="ipin_cblock"/>
   </device>
   <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-	       book area formula. This means the mux transistors are about 5x minimum drive strength.
-	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-	       2.5x when looking up in Jeff's tables.
-	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!-- Give uniform delays for all the MUXes driving different length of wires
+         TODO: Can be more accurate once the report timing strategies are elaborated
+       -->
+    <switch type="mux" name="L1_mux" R="0" Cin="0" Cout="0" Tdel="${L1_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <switch type="mux" name="L2_mux" R="0" Cin="0" Cout="0" Tdel="${L2_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <switch type="mux" name="L4_mux" R="0" Cin="0" Cout="0" Tdel="${L4_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
     <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+    <switch type="mux" name="ipin_cblock" R="0" Cout="0." Cin="0" Tdel="${CB_MUX_DELAY}" mux_trans_size="1.222260" buf_size="auto"/>
   </switchlist>
   <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!--- The wire delay is around 0.1ns in post PnR netlist.
+          Create a pair of RC value so that R * C = 0.1ns
+          This is o.k. because other RC values are all zero
+      -->
     <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
-    <segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+    <segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="${L1_WIRE_R}" Cmetal="${L1_WIRE_C}">
       <mux name="L1_mux"/>
       <sb type="pattern">1 1</sb>
       <cb type="pattern">1</cb>
     </segment>
-    <segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+    <segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="${L2_WIRE_R}" Cmetal="${L2_WIRE_C}">
       <mux name="L2_mux"/>
       <sb type="pattern">1 1 1</sb>
       <cb type="pattern">1 1</cb>
     </segment>
-    <segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+    <segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="${L4_WIRE_R}" Cmetal="${L4_WIRE_C}">
       <mux name="L4_mux"/>
       <sb type="pattern">1 1 1 1 1</sb>
       <cb type="pattern">1 1 1 1</cb>
@@ -277,18 +255,17 @@
         </pb_type>
         <interconnect>
           <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+            <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="iopad.outpad"/>
           </direct>
           <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+            <delay_constant max="${INPAD_DELAY}" in_port="iopad.inpad" out_port="io.inpad"/>
           </direct>
         </interconnect>
       </mode>
 
       <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
+	       The Embedded I/O timing is 0.11ns
+           FIXME: the timing may include the GPIO timing!!!
 	     -->
       <mode name="inpad">
         <pb_type name="inpad" blif_model=".input" num_pb="1">
@@ -296,7 +273,7 @@
         </pb_type>
         <interconnect>
           <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+            <delay_constant max="${INPAD_DELAY}" in_port="inpad.inpad" out_port="io.inpad"/>
           </direct>
         </interconnect>
       </mode>
@@ -306,7 +283,7 @@
         </pb_type>
         <interconnect>
           <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+            <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="outpad.outpad"/>
           </direct>
         </interconnect>
       </mode>
@@ -386,9 +363,9 @@
               <input name="DI" num_pins="1"/>
               <output name="Q" num_pins="1"/>
               <clock name="clk" num_pins="1"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_setup value="66e-12" port="ff.DI" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
+              <T_setup value="${FF_T_SETUP}" port="ff.DI" clock="clk"/>
+              <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
             </pb_type>         
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
@@ -398,22 +375,22 @@
               <direct name="direct5" input="ff[1].Q" output="fabric.reg_out"/>
               <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
               <mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
-                <delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
-                <delay_constant max="45e-12" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
+                <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
+                <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
               </mux>
               <mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D">
-                <delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
-                <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
+                <delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
+                <delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
               </mux>
               <mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
-                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+                <delay_constant max="${LUT_OUT0_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="fabric.out[0]"/>
               </mux>
               <mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
-                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+                <delay_constant max="${LUT_OUT1_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="fabric.out[1]"/>
               </mux>
             </interconnect>
           </pb_type>
@@ -443,18 +420,10 @@
                 <input name="in" num_pins="3" port_class="lut_in"/>
                 <output name="out" num_pins="1" port_class="lut_out"/>
                 <!-- LUT timing using delay matrix -->
-                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                           we instead take the average of these numbers to get more stable results
-                      82e-12
-                      173e-12
-                      261e-12
-                      263e-12
-                      398e-12
-                      -->
                 <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
-                  235e-12
-                  235e-12
-                  235e-12
+                  ${LUT3_DELAY}
+                  ${LUT3_DELAY}
+                  ${LUT3_DELAY}
                 </delay_matrix>
               </pb_type>
               <!-- Define the flip-flop -->
@@ -462,20 +431,22 @@
                 <input name="D" num_pins="1" port_class="D"/>
                 <output name="Q" num_pins="1" port_class="Q"/>
                 <clock name="clk" num_pins="1" port_class="clock"/>
-                <T_setup value="66e-12" port="ff.D" clock="clk"/>
-                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
+                <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
               </pb_type>
               <interconnect>
                 <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
                 <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
                   <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
                   <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
+                  <!-- Consider the delay of the MUX between LUT3 and FF -->
+                  <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
                 </direct>
                 <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
                 <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
-                  <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                  <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
-                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
+                  <!-- Combine the delay of LUT4/LUT3 output MUX and fabric output mux -->
+                  <delay_constant max="${LUT3_OUT_TO_FLE_OUT_DELAY}" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
+                  <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
                 </mux>
               </interconnect>
             </pb_type>
@@ -505,20 +476,11 @@
               <input name="in" num_pins="4" port_class="lut_in"/>
               <output name="out" num_pins="1" port_class="lut_out"/>
               <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
               <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                261e-12
-                261e-12
-                261e-12
-                261e-12
+                ${LUT4_DELAY}
+                ${LUT4_DELAY}
+                ${LUT4_DELAY}
+                ${LUT4_DELAY}
               </delay_matrix>
             </pb_type>
             <!-- Define flip-flop -->
@@ -526,20 +488,22 @@
               <input name="D" num_pins="1" port_class="D"/>
               <output name="Q" num_pins="1" port_class="Q"/>
               <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
             </pb_type>
             <interconnect>
               <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
               <direct name="direct2" input="lut4.out" output="ff.D">
                 <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
                 <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
+                  <!-- Consider the delay of the MUX between LUT4 and FF -->
+                <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut4.out" out_port="ff.D"/>
               </direct>
               <direct name="direct3" input="ble4.clk" output="ff.clk"/>
               <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
+                <!-- Combine the delay of LUT4/LUT3 output MUX and fabric output mux -->
+                <delay_constant max="${LUT4_OUT_TO_FLE_OUT_DELAY}" in_port="lut4.out" out_port="ble4.out"/>
+                <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff.Q" out_port="ble4.out"/>
               </mux>
             </interconnect>
           </pb_type>
@@ -561,15 +525,27 @@
               <input name="D" num_pins="1" port_class="D"/>
               <output name="Q" num_pins="1" port_class="Q"/>
               <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
             </pb_type>
             <interconnect>
-              <direct name="direct1" input="shift_reg.reg_in" output="ff[0].D"/>
-              <direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
+              <direct name="direct1" input="shift_reg.reg_in" output="ff[0].D">
+                <!-- Consider the delay of the MUX between LUT4 and FF -->
+                <delay_constant max="${REGIN_TO_FF0_DELAY}" in_port="shift_reg.reg_in" out_port="ff[0].D"/>
+              </direct>
+              <direct name="direct2" input="ff[0].Q" output="ff[1].D">
+                <!-- Consider the delay of the MUX between LUT4 and FF -->
+                <delay_constant max="${FF0_TO_FF1_DELAY}" in_port="ff[0].Q" out_port="ff[1].D"/>
+              </direct>
               <direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/>
-              <direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]"/>
-              <direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]"/>
+              <direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]">
+                <!-- Consider the delay of the MUX between LUT4 and FF -->
+                <delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="shift_reg.ff_out[0:0]"/>
+              </direct>
+              <direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]">
+                <!-- Consider the delay of the MUX between LUT4 and FF -->
+                <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="shift_reg.ff_out[1:1]"/>
+              </direct>
               <complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
             </interconnect>
           </pb_type>
@@ -591,52 +567,36 @@
                     I[0] should be connected to in[0]
           -->
         <direct name="direct_fle0" input="clb.I0[0:2]" output="fle[0:0].in[0:2]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle0i" input="clb.I0i" output="fle[0:0].in[3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle1" input="clb.I1[0:2]" output="fle[1:1].in[0:2]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle1i" input="clb.I1i" output="fle[1:1].in[3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle2" input="clb.I2[0:2]" output="fle[2:2].in[0:2]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle2i" input="clb.I2i" output="fle[2:2].in[3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle3" input="clb.I3[0:2]" output="fle[3:3].in[0:2]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle3i" input="clb.I3i" output="fle[3:3].in[3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle4" input="clb.I4[0:2]" output="fle[4:4].in[0:2]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle4i" input="clb.I4i" output="fle[4:4].in[3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle5" input="clb.I5[0:2]" output="fle[5:5].in[0:2]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle5i" input="clb.I5i" output="fle[5:5].in[3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle6" input="clb.I6[0:2]" output="fle[6:6].in[0:2]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle6i" input="clb.I6i" output="fle[6:6].in[3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle7" input="clb.I7[0:2]" output="fle[7:7].in[0:2]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle7i" input="clb.I7i" output="fle[7:7].in[3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <complete name="clks" input="clb.clk" output="fle[7:0].clk">
         </complete>
@@ -650,7 +610,7 @@
         <!-- Shift register chain links -->
         <direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
           <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
+          <delay_constant max="0e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
           <!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
         </direct>
         <direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
@@ -662,7 +622,7 @@
         <!-- Scan chain links -->
         <direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
           <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
+          <delay_constant max="0e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
         </direct>
         <direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
         </direct>
diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index b7c3089..fa538ba 100644
--- a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -1,5 +1,5 @@
 <!-- 
-  Low-cost homogeneous FPGA Architecture.
+  Low-cost homogeneous FPGA Architecture for QLSOFA_HD.
 
   - Skywater 130 nm technology
   - General purpose logic block: 
@@ -204,21 +204,6 @@
     </fixed_layout>
   </layout>
   <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
     <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
     <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
      	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
@@ -232,41 +217,25 @@
     <connection_block input_switch_name="ipin_cblock"/>
   </device>
   <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-	       book area formula. This means the mux transistors are about 5x minimum drive strength.
-	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-	       2.5x when looking up in Jeff's tables.
-	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <switch type="mux" name="L1_mux" R="0" Cin="0" Cout="0" Tdel="${L1_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <switch type="mux" name="L2_mux" R="0" Cin="0" Cout="0" Tdel="${L2_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <switch type="mux" name="L4_mux" R="0" Cin="0" Cout="0" Tdel="${L4_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
     <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+    <switch type="mux" name="ipin_cblock" R="0" Cout="0" Cin="0" Tdel="${CB_MUX_DELAY}" mux_trans_size="1.222260" buf_size="auto"/>
   </switchlist>
   <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
     <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
-    <segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+    <segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="${L1_WIRE_R}" Cmetal="${L1_WIRE_C}">
       <mux name="L1_mux"/>
       <sb type="pattern">1 1</sb>
       <cb type="pattern">1</cb>
     </segment>
-    <segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+    <segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="${L2_WIRE_R}" Cmetal="${L2_WIRE_C}">
       <mux name="L2_mux"/>
       <sb type="pattern">1 1 1</sb>
       <cb type="pattern">1 1</cb>
     </segment>
-    <segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+    <segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="${L4_WIRE_R}" Cmetal="${L4_WIRE_C}">
       <mux name="L4_mux"/>
       <sb type="pattern">1 1 1 1 1</sb>
       <cb type="pattern">1 1 1 1</cb>
@@ -296,10 +265,10 @@
         </pb_type>
         <interconnect>
           <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+            <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="iopad.outpad"/>
           </direct>
           <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+            <delay_constant max="${INPAD_DELAY}" in_port="iopad.inpad" out_port="io.inpad"/>
           </direct>
         </interconnect>
       </mode>
@@ -315,7 +284,7 @@
         </pb_type>
         <interconnect>
           <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+            <delay_constant max="${INPAD_DELAY}" in_port="inpad.inpad" out_port="io.inpad"/>
           </direct>
         </interconnect>
       </mode>
@@ -325,7 +294,7 @@
         </pb_type>
         <interconnect>
           <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+            <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="outpad.outpad"/>
           </direct>
         </interconnect>
       </mode>
@@ -430,10 +399,10 @@
               <input name="reset" num_pins="1"/>
               <output name="Q" num_pins="1"/>
               <clock name="clk" num_pins="1"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_setup value="66e-12" port="ff.DI" clock="clk"/>
-              <T_setup value="66e-12" port="ff.reset" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
+              <T_setup value="${FF_T_SETUP}" port="ff.DI" clock="clk"/>
+              <T_setup value="${FF_T_SETUP}" port="ff.reset" clock="clk"/>
+              <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
             </pb_type>         
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
@@ -446,22 +415,22 @@
               <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
               <complete name="complete2" input="fabric.reset" output="ff[1:0].reset"/>
               <mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
-                <delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
-                <delay_constant max="45e-12" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
+                <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
+                <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
               </mux>
               <mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D">
-                <delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
-                <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
+                <delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
+                <delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
               </mux>
               <mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
-                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+                <delay_constant max="${LUT_OUT0_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="fabric.out[0]"/>
               </mux>
               <mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
-                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+                <delay_constant max="${LUT_OUT1_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="fabric.out[1]"/>
               </mux>
             </interconnect>
           </pb_type>
@@ -494,18 +463,10 @@
                 <input name="in" num_pins="3" port_class="lut_in"/>
                 <output name="out" num_pins="1" port_class="lut_out"/>
                 <!-- LUT timing using delay matrix -->
-                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                           we instead take the average of these numbers to get more stable results
-                      82e-12
-                      173e-12
-                      261e-12
-                      263e-12
-                      398e-12
-                      -->
                 <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
-                  235e-12
-                  235e-12
-                  235e-12
+                  ${LUT3_DELAY}
+                  ${LUT3_DELAY}
+                  ${LUT3_DELAY}
                 </delay_matrix>
               </pb_type>
               <!-- Define the flip-flop -->
@@ -513,8 +474,8 @@
                 <input name="D" num_pins="1" port_class="D"/>
                 <output name="Q" num_pins="1" port_class="Q"/>
                 <clock name="clk" num_pins="1" port_class="clock"/>
-                <T_setup value="66e-12" port="ff.D" clock="clk"/>
-                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
+                <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
               </pb_type>
               <interconnect>
                 <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
@@ -525,8 +486,8 @@
                 <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
                 <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
                   <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                  <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
-                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
+                  <delay_constant max="${LUT3_OUT_TO_FLE_OUT_DELAY}" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
+                  <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
                 </mux>
               </interconnect>
             </pb_type>
@@ -556,20 +517,11 @@
               <input name="in" num_pins="4" port_class="lut_in"/>
               <output name="out" num_pins="1" port_class="lut_out"/>
               <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
               <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                261e-12
-                261e-12
-                261e-12
-                261e-12
+                ${LUT4_DELAY}
+                ${LUT4_DELAY}
+                ${LUT4_DELAY}
+                ${LUT4_DELAY}
               </delay_matrix>
             </pb_type>
             <!-- Define flip-flop -->
@@ -577,20 +529,21 @@
               <input name="D" num_pins="1" port_class="D"/>
               <output name="Q" num_pins="1" port_class="Q"/>
               <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
             </pb_type>
             <interconnect>
               <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
               <direct name="direct2" input="lut4.out" output="ff.D">
                 <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
                 <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
+                <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut4.out" out_port="ff.D"/>
               </direct>
               <direct name="direct3" input="ble4.clk" output="ff.clk"/>
               <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
+                <delay_constant max="${LUT4_OUT_TO_FLE_OUT_DELAY}" in_port="lut4.out" out_port="ble4.out"/>
+                <delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff.Q" out_port="ble4.out"/>
               </mux>
             </interconnect>
           </pb_type>
@@ -612,15 +565,23 @@
               <input name="D" num_pins="1" port_class="D"/>
               <output name="Q" num_pins="1" port_class="Q"/>
               <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
             </pb_type>
             <interconnect>
-              <direct name="direct1" input="shift_reg.reg_in" output="ff[0].D"/>
-              <direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
+              <direct name="direct1" input="shift_reg.reg_in" output="ff[0].D">
+                <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="shift_reg.reg_in" out_port="ff[0].D"/>
+              </direct>
+              <direct name="direct2" input="ff[0].Q" output="ff[1].D">
+                <delay_constant max="${FF0_TO_FF1_DELAY}" in_port="ff[0].Q" out_port="ff[1].D"/>
+              </direct>
               <direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/>
-              <direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]"/>
-              <direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]"/>
+              <direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]">
+                <delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="shift_reg.ff_out[0:0]"/>
+              </direct>
+              <direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]">
+                <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="shift_reg.ff_out[1:1]"/>
+              </direct>
               <complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
             </interconnect>
           </pb_type>
@@ -642,52 +603,36 @@
                     I[0] should be connected to in[0]
           -->
         <direct name="direct_fle0" input="clb.I0[0:1]" output="fle[0:0].in[0:1]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle0i" input="clb.I0i[0:1]" output="fle[0:0].in[2:3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle1" input="clb.I1[0:1]" output="fle[1:1].in[0:1]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle1i" input="clb.I1i[0:1]" output="fle[1:1].in[2:3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle2" input="clb.I2[0:1]" output="fle[2:2].in[0:1]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle2i" input="clb.I2i[0:1]" output="fle[2:2].in[2:3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle3" input="clb.I3[0:1]" output="fle[3:3].in[0:1]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle3i" input="clb.I3i[0:1]" output="fle[3:3].in[2:3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle4" input="clb.I4[0:1]" output="fle[4:4].in[0:1]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle4i" input="clb.I4i[0:1]" output="fle[4:4].in[2:3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle5" input="clb.I5[0:1]" output="fle[5:5].in[0:1]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle5i" input="clb.I5i[0:1]" output="fle[5:5].in[2:3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle6" input="clb.I6[0:1]" output="fle[6:6].in[0:1]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle6i" input="clb.I6i[0:1]" output="fle[6:6].in[2:3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle7" input="clb.I7[0:1]" output="fle[7:7].in[0:1]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle7i" input="clb.I7i[0:1]" output="fle[7:7].in[2:3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <complete name="clks" input="clb.clk" output="fle[7:0].clk">
         </complete>
@@ -703,7 +648,7 @@
         <!-- Shift register chain links -->
         <direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
           <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
+          <delay_constant max="0" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
           <!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
         </direct>
         <direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
@@ -715,7 +660,7 @@
         <!-- Scan chain links -->
         <direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
           <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
+          <delay_constant max="0" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
         </direct>
         <direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
         </direct>
@@ -724,7 +669,7 @@
         <!-- Carry chain links -->
         <direct name="carry_chain_in" input="clb.cin" output="fle[0:0].cin">
           <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <delay_constant max="0" in_port="clb.cin" out_port="fle[0:0].cin"/>
         </direct>
         <direct name="carry_chain_out" input="fle[7:7].cout" output="clb.cout">
         </direct>
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
index 222aee6..83177c0 100644
--- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
@@ -14,6 +14,7 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 1*60
 fpga_flow=yosys_vpr
+arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
index 24bc072..4e4f773 100644
--- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
@@ -14,6 +14,7 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 1*60
 fpga_flow=yosys_vpr
+arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
index 8ffa663..8549248 100644
--- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
@@ -14,6 +14,7 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 1*60
 fpga_flow=yosys_vpr
+arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf
index 5c2cfba..63edfe6 100644
--- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf
@@ -14,6 +14,7 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 1*60
 fpga_flow=yosys_vpr
+arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf
index 78f595f..5a0c479 100644
--- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf
@@ -14,6 +14,7 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 1*60
 fpga_flow=yosys_vpr
+arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf
index fced52c..1e0ba61 100644
--- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf
@@ -14,6 +14,7 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 1*60
 fpga_flow=yosys_vpr
+arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf
index cd63b08..313ec0a 100644
--- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf
@@ -14,6 +14,7 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 1*60
 fpga_flow=yosys_vpr
+arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf
index 4c9c449..f9ce99e 100644
--- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf
@@ -14,6 +14,7 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 1*60
 fpga_flow=yosys_vpr
+arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf
index 10575fb..91083ef 100644
--- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf
@@ -14,6 +14,7 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 1*60
 fpga_flow=yosys_vpr
+arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
index cb4179f..c91fba3 100644
--- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
@@ -14,6 +14,7 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 1*60
 fpga_flow=yosys_vpr
+arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
index ce0d515..53e507b 100644
--- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
@@ -14,6 +14,7 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 1*60
 fpga_flow=yosys_vpr
+arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
index 8af1f08..0ac1d09 100644
--- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
@@ -14,6 +14,7 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 1*60
 fpga_flow=yosys_vpr
+arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
diff --git a/SNPS_PT/SCRIPT/report_timing_cb.tcl b/SNPS_PT/SCRIPT/report_timing_cb.tcl
new file mode 100644
index 0000000..fd5fb73
--- /dev/null
+++ b/SNPS_PT/SCRIPT/report_timing_cb.tcl
@@ -0,0 +1,85 @@
+#####################################################################
+# A template script to report timing for Connection Blocks from post-PnR results
+# using Synopsys PrimeTime
+#####################################################################
+#
+##################################
+# Define environment variables
+set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
+
+#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
+set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
+#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
+
+#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
+set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
+#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
+
+#set DEVICE_NAME "SOFA_HD"
+set DEVICE_NAME "QLSOFA_HD"
+#set DEVICE_NAME "SOFA_CHD"
+
+set TIMING_REPORT_HOME "../TIMING_REPORTS/";
+
+# Enable preprocessing in Verilog parser
+set_app_var svr_enable_vpp true
+# Enable reporting ALL the timing paths even those are NOT constrained
+set_app_var timing_report_unconstrained_paths true
+
+set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
+
+set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
+
+set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
+ 
+##################################
+# Sweep all the CB design
+set DESIGN_NAMES {"cbx_1__0_" "cbx_1__1_" "cbx_1__2_" "cby_0__1_" "cby_1__1_" "cby_2__1_"};
+foreach DESIGN_NAME ${DESIGN_NAMES} {
+   
+  ##################################
+  # Ensure a clean start
+  remove_design -all
+  remove_lib -all
+  
+  ##################################
+  # Read timing libraries
+  read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
+  
+  ##################################
+  # Read post-PnR netlists
+  read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
+  link_design ${DESIGN_NAME}
+  
+  #########################################
+  # Setup constraints to break combinational loops
+  #source ${SDC_HOME}/disable_configurable_memory_outputs.sdc
+  set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D
+  
+  #########################################
+  # Setup constraints for clocks
+  #source ${SDC_HOME}/global_ports.sdc
+  
+  #########################################
+  # Setup constraints for paths
+  # Connection block name
+  set CB_CHAN_NAME "chan*";
+  set CB_PIN_NAME "*grid_pin*";
+  set_max_delay -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} 6.02e-11
+  set_max_delay -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} 6.02e-11
+  
+  ##################################
+  # Read post-PnR parasitics
+  read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
+  
+  ##################################
+  # Report timing of Connect block
+  report_timing -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
+  report_timing -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
+
+}
+
+##################################
+# Finish and quit 
+# Comment it out if you want to debug
+exit
diff --git a/SNPS_PT/SCRIPT/report_timing_clb.tcl b/SNPS_PT/SCRIPT/report_timing_clb.tcl
new file mode 100644
index 0000000..91a7314
--- /dev/null
+++ b/SNPS_PT/SCRIPT/report_timing_clb.tcl
@@ -0,0 +1,95 @@
+#####################################################################
+# A template script to report timing for A CLB from post-PnR results
+# using Synopsys PrimeTime
+#####################################################################
+ 
+##################################
+# Define environment variables
+set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
+
+#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
+set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
+#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
+
+#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
+set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
+#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
+
+#set DEVICE_NAME "SOFA_HD"
+set DEVICE_NAME "QLSOFA_HD"
+#set DEVICE_NAME "SOFA_CHD"
+
+set TIMING_REPORT_HOME "../TIMING_REPORTS/";
+
+# Enable preprocessing in Verilog parser
+set_app_var svr_enable_vpp true
+# Enable reporting ALL the timing paths even those are NOT constrained
+set_app_var timing_report_unconstrained_paths tr
+
+set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
+
+set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
+
+set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
+
+##################################
+# Ensure a clean start
+remove_design -all
+remove_lib -all
+
+##################################
+# Read timing libraries
+read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
+
+##################################
+# Read post-PnR netlists
+read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
+# Top-level module name
+set DESIGN_NAME "grid_clb";
+
+link_design ${DESIGN_NAME}
+
+#########################################
+# Setup constraints to break combinational loops
+if {${DEVICE_NAME} eq "SOFA_HD"} {
+  set_disable_timing */*/*/mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q
+} else {
+  # QLSOFA and SOFA CHD use a LUT with carry logic, the memory is deeper in hierarchy
+  # Also QLSOFA and SOFA CHD use a different FF cell as configuration memory
+  set_disable_timing */*/*/*/*/*mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
+}
+#
+##########################################
+## Setup constraints for clocks
+
+##########################################
+## Setup constraints for paths
+
+##################################
+# Read post-PnR parasitics
+read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
+
+##################################
+# Report timing of Connect block
+# LUT4 output timing
+report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/in  -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut4_out > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut4_timing.rpt
+# LUT3 output timing
+report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/in  -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut3_timing.rpt
+
+# Output selector timing
+report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
+report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
+report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
+report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[1] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
+
+# LUT output to FF input timing
+report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut4_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
+report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
+report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
+
+# TODO: Carry logic timing 
+
+##################################
+# Finish and quit 
+# Comment it out if you want to debug
+exit
diff --git a/SNPS_PT/SCRIPT/report_timing_io.tcl b/SNPS_PT/SCRIPT/report_timing_io.tcl
new file mode 100644
index 0000000..5714dfc
--- /dev/null
+++ b/SNPS_PT/SCRIPT/report_timing_io.tcl
@@ -0,0 +1,76 @@
+#####################################################################
+# A template script to report timing for A CLB from post-PnR results
+# using Synopsys PrimeTime
+#####################################################################
+ 
+##################################
+# Define environment variables
+set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
+
+#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
+set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
+#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
+
+#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
+set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
+#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
+
+#set DEVICE_NAME "SOFA_HD"
+set DEVICE_NAME "QLSOFA_HD"
+#set DEVICE_NAME "SOFA_CHD"
+
+set TIMING_REPORT_HOME "../TIMING_REPORTS/";
+
+# Enable preprocessing in Verilog parser
+set_app_var svr_enable_vpp true
+# Enable reporting ALL the timing paths even those are NOT constrained
+set_app_var timing_report_unconstrained_paths tr
+
+set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
+
+set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
+
+set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
+
+##################################
+# Ensure a clean start
+remove_design -all
+remove_lib -all
+
+##################################
+# Read timing libraries
+read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
+
+##################################
+# Read post-PnR netlists
+read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
+# Top-level module name
+# May sweep for all the io modules
+set DESIGN_NAME "cbx_1__0__logical_tile_io_mode_physical__iopad_0";
+
+link_design ${DESIGN_NAME}
+
+#########################################
+# Setup constraints to break combinational loops
+set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q
+#
+##########################################
+## Setup constraints for clocks
+
+##########################################
+## Setup constraints for paths
+
+##################################
+# Read post-PnR parasitics
+read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
+
+##################################
+# Report timing of Connect block
+# Inpad -> FPGA timing 
+report_timing -from gfpga_pad_EMBEDDED_IO_HD_SOC_IN -to iopad_inpad > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
+report_timing -from iopad_outpad -to gfpga_pad_EMBEDDED_IO_HD_SOC_OUT >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
+
+##################################
+# Finish and quit 
+# Comment it out if you want to debug
+exit
diff --git a/SNPS_PT/SCRIPT/report_timing_sb.tcl b/SNPS_PT/SCRIPT/report_timing_sb.tcl
new file mode 100644
index 0000000..9e426b7
--- /dev/null
+++ b/SNPS_PT/SCRIPT/report_timing_sb.tcl
@@ -0,0 +1,83 @@
+#####################################################################
+# A template script to report timing for Connection Blocks from post-PnR results
+# using Synopsys PrimeTime
+#####################################################################
+ 
+##################################
+# Define environment variables
+set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
+
+#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
+set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
+#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
+
+#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
+set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
+#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
+
+#set DEVICE_NAME "SOFA_HD"
+set DEVICE_NAME "QLSOFA_HD"
+#set DEVICE_NAME "SOFA_CHD"
+
+set TIMING_REPORT_HOME "../TIMING_REPORTS/";
+# Enable preprocessing in Verilog parser
+set_app_var svr_enable_vpp true
+# Enable reporting ALL the timing paths even those are NOT constrained
+set_app_var timing_report_unconstrained_paths tr
+
+set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
+
+set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
+
+set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
+
+##################################
+# Sweep all the SB designs
+set DESIGN_NAMES {"sb_1__1_" "sb_0__0_" "sb_0__2_" "sb_0__1_" "sb_2__0_" "sb_2__2_" "sb_2__1_" "sb_1__0_" "sb_1__2_"};
+
+foreach DESIGN_NAME ${DESIGN_NAMES} {
+
+  ##################################
+  # Ensure a clean start
+  remove_design -all
+  remove_lib -all
+  
+  ##################################
+  # Read timing libraries
+  read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
+  
+  ##################################
+  # Read post-PnR netlists
+  read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
+  
+  link_design ${DESIGN_NAME}
+  
+  #########################################
+  # Setup constraints to break combinational loops
+  set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D
+  #
+  ##########################################
+  ## Setup constraints for clocks
+  
+  ##########################################
+  ## Setup constraints for paths
+  ## Switch block name
+  set SB_CHAN_NAME "chan*";
+  set SB_PIN_NAME "*grid_pin*";
+  set_max_delay -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} 2.272500113e-12
+  set_max_delay -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} 7.247000222e-11
+  
+  ##################################
+  # Read post-PnR parasitics
+  read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
+  
+  ##################################
+  # Report timing of Connect block
+  report_timing -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
+  report_timing -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
+}
+
+##################################
+# Finish and quit 
+# Comment it out if you want to debug
+exit