From 1eac22feba4bf644a336c514262ffea7acad023c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Dec 2020 20:18:02 -0700 Subject: [PATCH] [Testbench] Critical bug fix on Caravel Testbench: Add a sufficient long waiting time for Caravel to finish its I/O configuration --- .../caravel_dv/and2_latch_test/and2_latch_test_caravel.v | 5 +++-- TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.v | 5 +++-- TESTBENCH/caravel_dv/scff_test/scff_test_caravel.v | 5 +++-- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.v b/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.v index 7587835..2cf870e 100644 --- a/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.v +++ b/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.v @@ -9,7 +9,8 @@ `timescale 1ns / 1ps `define POWER_UP_TIME_PERIOD 200 -`define SOC_SETUP_TIME_PERIOD 2000 +`define SOC_RESET_TIME_PERIOD 2000 +`define SOC_SETUP_TIME_PERIOD 200*2001 `define SOC_CLOCK_PERIOD 12.5 `define FPGA_PROG_CLOCK_PERIOD 12.5 `define FPGA_CLOCK_PERIOD 12.5 @@ -79063,7 +79064,7 @@ end initial begin RSTB <= 1'b0; soc_setup_done <= 1'b1; - #(`SOC_SETUP_TIME_PERIOD); + #(`SOC_RESET_TIME_PERIOD); RSTB <= 1'b1; // Release reset soc_setup_done <= 1'b1; // We can start scff test end diff --git a/TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.v b/TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.v index 955a177..41065bc 100644 --- a/TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.v +++ b/TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.v @@ -1,7 +1,8 @@ `timescale 1 ns / 1 ps `define POWER_UP_TIME_PERIOD 200 -`define SOC_SETUP_TIME_PERIOD 2000 +`define SOC_RESET_TIME_PERIOD 2000 +`define SOC_SETUP_TIME_PERIOD 200*2001 `define SOC_CLOCK_PERIOD 12.5 `define FPGA_PROG_CLOCK_PERIOD 12.5 `define FPGA_CLOCK_PERIOD 12.5 @@ -180,7 +181,7 @@ module ccff_test_post_pnr_caravel_autocheck_top_tb; initial begin RSTB <= 1'b0; soc_setup_done <= 1'b1; - #(`SOC_SETUP_TIME_PERIOD); + #(`SOC_RESET_TIME_PERIOD); RSTB <= 1'b1; // Release reset soc_setup_done <= 1'b1; // We can start scff test end diff --git a/TESTBENCH/caravel_dv/scff_test/scff_test_caravel.v b/TESTBENCH/caravel_dv/scff_test/scff_test_caravel.v index 97dd641..f846520 100644 --- a/TESTBENCH/caravel_dv/scff_test/scff_test_caravel.v +++ b/TESTBENCH/caravel_dv/scff_test/scff_test_caravel.v @@ -1,7 +1,8 @@ `timescale 1 ns / 1 ps `define POWER_UP_TIME_PERIOD 200 -`define SOC_SETUP_TIME_PERIOD 2000 +`define SOC_RESET_TIME_PERIOD 2000 +`define SOC_SETUP_TIME_PERIOD 200*2001 `define SOC_CLOCK_PERIOD 12.5 `define FPGA_CLOCK_PERIOD 12.5 @@ -177,7 +178,7 @@ module scff_test_post_pnr_caravel_autocheck_top_tb; initial begin RSTB <= 1'b0; soc_setup_done <= 1'b1; - #(`SOC_SETUP_TIME_PERIOD); + #(`SOC_RESET_TIME_PERIOD); RSTB <= 1'b1; // Release reset soc_setup_done <= 1'b1; // We can start scff test end