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Added port relations to models and timing annotation to pb_types of the k4_N8 VPR architecture. 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2021-02-01 15:45:48 +01:00
parent 4ea02f257a
commit 1e3490dc8d
1 changed files with 26 additions and 4 deletions
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30
ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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@ -36,7 +36,7 @@ Authors: Xifan Tang
<model name="frac_lut4"> <model name="frac_lut4">
<input_ports> <input_ports>
<port name="in"/> <port name="in" combinational_sink_ports="lut2_out lut4_out"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="lut2_out"/> <port name="lut2_out"/>
@ -45,9 +45,9 @@ Authors: Xifan Tang
</model> </model>
<model name="carry_follower"> <model name="carry_follower">
<input_ports> <input_ports>
<port name="a"/> <port name="a" combinational_sink_ports="cout"/>
<port name="b"/> <port name="b" combinational_sink_ports="cout"/>
<port name="cin"/> <port name="cin" combinational_sink_ports="cout"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="cout"/> <port name="cout"/>
@ -486,12 +486,34 @@ Authors: Xifan Tang
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="lut2_out" num_pins="2"/> <output name="lut2_out" num_pins="2"/>
<output name="lut4_out" num_pins="1"/> <output name="lut4_out" num_pins="1"/>
<!-- FIXME: Timing values taken from the pb_type implementing .names.
May require adjustments as delays may differ between lut2_out and lut4_out -->
<delay_matrix type="max" in_port="frac_lut4.in" out_port="frac_lut4.lut2_out">
261e-12
261e-12
261e-12
261e-12
261e-12
261e-12
261e-12
261e-12
</delay_matrix>
<delay_matrix type="max" in_port="frac_lut4.in" out_port="frac_lut4.lut4_out">
261e-12
261e-12
261e-12
261e-12
</delay_matrix>
</pb_type> </pb_type>
<pb_type name="carry_follower" blif_model=".subckt carry_follower" num_pb="1"> <pb_type name="carry_follower" blif_model=".subckt carry_follower" num_pb="1">
<input name="a" num_pins="1"/> <input name="a" num_pins="1"/>
<input name="b" num_pins="1"/> <input name="b" num_pins="1"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<!-- FIXME: Completely fake timing data -->
<delay_constant max="100e-12" in_port="carry_follower.a" out_port="carry_follower.cout"/>
<delay_constant max="100e-12" in_port="carry_follower.b" out_port="carry_follower.cout"/>
<delay_constant max="100e-12" in_port="carry_follower.cin" out_port="carry_follower.cout"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="frac_logic.in[0:1]" output="frac_lut4.in[0:1]"/> <direct name="direct1" input="frac_logic.in[0:1]" output="frac_lut4.in[0:1]"/>