From 1b2a14886b3eb704b5126bc11f18043e913d8284 Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Tue, 6 Apr 2021 08:58:07 -0600
Subject: [PATCH] [Repo] Adding skywater PDK as submodule

---
 .gitmodules                                   |  4 ++
 .../FPGA1212_SOFA_CHD_task/config/task.conf   | 40 +-----------------
 FPGA1212_SOFA_CHD_PNR/Makefile                | 41 +------------------
 skywater-pdk                                  |  1 +
 4 files changed, 7 insertions(+), 79 deletions(-)
 create mode 100644 .gitmodules
 mode change 100644 => 120000 FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/config/task.conf
 mode change 100644 => 120000 FPGA1212_SOFA_CHD_PNR/Makefile
 create mode 160000 skywater-pdk

diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..a8b8380
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,4 @@
+[submodule "skywater-pdk"]
+	path = skywater-pdk
+	url = https://github.com/ganeshgore/skywater-pdk.git
+	branch = ganesh_dev
diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/config/task.conf b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/config/task.conf
deleted file mode 100644
index 66d79ea..0000000
--- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/config/task.conf
+++ /dev/null
@@ -1,39 +0,0 @@
-    # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# Configuration file for running experiments
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
-# Each job execute fpga_flow script on combination of architecture & benchmark
-# timeout_each_job is timeout for each job
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-
-[GENERAL]
-run_engine=openfpga_shell
-power_analysis = false
-spice_output=false
-verilog_output=true
-timeout_each_job = 20*60
-fpga_flow=vpr_blif
-arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
-
-
-[OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
-openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
-openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
-external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
-openfpga_vpr_device_layout=12x12
-openfpga_vpr_route_chan_width=60
-
-[ARCHITECTURES]
-arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
-
-[BENCHMARKS]
-bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif
-
-[SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
-bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v
-
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/config/task.conf b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/config/task.conf
new file mode 120000
index 0000000..5fd7865
--- /dev/null
+++ b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/config/task.conf
@@ -0,0 +1 @@
+task_generation.conf
\ No newline at end of file
diff --git a/FPGA1212_SOFA_CHD_PNR/Makefile b/FPGA1212_SOFA_CHD_PNR/Makefile
deleted file mode 100644
index d0ddbe8..0000000
--- a/FPGA1212_SOFA_CHD_PNR/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-##########################################################################################
-##########################################################################################
-
-SHELL=bash
-PYTHON_EXEC=python3.8
-RERUN = 0
-TB = top
-OPTIONS =
-
-.SILENT:
-.ONESHELL:
-
-runOpenFPGA:
-	SECONDS=0
-	source config.sh
-	# =====================  Check Tools  =====================
-	which python3.8 > /dev/null
-	if [ $$? -eq 1 ]; then
-		echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit;
-	fi
-
-	# ===================  Clean Previous Run  =================================
-	rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME}
-	(cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf)
-
-	# =====================  Generate Netlist  =================================
-	(currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir &&
-	run-task $${TASK_DIR_NAME} --remove_run_dir all
-	run-task $${TASK_DIR_NAME} ${OPTIONS})
-
-	if [ $$? -eq 1 ]; then
-		echo "X X X X X X Failed to generate netlist X X X X X X"; exit;
-	fi
-
-	duration=$$SECONDS
-	date > runOpenFPGA
-	echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA
-
-clean:
-	rm -rf runOpenFPGA
\ No newline at end of file
diff --git a/FPGA1212_SOFA_CHD_PNR/Makefile b/FPGA1212_SOFA_CHD_PNR/Makefile
new file mode 120000
index 0000000..2757a41
--- /dev/null
+++ b/FPGA1212_SOFA_CHD_PNR/Makefile
@@ -0,0 +1 @@
+../FPGA1212_SOFA_HD_PNR/Makefile
\ No newline at end of file
diff --git a/skywater-pdk b/skywater-pdk
new file mode 160000
index 0000000..3b0f275
--- /dev/null
+++ b/skywater-pdk
@@ -0,0 +1 @@
+Subproject commit 3b0f27509ecf79e6533b2a6c2f5b29914c3c5135