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Disable generation of formal verification testbench due to disk space 

limitation on github actions.
Disable testcase not fitting on 32x32 device
This commit is contained in:
Tarachand Pagarani 2021-01-05 19:44:08 -08:00
parent f04e72b5b3
commit 1a4b1bc6b4
2 changed files with 3 additions and 3 deletions
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2
SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
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@ -57,7 +57,7 @@ write_verilog_testbench --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/verilog_testbench
--fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--print_top_testbench \
--print_preconfig_top_testbench \
# --print_preconfig_top_testbench \ disabled for now due to disk space limitation on github actions
--print_simulation_ini ${OPENFPGA_VERILOG_OUTPUT_DIR}/SimulationDeck/simulation_deck.ini \
--explicit_port_mapping
# Exclude signal initialization since it does not help simulator converge

4
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf
View File

@ -39,7 +39,7 @@ bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
bench8=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/cavlc_top/rtl/*.v
bench9=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/cf_fft_256_8/rtl/*.v
#bench9=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/cf_fft_256_8/rtl/*.v
bench10=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter120bitx5/rtl/*.v
bench11=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter_16bit/rtl/*.v
bench12=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/dct_mac/rtl/*.v
@ -65,7 +65,7 @@ bench5_top = rs_decoder_top
bench6_top = top_module
bench7_top = and2_or2
bench8_top = cavlc_top
bench9_top = cf_fft_256_8
#bench9_top = cf_fft_256_8
bench10_top = counter120bitx5
bench11_top = top
bench12_top = dct_mac