diff --git a/SynRepoConfig/sync_files_qlsofa_hd.csv b/SynRepoConfig/sync_files_qlsofa_hd.csv
index 214d025..e93b11f 100644
--- a/SynRepoConfig/sync_files_qlsofa_hd.csv
+++ b/SynRepoConfig/sync_files_qlsofa_hd.csv
@@ -1,4 +1,5 @@
 SrcLoc, DestLoc
 FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/,OpenFPGA_task
 FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
-FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
\ No newline at end of file
+FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
+SOFA-Chips/HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v
diff --git a/SynRepoConfig/sync_files_sofa_chd.csv b/SynRepoConfig/sync_files_sofa_chd.csv
index b690165..89e0555 100644
--- a/SynRepoConfig/sync_files_sofa_chd.csv
+++ b/SynRepoConfig/sync_files_sofa_chd.csv
@@ -1,4 +1,5 @@
 SrcLoc, DestLoc
 FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/,OpenFPGA_task
 FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
-FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
+FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
+SOFA-Chips/HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v
diff --git a/SynRepoConfig/sync_files_sofa_hd.csv b/SynRepoConfig/sync_files_sofa_hd.csv
index c22dd43..1bc6d22 100644
--- a/SynRepoConfig/sync_files_sofa_hd.csv
+++ b/SynRepoConfig/sync_files_sofa_hd.csv
@@ -2,4 +2,4 @@ SrcLoc, DestLoc
 FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/,OpenFPGA_task
 FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
 FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
-SOFA-Chips/HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v
\ No newline at end of file
+SOFA-Chips/HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v