riscv
/
SOFA
mirror of https://github.com/lnis-uofu/SOFA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge branch 'master' into ganesh_dev

This commit is contained in:
tangxifan 2021-04-03 19:06:52 -06:00 committed by GitHub
parent 15b64a68aa 946914698e
commit 151a54ef5f
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
6 changed files with 86 additions and 59 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
View File

@ -1,7 +1,7 @@
L1_SB_MUX_DELAY: 1.44e-9
L2_SB_MUX_DELAY: 1.44e-9
L4_SB_MUX_DELAY: 1.44e-9
CB_MUX_DELAY: 1.38e-9
L1_SB_MUX_DELAY: 0.81e-9
L2_SB_MUX_DELAY: 0.81e-9
L4_SB_MUX_DELAY: 0.81e-9
CB_MUX_DELAY: 0.57e-9
L1_WIRE_R: 100
L1_WIRE_C: 1e-12
L2_WIRE_R: 100
@ -12,15 +12,15 @@ INPAD_DELAY: 0.11e-9
OUTPAD_DELAY: 0.11e-9
FF_T_SETUP: 0.39e-9
FF_T_CLK2Q: 0.43e-9
LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
LUT3_DELAY: 2.31e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9
LUT4_DELAY: 2.6e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9
REGIN_TO_FF0_DELAY: 1.12e-9
FF0_TO_FF1_DELAY: 0.56e-9
LUT_OUT0_TO_FF_D_DELAY: 0.32e-9
LUT_OUT1_TO_FF_D_DELAY: 0.16e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.65e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.48e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.47e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.37e-9
LUT3_DELAY: 0.86e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 0.65e-9
LUT4_DELAY: 1.20e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 0.66e-9
REGIN_TO_FF0_DELAY: 0.15e-9
FF0_TO_FF1_DELAY: 0.16e-9

48
DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst
View File

@ -25,47 +25,47 @@ The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref:
+-------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+=========================+==============================+
| in0 -> LUT3_out[0] | 0.85 |
| in0 -> LUT3_out[0] | 0.86 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[0] | 0.57 |
| in1 -> LUT3_out[0] | 0.58 |
+-------------------------+------------------------------+
| in2 -> B | 0.60 |
| in2 -> B | 0.16 |
+-------------------------+------------------------------+
| B -> LUT3_out[0] | 0.32 |
+-------------------------+------------------------------+
| in0 -> LUT3_out[1] | 0.90 |
| in0 -> LUT3_out[1] | 0.91 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[1] | 0.62 |
| in1 -> LUT3_out[1] | 0.63 |
+-------------------------+------------------------------+
| B -> LUT3_out[1] | 0.33 |
| B -> LUT3_out[1] | 0.34 |
+-------------------------+------------------------------+
| in0 -> LUT4_out | 1.17 |
| in0 -> LUT4_out | 1.20 |
+-------------------------+------------------------------+
| in1 -> LUT4_out | 0.89 |
| in1 -> LUT4_out | 0.92 |
+-------------------------+------------------------------+
| in2 -> LUT4_out | 1.21 |
| in2 -> LUT4_out | 0.78 |
+-------------------------+------------------------------+
| in3 -> LUT4_out | 0.79 |
| in3 -> LUT4_out | 0.52 |
+-------------------------+------------------------------+
| LUT3_out[0] -> A | 0.56 |
| LUT3_out[0] -> A | 0.17 |
+-------------------------+------------------------------+
| LUT4_out[0] -> A | 0.58 |
| LUT4_out[0] -> A | 0.18 |
+-------------------------+------------------------------+
| A -> out[0] | 0.88 |
| A -> out[0] | 0.48 |
+-------------------------+------------------------------+
| A -> FF[0] | 0.56 |
| A -> FF[0] | 0.15 |
+-------------------------+------------------------------+
| FF[0] -> out[0] | 0.88 |
| FF[0] -> out[0] | 0.48 |
+-------------------------+------------------------------+
| LUT3_out[1] -> out[1] | 0.89 |
| LUT3_out[1] -> out[1] | 0.47 |
+-------------------------+------------------------------+
| LUT3_out[1] -> FF[1] | 0.56 |
| LUT3_out[1] -> FF[1] | 0.16 |
+-------------------------+------------------------------+
| FF[1] -> out[1] | 0.89 |
| FF[1] -> out[1] | 0.37 |
+-------------------------+------------------------------+
| regin -> FF[0] | 0.58 |
| regin -> FF[0] | 0.15 |
+-------------------------+------------------------------+
| FF[0] -> FF[1] | 0.56 |
| FF[0] -> FF[1] | 0.16 |
+-------------------------+------------------------------+
@ -90,12 +90,12 @@ The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`tab
+---------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+===========================+==============================+
| A -> B | 1.44 |
| A -> B | 0.81 |
+---------------------------+------------------------------+
| A -> C | 1.44 |
| A -> C | 0.81 |
+---------------------------+------------------------------+
| A -> D | 1.44 |
| A -> D | 0.81 |
+---------------------------+------------------------------+
| B -> E | 1.38 |
| B -> E | 0.57 |
+---------------------------+------------------------------+

17
SNPS_PT/SCRIPT/report_timing_cb.tcl
View File

@ -6,9 +6,9 @@
##################################
# Define environment variables
#
set DEVICE_NAME "SOFA_HD"
#set DEVICE_NAME "SOFA_HD"
#set DEVICE_NAME "QLSOFA_HD"
#set DEVICE_NAME "SOFA_CHD"
set DEVICE_NAME "SOFA_CHD"
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
@ -30,9 +30,13 @@ set_app_var svr_enable_vpp true
# Enable reporting ALL the timing paths even those are NOT constrained
set_app_var timing_report_unconstrained_paths true
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
if {"SOFA_CHD" == ${DEVICE_NAME}} {
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib"
} else {
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
}
set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
@ -49,6 +53,9 @@ foreach DESIGN_NAME ${DESIGN_NAMES} {
##################################
# Read timing libraries
read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
if {"SOFA_CHD" == ${DEVICE_NAME}} {
read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib"
}
##################################
# Read post-PnR netlists

17
SNPS_PT/SCRIPT/report_timing_clb.tcl
View File

@ -6,9 +6,9 @@
##################################
# Define environment variables
#
set DEVICE_NAME "SOFA_HD"
#set DEVICE_NAME "SOFA_HD"
#set DEVICE_NAME "QLSOFA_HD"
#set DEVICE_NAME "SOFA_CHD"
set DEVICE_NAME "SOFA_CHD"
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
@ -30,9 +30,13 @@ set_app_var svr_enable_vpp true
# Enable reporting ALL the timing paths even those are NOT constrained
set_app_var timing_report_unconstrained_paths tr
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
if {"SOFA_CHD" == ${DEVICE_NAME}} {
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib"
} else {
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
}
set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
@ -44,6 +48,9 @@ remove_lib -all
##################################
# Read timing libraries
read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
if {"SOFA_CHD" == ${DEVICE_NAME}} {
read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib"
}
##################################
# Read post-PnR netlists

14
SNPS_PT/SCRIPT/report_timing_io.tcl
View File

@ -23,7 +23,6 @@ if {"SOFA_HD" == ${DEVICE_NAME}} {
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
}
set TIMING_REPORT_HOME "../TIMING_REPORTS/";
# Enable preprocessing in Verilog parser
@ -31,9 +30,13 @@ set_app_var svr_enable_vpp true
# Enable reporting ALL the timing paths even those are NOT constrained
set_app_var timing_report_unconstrained_paths tr
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
if {"SOFA_CHD" == ${DEVICE_NAME}} {
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib"
} else {
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
}
set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
@ -45,6 +48,9 @@ remove_lib -all
##################################
# Read timing libraries
read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
if {"SOFA_CHD" == ${DEVICE_NAME}} {
read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib"
}
##################################
# Read post-PnR netlists

17
SNPS_PT/SCRIPT/report_timing_sb.tcl
View File

@ -6,9 +6,9 @@
##################################
# Define environment variables
set DEVICE_NAME "SOFA_HD"
#set DEVICE_NAME "SOFA_HD"
#set DEVICE_NAME "QLSOFA_HD"
#set DEVICE_NAME "SOFA_CHD"
set DEVICE_NAME "SOFA_CHD"
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
@ -29,9 +29,13 @@ set_app_var svr_enable_vpp true
# Enable reporting ALL the timing paths even those are NOT constrained
set_app_var timing_report_unconstrained_paths tr
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
if {"SOFA_CHD" == ${DEVICE_NAME}} {
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib"
} else {
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
}
set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
@ -49,6 +53,9 @@ foreach DESIGN_NAME ${DESIGN_NAMES} {
##################################
# Read timing libraries
read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
if {"SOFA_CHD" == ${DEVICE_NAME}} {
read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib"
}
##################################
# Read post-PnR netlists