From 14062a971ebc32faba620cbe13f4fc38080b5e87 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Sat, 3 Apr 2021 11:12:40 -0600 Subject: [PATCH] fixed vexriscv task template --- .../vexriscv/generate_testbench/config/task_template.conf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/SCRIPT/skywater_openfpga_task/vexriscv/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/vexriscv/generate_testbench/config/task_template.conf index 461d002..d07ca0c 100644 --- a/SCRIPT/skywater_openfpga_task/vexriscv/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/vexriscv/generate_testbench/config/task_template.conf @@ -20,10 +20,10 @@ openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/s openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_auto_clock.xml openfpga_vpr_device_layout=auto -openfpga_vpr_route_chan_width=40 # Don't care about auto chan width +openfpga_vpr_route_chan_width=40 # Don't care openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v -external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml # Don't care about fabric key +external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml # Don't care [ARCHITECTURES] arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_scan_chain_nonLR_caravel_io_skywater130nm.xml