From 13fc082cb3c47fa417290f282b330fbcab1f75b6 Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Mon, 14 Dec 2020 01:16:30 -0700
Subject: [PATCH] [SOFA_HD] Updated verification script

---
 FPGA1212_SOFA_HD_PNR/Verification/Makefile    |  122 +-
 .../ScanChainTestFull_run/run.log             |  167 +
 .../ScanChainTestFull_run/scff_test.vcd       | 7502 ++++++++---------
 .../Verification/fpga_tests.py                |  330 +
 .../Verification/skywater_tests.py            |    2 +
 5 files changed, 4324 insertions(+), 3799 deletions(-)
 create mode 100644 FPGA1212_SOFA_HD_PNR/Verification/fpga_tests.py

diff --git a/FPGA1212_SOFA_HD_PNR/Verification/Makefile b/FPGA1212_SOFA_HD_PNR/Verification/Makefile
index aae5557..8ca6a3d 100644
--- a/FPGA1212_SOFA_HD_PNR/Verification/Makefile
+++ b/FPGA1212_SOFA_HD_PNR/Verification/Makefile
@@ -1,3 +1,5 @@
+##########################################################################################
+##########################################################################################
 
 SHELL=bash
 PYTHON_EXEC=python3.8
@@ -5,70 +7,54 @@ RERUN = 0
 TB = top
 OPTIONS =
 
+BLOCK_MAKE_ACTIONS=init_design place_opt clock_opt_cts
+
 .SILENT:
 .ONESHELL:
 
-UpdatePostPnRNetlist:
+RunTest:
 	source ../config.sh
-	DESIGN_NAME=$${TOP_MODULE:-$${DESIGN_NAME}}
-	echo "Collecting files $${DESIGN_NAME}"
-	cp ../pnr/$${DESIGN_NAME}/outputs_icc2/$${DESIGN_NAME}_icv_in_design.pt.v . || true
-	cp ../$${DESIGN_NAME}/outputs_icc2/$${DESIGN_NAME}_icv_in_design.pt.v . || true
-
-RunPostPnRTest:
-	source ../config.sh
-	INCLUDE_POSTPNR=$${INCLUDE_POSTPNR:-include_postpnr}
-	DESIGN_NAME=$${TOP_MODULE:-$${DESIGN_NAME}}
-	VerificationFile=$${TEST_FILE:-fpga_test}
-	# = = = = = = = = = = = = = = Log Information = = = = = = = = = = = =
-	echo "DESIGN_NAME       = $${DESIGN_NAME}"
-	echo "VerificationFile  = $${DESIGN_NAME}"
-	echo "INCLUDE_FILE      = $${INCLUDE_POSTPNR}"
-	# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-	echo $${VerificationFile}
+	VerificationFile=$${TECHNOLOGY}_tests
 	if [ ! -f "./$${VerificationFile}.py" ]; then
-		echo "Test file not found $${VerificationFile}.py"
+			VerificationFile=fpga_tests
 	fi
 	echo "Using test file $${VerificationFile}.py"
-	Tests=`grep -A 1 "^@cocotb.test" ./$${VerificationFile}.py | grep "def" | sed "s/.*def \(.*\)(.*/\1/g"`
+	Tests=`grep -A 1 "@cocotb.test" ./$${VerificationFile}.py | grep "def" | sed "s/.*def \(.*\)(.*/\1/g"`
 	select RUN_TB in $${Tests}
 	do
 		echo "Running $${RUN_TB} Test"
 		if [[ -d  "$${RUN_TB}_run" ]] && [[ -z "$${RERUN}" ]]; then
-			echo "Skipping copying source, which will skip the compilations";
-			cp *_tests.py ./$${RUN_TB}_run;
-			cd $${RUN_TB}_run; break;
+				echo "Skipping copying source";
+				cp *_tests.py ./$${RUN_TB}_run;
+				cd $${RUN_TB}_run; break;
 		fi
 
 		# = = = = = = = = = = = Prepare Netlist = = = = = = = = = = = = = =
 		# = = = = = = = = = = = Copy python test = = = = = = = = = = = = =
 		mkdir -p "$${RUN_TB}_run"
 		cp $${VerificationFile}.py ./$${RUN_TB}_run
-		cp $${DESIGN_NAME}_icv_in_design.pt.v ./$${RUN_TB}_run/$${DESIGN_NAME}_cocosim.v
-		if [ -d "../*_Verilog/TaskConfigCopy" ]; then
-			TaskDir=`readlink -f ../*_Verilog/TaskConfigCopy`
-			rm -rf ./$${RUN_TB}_run/TaskConfigCopy && ln -s $${TaskDir} ./$${RUN_TB}_run
-		elif  [ -d "../*_task" ]; then
-			TaskDir=`readlink -f ../*_task`
-			rm -rf ./$${RUN_TB}_run/TaskConfigCopy && ln -s $${TaskDir} ./$${RUN_TB}_run/TaskConfigCopy
-		else
-			echo "Task configuration directory not found"
-		fi
-		# = = = = = = = = = = = Enter Run Directory = = = = = = = = = = = = =
-		cd $${RUN_TB}_run
-		cp ../INIT/$${INCLUDE_POSTPNR}.v ./fabric_netlists_cocosim.v
-		echo "\`include \"$$(readlink -f $${DESIGN_NAME}_cocosim.v)\"" >> ./fabric_netlists_cocosim.v
+		# = = = = Make symbolic link to SRC | TaskConfigCopy | TESTBENCH
+		SRCDir=`readlink -f ../*_Verilog/SRC`
+		rm -rf ./$${RUN_TB}_run/SRC && ln -s $${SRCDir} ./$${RUN_TB}_run
+		TaskDir=`readlink -f ../*_Verilog/TaskConfigCopy`
+		rm -rf ./$${RUN_TB}_run/TaskConfigCopy && ln -s $${TaskDir} ./$${RUN_TB}_run
+		TestbenchDir=`readlink -f ../*_Verilog/TESTBENCH`
+		rm -rf ./$${RUN_TB}_run/TESTBENCH && ln -s $${TestbenchDir} ./$${RUN_TB}_run
 
-		# = = = = = = = = = = = Insert Init Signals = = = = = = = = = = = =
+		# = = = = = = = = = = Enter Run Directory = = = = = = = = = = = = =
+		cd $${RUN_TB}_run
+		cp ./SRC/$${DESIGN_NAME}.v ./$${DESIGN_NAME}_cocosim.v
+		cp ./SRC/fabric_netlists.v ./fabric_netlists_cocosim.v
+
+		# = = = = = = = = = = Modify the netlist = = = = = = = = = = = = =
+		sed -i "s/SRC\/$${DESIGN_NAME}/$${DESIGN_NAME}_cocosim/g" fabric_netlists_cocosim.v
+
+		# Insert Init Signals
 		if test -f "../INIT/$${RUN_TB}_init.v"; then
-			echo "Found Initialization file [../INIT/$${RUN_TB}_init.v]"
-			modLineNo=$$(grep -n "module fpga_top" $${DESIGN_NAME}_cocosim.v | cut -f1 -d:)
-			echo $${modLineNo}
-			sed -i "$${modLineNo},\$${/endmodule/d}" $${DESIGN_NAME}_cocosim.v
-			cat ../INIT/$${RUN_TB}_init.v >> $${DESIGN_NAME}_cocosim.v
-			printf "\nendmodule" >> $${DESIGN_NAME}_cocosim.v
-		else
-			echo "No Initialization file found [../INIT/$${RUN_TB}_init.v]"
+				echo "Found initialization file"
+				sed -i "/endmodule/d" $${DESIGN_NAME}_cocosim.v
+				cat ../INIT/$${RUN_TB}_init.v >> $${DESIGN_NAME}_cocosim.v
+				printf "\nendmodule" >> $${DESIGN_NAME}_cocosim.v
 		fi
 
 		# = = = = = = = = Create Makefile to run = = = = = = = = = = = = = =
@@ -81,4 +67,48 @@ RunPostPnRTest:
 		echo "include $(shell cocotb-config --makefiles)/Makefile.sim" >> Makefile
 		break
 	done
-	if [ -z "$$DRY_RUN" ]; then make; fi
\ No newline at end of file
+	make
+
+GenerateNetlist:
+	cd .. && make clean all
+
+GenerateTestBench:
+	cd .. && source ./FPGA22_SPY_Verification/generateTestbench.sh
+
+GenerateSyntheticTestBench:
+	TestbenchDir=`readlink -f ../*_Verilog/TESTBENCH`
+	mkdir -p $$TestbenchDir/AllOne && cp $$TestbenchDir/top/* $$TestbenchDir/AllOne/
+	mkdir -p $$TestbenchDir/AllZero && cp $$TestbenchDir/top/* $$TestbenchDir/AllZero/
+	mkdir -p $$TestbenchDir/Patterned10 && cp $$TestbenchDir/top/* $$TestbenchDir/Patterned10/
+
+	BitStreamLength=(`wc -c $$TestbenchDir/AllOne/fabric_bitstream.bit`)
+	BitStreamLength=$${BitStreamLength[0]}
+	echo "Bitstream Length is $$BitStreamLength "
+
+	for ((i=0; i<$$BitStreamLength; i++)); do printf "1"; done > $$TestbenchDir/AllOne/fabric_bitstream.bit
+	echo "Created AllOne Bitstream"
+	for ((i=0; i<$$BitStreamLength; i++)); do printf "0"; done > $$TestbenchDir/AllZero/fabric_bitstream.bit
+	echo "Created AllZero Bitstream"
+	for ((i=0; i<$$BitStreamLength; i=i+2)); do printf "10"; done > $$TestbenchDir/Patterned10/fabric_bitstream.bit
+	echo "Created Patterned10 Bitstream"
+
+	# Creating PatternedBitstreams
+	PATT=10110
+	PATTLen=`echo $${#PATT}`
+	Remainder=`echo $$(($$BitStreamLength % $$PATTLen))`
+	mkdir -p $$TestbenchDir/Patterned$${PATT} && cp $$TestbenchDir/top/* $$TestbenchDir/Patterned$${PATT}/
+	for ((i=0; i<($$BitStreamLength-$$Remainder); i=i+$$PATTLen)); do printf $$PATT; done > $$TestbenchDir/Patterned$${PATT}/fabric_bitstream.bit
+	printf "$${PATT:0:$$Remainder}">> $$TestbenchDir/Patterned$${PATT}/fabric_bitstream.bit
+	echo "Created Patterned$${PATT} Bitstream"
+
+	# Creating PatternedBitstreams
+	PATT=10110001
+	PATTLen=`echo $${#PATT}`
+	Remainder=`echo $$(($$BitStreamLength % $$PATTLen))`
+	mkdir -p $$TestbenchDir/Patterned$${PATT} && cp $$TestbenchDir/top/* $$TestbenchDir/Patterned$${PATT}/
+	for ((i=0; i<($$BitStreamLength-$$Remainder); i=i+$$PATTLen)); do printf $$PATT; done > $$TestbenchDir/Patterned$${PATT}/fabric_bitstream.bit
+	printf "$${PATT:0:$$Remainder}" >> $$TestbenchDir/Patterned$${PATT}/fabric_bitstream.bit
+	echo "Created Patterned$${PATT} Bitstream"
+
+
+-include Makefile_project
\ No newline at end of file
diff --git a/FPGA1212_SOFA_HD_PNR/Verification/ScanChainTestFull_run/run.log b/FPGA1212_SOFA_HD_PNR/Verification/ScanChainTestFull_run/run.log
index 50d714c..105ef8e 100644
--- a/FPGA1212_SOFA_HD_PNR/Verification/ScanChainTestFull_run/run.log
+++ b/FPGA1212_SOFA_HD_PNR/Verification/ScanChainTestFull_run/run.log
@@ -1854,3 +1854,170 @@ Passed 1 tests (0 skipped)
 *************************************************************************************
 
 Shutting down...
+Found test skywater_tests.ScanChainTestFull
+Running test 1/1: ScanChainTestFull
+Starting test: "ScanChainTestFull"
+Description: None
+Signal received at grid_clb_1__12_ at 8
+Signal received at grid_clb_1__11_ at 8
+Signal received at grid_clb_1__10_ at 8
+Signal received at grid_clb_1__9_ at 8
+Signal received at grid_clb_1__8_ at 8
+Signal received at grid_clb_1__7_ at 8
+Signal received at grid_clb_1__6_ at 8
+Signal received at grid_clb_1__5_ at 8
+Signal received at grid_clb_1__4_ at 8
+Signal received at grid_clb_1__3_ at 8
+Signal received at grid_clb_1__2_ at 8
+Signal received at grid_clb_1__1_ at 8
+Signal received at grid_clb_2__1_ at 8
+Signal received at grid_clb_2__2_ at 8
+Signal received at grid_clb_2__3_ at 8
+Signal received at grid_clb_2__4_ at 8
+Signal received at grid_clb_2__5_ at 8
+Signal received at grid_clb_2__6_ at 8
+Signal received at grid_clb_2__7_ at 8
+Signal received at grid_clb_2__8_ at 8
+Signal received at grid_clb_2__9_ at 8
+Signal received at grid_clb_2__10_ at 8
+Signal received at grid_clb_2__11_ at 8
+Signal received at grid_clb_2__12_ at 8
+Signal received at grid_clb_3__12_ at 8
+Signal received at grid_clb_3__11_ at 9
+Signal received at grid_clb_3__10_ at 8
+Signal received at grid_clb_3__9_ at 8
+Signal received at grid_clb_3__8_ at 8
+Signal received at grid_clb_3__7_ at 8
+Signal received at grid_clb_3__6_ at 8
+Signal received at grid_clb_3__5_ at 8
+Signal received at grid_clb_3__4_ at 8
+Signal received at grid_clb_3__3_ at 8
+Signal received at grid_clb_3__2_ at 8
+Signal received at grid_clb_3__1_ at 8
+Signal received at grid_clb_4__1_ at 8
+Signal received at grid_clb_4__2_ at 8
+Signal received at grid_clb_4__3_ at 8
+Signal received at grid_clb_4__4_ at 8
+Signal received at grid_clb_4__5_ at 8
+Signal received at grid_clb_4__6_ at 8
+Signal received at grid_clb_4__7_ at 8
+Signal received at grid_clb_4__8_ at 8
+Signal received at grid_clb_4__9_ at 8
+Signal received at grid_clb_4__10_ at 8
+Signal received at grid_clb_4__11_ at 8
+Signal received at grid_clb_4__12_ at 8
+Signal received at grid_clb_5__12_ at 8
+Signal received at grid_clb_5__11_ at 8
+Signal received at grid_clb_5__10_ at 8
+Signal received at grid_clb_5__9_ at 8
+Signal received at grid_clb_5__8_ at 8
+Signal received at grid_clb_5__7_ at 8
+Signal received at grid_clb_5__6_ at 8
+Signal received at grid_clb_5__5_ at 8
+Signal received at grid_clb_5__4_ at 8
+Signal received at grid_clb_5__3_ at 8
+Signal received at grid_clb_5__2_ at 8
+Signal received at grid_clb_5__1_ at 8
+Signal received at grid_clb_6__1_ at 8
+Signal received at grid_clb_6__2_ at 8
+Signal received at grid_clb_6__3_ at 8
+Signal received at grid_clb_6__4_ at 8
+Signal received at grid_clb_6__5_ at 8
+Signal received at grid_clb_6__6_ at 8
+Signal received at grid_clb_6__7_ at 8
+Signal received at grid_clb_6__8_ at 8
+Signal received at grid_clb_6__9_ at 8
+Signal received at grid_clb_6__10_ at 8
+Signal received at grid_clb_6__11_ at 8
+Signal received at grid_clb_6__12_ at 8
+Signal received at grid_clb_7__12_ at 8
+Signal received at grid_clb_7__11_ at 8
+Signal received at grid_clb_7__10_ at 8
+Signal received at grid_clb_7__9_ at 8
+Signal received at grid_clb_7__8_ at 8
+Signal received at grid_clb_7__7_ at 8
+Signal received at grid_clb_7__6_ at 8
+Signal received at grid_clb_7__5_ at 8
+Signal received at grid_clb_7__4_ at 8
+Signal received at grid_clb_7__3_ at 8
+Signal received at grid_clb_7__2_ at 8
+Signal received at grid_clb_7__1_ at 8
+Signal received at grid_clb_8__1_ at 8
+Signal received at grid_clb_8__2_ at 8
+Signal received at grid_clb_8__3_ at 8
+Signal received at grid_clb_8__4_ at 8
+Signal received at grid_clb_8__5_ at 8
+Signal received at grid_clb_8__6_ at 8
+Signal received at grid_clb_8__7_ at 8
+Signal received at grid_clb_8__8_ at 8
+Signal received at grid_clb_8__9_ at 8
+Signal received at grid_clb_8__10_ at 8
+Signal received at grid_clb_8__11_ at 8
+Signal received at grid_clb_8__12_ at 8
+Signal received at grid_clb_9__12_ at 8
+Signal received at grid_clb_9__11_ at 8
+Signal received at grid_clb_9__10_ at 8
+Signal received at grid_clb_9__9_ at 8
+Signal received at grid_clb_9__8_ at 8
+Signal received at grid_clb_9__7_ at 8
+Signal received at grid_clb_9__6_ at 8
+Signal received at grid_clb_9__5_ at 8
+Signal received at grid_clb_9__4_ at 8
+Signal received at grid_clb_9__3_ at 8
+Signal received at grid_clb_9__2_ at 8
+Signal received at grid_clb_9__1_ at 8
+Signal received at grid_clb_10__1_ at 8
+Signal received at grid_clb_10__2_ at 8
+Signal received at grid_clb_10__3_ at 8
+Signal received at grid_clb_10__4_ at 8
+Signal received at grid_clb_10__5_ at 8
+Signal received at grid_clb_10__6_ at 8
+Signal received at grid_clb_10__7_ at 8
+Signal received at grid_clb_10__8_ at 8
+Signal received at grid_clb_10__9_ at 8
+Signal received at grid_clb_10__10_ at 8
+Signal received at grid_clb_10__11_ at 8
+Signal received at grid_clb_10__12_ at 8
+Signal received at grid_clb_11__12_ at 8
+Signal received at grid_clb_11__11_ at 8
+Signal received at grid_clb_11__10_ at 8
+Signal received at grid_clb_11__9_ at 8
+Signal received at grid_clb_11__8_ at 8
+Signal received at grid_clb_11__7_ at 8
+Signal received at grid_clb_11__6_ at 8
+Signal received at grid_clb_11__5_ at 8
+Signal received at grid_clb_11__4_ at 8
+Signal received at grid_clb_11__3_ at 8
+Signal received at grid_clb_11__2_ at 8
+Signal received at grid_clb_11__1_ at 8
+Signal received at grid_clb_12__1_ at 8
+Signal received at grid_clb_12__2_ at 8
+Signal received at grid_clb_12__3_ at 8
+Signal received at grid_clb_12__4_ at 8
+Signal received at grid_clb_12__5_ at 8
+Signal received at grid_clb_12__6_ at 8
+Signal received at grid_clb_12__7_ at 8
+Signal received at grid_clb_12__8_ at 8
+Signal received at grid_clb_12__9_ at 8
+Signal received at grid_clb_12__10_ at 8
+Signal received at grid_clb_12__11_ at 8
+Signal received at grid_clb_12__12_ at 8
+Simulation Finished in clocks 1152
+Per Grid 8.0
+Test Passed: ScanChainTestFull
+Passed 1 tests (0 skipped)
+******************************************************************************************
+** TEST                              PASS/FAIL  SIM TIME(NS)  REAL TIME(S)  RATIO(NS/S) **
+******************************************************************************************
+** skywater_tests.ScanChainTestFull    PASS        11580.00          0.99     11725.64  **
+******************************************************************************************
+
+*************************************************************************************
+**                                 ERRORS : 0                                      **
+*************************************************************************************
+**                               SIM TIME : 11580.00 NS                            **
+**                              REAL TIME : 1.02 S                                 **
+**                        SIM / REAL TIME : 11333.51 NS/S                          **
+*************************************************************************************
+
+Shutting down...
diff --git a/FPGA1212_SOFA_HD_PNR/Verification/ScanChainTestFull_run/scff_test.vcd b/FPGA1212_SOFA_HD_PNR/Verification/ScanChainTestFull_run/scff_test.vcd
index 2d6f77a..0fa003a 100644
--- a/FPGA1212_SOFA_HD_PNR/Verification/ScanChainTestFull_run/scff_test.vcd
+++ b/FPGA1212_SOFA_HD_PNR/Verification/ScanChainTestFull_run/scff_test.vcd
@@ -1,5 +1,5 @@
 $date
-	Sat Nov 21 15:38:56 2020
+	Sun Nov 22 16:03:39 2020
 $end
 $version
 	QuestaSim Version 2019.4
@@ -450,214 +450,214 @@ $var wire 1 M$ chanx_left_out [17] $end
 $var wire 1 N$ chanx_left_out [18] $end
 $var wire 1 O$ chanx_left_out [19] $end
 $var wire 1 P$ ccff_tail [0] $end
-$var wire 1 Q$ SC_IN_TOP $end
-$var wire 1 R$ SC_OUT_BOT $end
 $var wire 1 $ SC_IN_BOT $end
-$var wire 1 S$ SC_OUT_TOP $end
-$var wire 1 T$ prog_clk_0_S_in $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 V$ prog_clk_0 $end
-$var wire 1 W$ mux_tree_tapbuf_size2_0_sram [0] $end
-$var wire 1 X$ mux_tree_tapbuf_size2_0_sram [1] $end
-$var wire 1 Y$ mux_tree_tapbuf_size2_10_sram [0] $end
-$var wire 1 Z$ mux_tree_tapbuf_size2_10_sram [1] $end
-$var wire 1 [$ mux_tree_tapbuf_size2_11_sram [0] $end
-$var wire 1 \$ mux_tree_tapbuf_size2_11_sram [1] $end
-$var wire 1 ]$ mux_tree_tapbuf_size2_12_sram [0] $end
-$var wire 1 ^$ mux_tree_tapbuf_size2_12_sram [1] $end
-$var wire 1 _$ mux_tree_tapbuf_size2_13_sram [0] $end
-$var wire 1 `$ mux_tree_tapbuf_size2_13_sram [1] $end
-$var wire 1 a$ mux_tree_tapbuf_size2_14_sram [0] $end
-$var wire 1 b$ mux_tree_tapbuf_size2_14_sram [1] $end
-$var wire 1 c$ mux_tree_tapbuf_size2_15_sram [0] $end
-$var wire 1 d$ mux_tree_tapbuf_size2_15_sram [1] $end
-$var wire 1 e$ mux_tree_tapbuf_size2_16_sram [0] $end
-$var wire 1 f$ mux_tree_tapbuf_size2_16_sram [1] $end
-$var wire 1 g$ mux_tree_tapbuf_size2_17_sram [0] $end
-$var wire 1 h$ mux_tree_tapbuf_size2_17_sram [1] $end
-$var wire 1 i$ mux_tree_tapbuf_size2_18_sram [0] $end
-$var wire 1 j$ mux_tree_tapbuf_size2_18_sram [1] $end
-$var wire 1 k$ mux_tree_tapbuf_size2_19_sram [0] $end
-$var wire 1 l$ mux_tree_tapbuf_size2_19_sram [1] $end
-$var wire 1 m$ mux_tree_tapbuf_size2_1_sram [0] $end
-$var wire 1 n$ mux_tree_tapbuf_size2_1_sram [1] $end
-$var wire 1 o$ mux_tree_tapbuf_size2_20_sram [0] $end
-$var wire 1 p$ mux_tree_tapbuf_size2_20_sram [1] $end
-$var wire 1 q$ mux_tree_tapbuf_size2_21_sram [0] $end
-$var wire 1 r$ mux_tree_tapbuf_size2_21_sram [1] $end
-$var wire 1 s$ mux_tree_tapbuf_size2_22_sram [0] $end
-$var wire 1 t$ mux_tree_tapbuf_size2_22_sram [1] $end
-$var wire 1 u$ mux_tree_tapbuf_size2_23_sram [0] $end
-$var wire 1 v$ mux_tree_tapbuf_size2_23_sram [1] $end
-$var wire 1 w$ mux_tree_tapbuf_size2_2_sram [0] $end
-$var wire 1 x$ mux_tree_tapbuf_size2_2_sram [1] $end
-$var wire 1 y$ mux_tree_tapbuf_size2_3_sram [0] $end
-$var wire 1 z$ mux_tree_tapbuf_size2_3_sram [1] $end
-$var wire 1 {$ mux_tree_tapbuf_size2_4_sram [0] $end
-$var wire 1 |$ mux_tree_tapbuf_size2_4_sram [1] $end
-$var wire 1 }$ mux_tree_tapbuf_size2_5_sram [0] $end
-$var wire 1 ~$ mux_tree_tapbuf_size2_5_sram [1] $end
-$var wire 1 !% mux_tree_tapbuf_size2_6_sram [0] $end
-$var wire 1 "% mux_tree_tapbuf_size2_6_sram [1] $end
-$var wire 1 #% mux_tree_tapbuf_size2_7_sram [0] $end
-$var wire 1 $% mux_tree_tapbuf_size2_7_sram [1] $end
-$var wire 1 %% mux_tree_tapbuf_size2_8_sram [0] $end
-$var wire 1 &% mux_tree_tapbuf_size2_8_sram [1] $end
-$var wire 1 '% mux_tree_tapbuf_size2_9_sram [0] $end
-$var wire 1 (% mux_tree_tapbuf_size2_9_sram [1] $end
-$var wire 1 )% mux_tree_tapbuf_size2_mem_0_ccff_tail [0] $end
-$var wire 1 *% mux_tree_tapbuf_size2_mem_10_ccff_tail [0] $end
-$var wire 1 +% mux_tree_tapbuf_size2_mem_11_ccff_tail [0] $end
-$var wire 1 ,% mux_tree_tapbuf_size2_mem_12_ccff_tail [0] $end
-$var wire 1 -% mux_tree_tapbuf_size2_mem_13_ccff_tail [0] $end
-$var wire 1 .% mux_tree_tapbuf_size2_mem_14_ccff_tail [0] $end
-$var wire 1 /% mux_tree_tapbuf_size2_mem_15_ccff_tail [0] $end
-$var wire 1 0% mux_tree_tapbuf_size2_mem_16_ccff_tail [0] $end
-$var wire 1 1% mux_tree_tapbuf_size2_mem_17_ccff_tail [0] $end
-$var wire 1 2% mux_tree_tapbuf_size2_mem_18_ccff_tail [0] $end
-$var wire 1 3% mux_tree_tapbuf_size2_mem_19_ccff_tail [0] $end
-$var wire 1 4% mux_tree_tapbuf_size2_mem_1_ccff_tail [0] $end
-$var wire 1 5% mux_tree_tapbuf_size2_mem_20_ccff_tail [0] $end
-$var wire 1 6% mux_tree_tapbuf_size2_mem_21_ccff_tail [0] $end
-$var wire 1 7% mux_tree_tapbuf_size2_mem_22_ccff_tail [0] $end
-$var wire 1 8% mux_tree_tapbuf_size2_mem_2_ccff_tail [0] $end
-$var wire 1 9% mux_tree_tapbuf_size2_mem_3_ccff_tail [0] $end
-$var wire 1 :% mux_tree_tapbuf_size2_mem_4_ccff_tail [0] $end
-$var wire 1 ;% mux_tree_tapbuf_size2_mem_5_ccff_tail [0] $end
-$var wire 1 <% mux_tree_tapbuf_size2_mem_6_ccff_tail [0] $end
-$var wire 1 =% mux_tree_tapbuf_size2_mem_7_ccff_tail [0] $end
-$var wire 1 >% mux_tree_tapbuf_size2_mem_8_ccff_tail [0] $end
-$var wire 1 ?% mux_tree_tapbuf_size2_mem_9_ccff_tail [0] $end
-$var wire 1 @% mux_tree_tapbuf_size3_0_sram [0] $end
-$var wire 1 A% mux_tree_tapbuf_size3_0_sram [1] $end
-$var wire 1 B% mux_tree_tapbuf_size3_1_sram [0] $end
-$var wire 1 C% mux_tree_tapbuf_size3_1_sram [1] $end
-$var wire 1 D% mux_tree_tapbuf_size3_2_sram [0] $end
-$var wire 1 E% mux_tree_tapbuf_size3_2_sram [1] $end
-$var wire 1 F% mux_tree_tapbuf_size3_mem_0_ccff_tail [0] $end
-$var wire 1 G% mux_tree_tapbuf_size3_mem_1_ccff_tail [0] $end
-$var wire 1 H% mux_tree_tapbuf_size3_mem_2_ccff_tail [0] $end
-$var wire 1 I% mux_tree_tapbuf_size5_0_sram [0] $end
-$var wire 1 J% mux_tree_tapbuf_size5_0_sram [1] $end
-$var wire 1 K% mux_tree_tapbuf_size5_0_sram [2] $end
-$var wire 1 L% mux_tree_tapbuf_size5_1_sram [0] $end
-$var wire 1 M% mux_tree_tapbuf_size5_1_sram [1] $end
-$var wire 1 N% mux_tree_tapbuf_size5_1_sram [2] $end
-$var wire 1 O% mux_tree_tapbuf_size5_2_sram [0] $end
-$var wire 1 P% mux_tree_tapbuf_size5_2_sram [1] $end
-$var wire 1 Q% mux_tree_tapbuf_size5_2_sram [2] $end
-$var wire 1 R% mux_tree_tapbuf_size5_3_sram [0] $end
-$var wire 1 S% mux_tree_tapbuf_size5_3_sram [1] $end
-$var wire 1 T% mux_tree_tapbuf_size5_3_sram [2] $end
-$var wire 1 U% mux_tree_tapbuf_size5_mem_0_ccff_tail [0] $end
-$var wire 1 V% mux_tree_tapbuf_size5_mem_1_ccff_tail [0] $end
-$var wire 1 W% mux_tree_tapbuf_size5_mem_2_ccff_tail [0] $end
-$var wire 1 X% mux_tree_tapbuf_size5_mem_3_ccff_tail [0] $end
-$var wire 1 Y% mux_tree_tapbuf_size6_0_sram [0] $end
-$var wire 1 Z% mux_tree_tapbuf_size6_0_sram [1] $end
-$var wire 1 [% mux_tree_tapbuf_size6_0_sram [2] $end
-$var wire 1 \% mux_tree_tapbuf_size6_1_sram [0] $end
-$var wire 1 ]% mux_tree_tapbuf_size6_1_sram [1] $end
-$var wire 1 ^% mux_tree_tapbuf_size6_1_sram [2] $end
-$var wire 1 _% mux_tree_tapbuf_size6_2_sram [0] $end
-$var wire 1 `% mux_tree_tapbuf_size6_2_sram [1] $end
-$var wire 1 a% mux_tree_tapbuf_size6_2_sram [2] $end
-$var wire 1 b% mux_tree_tapbuf_size6_3_sram [0] $end
-$var wire 1 c% mux_tree_tapbuf_size6_3_sram [1] $end
-$var wire 1 d% mux_tree_tapbuf_size6_3_sram [2] $end
-$var wire 1 e% mux_tree_tapbuf_size6_mem_0_ccff_tail [0] $end
-$var wire 1 f% mux_tree_tapbuf_size6_mem_1_ccff_tail [0] $end
-$var wire 1 g% mux_tree_tapbuf_size6_mem_2_ccff_tail [0] $end
-$var wire 1 h% mux_tree_tapbuf_size6_mem_3_ccff_tail [0] $end
-$var wire 1 i% SYNOPSYS_UNCONNECTED_1 $end
-$var wire 1 j% SYNOPSYS_UNCONNECTED_2 $end
-$var wire 1 k% SYNOPSYS_UNCONNECTED_3 $end
-$var wire 1 l% optlc_net_98 $end
-$var wire 1 m% SYNOPSYS_UNCONNECTED_4 $end
-$var wire 1 n% SYNOPSYS_UNCONNECTED_5 $end
-$var wire 1 o% SYNOPSYS_UNCONNECTED_6 $end
-$var wire 1 p% SYNOPSYS_UNCONNECTED_7 $end
-$var wire 1 q% SYNOPSYS_UNCONNECTED_8 $end
-$var wire 1 r% SYNOPSYS_UNCONNECTED_9 $end
-$var wire 1 s% optlc_net_97 $end
-$var wire 1 t% SYNOPSYS_UNCONNECTED_10 $end
-$var wire 1 u% SYNOPSYS_UNCONNECTED_11 $end
-$var wire 1 v% SYNOPSYS_UNCONNECTED_12 $end
-$var wire 1 w% SYNOPSYS_UNCONNECTED_13 $end
-$var wire 1 x% SYNOPSYS_UNCONNECTED_14 $end
-$var wire 1 y% SYNOPSYS_UNCONNECTED_15 $end
-$var wire 1 z% SYNOPSYS_UNCONNECTED_16 $end
-$var wire 1 {% SYNOPSYS_UNCONNECTED_17 $end
-$var wire 1 |% SYNOPSYS_UNCONNECTED_18 $end
-$var wire 1 }% SYNOPSYS_UNCONNECTED_19 $end
-$var wire 1 ~% SYNOPSYS_UNCONNECTED_20 $end
-$var wire 1 !& SYNOPSYS_UNCONNECTED_21 $end
-$var wire 1 "& SYNOPSYS_UNCONNECTED_22 $end
-$var wire 1 #& SYNOPSYS_UNCONNECTED_23 $end
-$var wire 1 $& SYNOPSYS_UNCONNECTED_24 $end
-$var wire 1 %& SYNOPSYS_UNCONNECTED_25 $end
-$var wire 1 && SYNOPSYS_UNCONNECTED_26 $end
-$var wire 1 '& optlc_net_95 $end
-$var wire 1 (& SYNOPSYS_UNCONNECTED_27 $end
-$var wire 1 )& SYNOPSYS_UNCONNECTED_28 $end
-$var wire 1 *& SYNOPSYS_UNCONNECTED_29 $end
-$var wire 1 +& SYNOPSYS_UNCONNECTED_30 $end
-$var wire 1 ,& SYNOPSYS_UNCONNECTED_31 $end
-$var wire 1 -& SYNOPSYS_UNCONNECTED_32 $end
-$var wire 1 .& SYNOPSYS_UNCONNECTED_33 $end
-$var wire 1 /& SYNOPSYS_UNCONNECTED_34 $end
-$var wire 1 0& SYNOPSYS_UNCONNECTED_35 $end
-$var wire 1 1& SYNOPSYS_UNCONNECTED_36 $end
-$var wire 1 2& SYNOPSYS_UNCONNECTED_37 $end
-$var wire 1 3& SYNOPSYS_UNCONNECTED_38 $end
-$var wire 1 4& SYNOPSYS_UNCONNECTED_39 $end
-$var wire 1 5& SYNOPSYS_UNCONNECTED_40 $end
-$var wire 1 6& SYNOPSYS_UNCONNECTED_41 $end
-$var wire 1 7& SYNOPSYS_UNCONNECTED_42 $end
-$var wire 1 8& SYNOPSYS_UNCONNECTED_43 $end
-$var wire 1 9& SYNOPSYS_UNCONNECTED_44 $end
-$var wire 1 :& SYNOPSYS_UNCONNECTED_45 $end
-$var wire 1 ;& SYNOPSYS_UNCONNECTED_46 $end
-$var wire 1 <& optlc_net_96 $end
-$var wire 1 =& SYNOPSYS_UNCONNECTED_47 $end
-$var wire 1 >& SYNOPSYS_UNCONNECTED_48 $end
-$var wire 1 ?& SYNOPSYS_UNCONNECTED_49 $end
-$var wire 1 @& SYNOPSYS_UNCONNECTED_50 $end
-$var wire 1 A& SYNOPSYS_UNCONNECTED_51 $end
-$var wire 1 B& SYNOPSYS_UNCONNECTED_52 $end
-$var wire 1 C& SYNOPSYS_UNCONNECTED_53 $end
-$var wire 1 D& SYNOPSYS_UNCONNECTED_54 $end
-$var wire 1 E& SYNOPSYS_UNCONNECTED_55 $end
-$var wire 1 F& SYNOPSYS_UNCONNECTED_56 $end
-$var wire 1 G& SYNOPSYS_UNCONNECTED_57 $end
-$var wire 1 H& SYNOPSYS_UNCONNECTED_58 $end
-$var wire 1 I& SYNOPSYS_UNCONNECTED_59 $end
-$var wire 1 J& SYNOPSYS_UNCONNECTED_60 $end
-$var wire 1 K& SYNOPSYS_UNCONNECTED_61 $end
-$var wire 1 L& SYNOPSYS_UNCONNECTED_62 $end
-$var wire 1 M& SYNOPSYS_UNCONNECTED_63 $end
-$var wire 1 N& SYNOPSYS_UNCONNECTED_64 $end
-$var wire 1 O& SYNOPSYS_UNCONNECTED_65 $end
-$var wire 1 P& SYNOPSYS_UNCONNECTED_66 $end
-$var wire 1 Q& SYNOPSYS_UNCONNECTED_67 $end
-$var wire 1 R& SYNOPSYS_UNCONNECTED_68 $end
-$var wire 1 S& SYNOPSYS_UNCONNECTED_69 $end
-$var wire 1 T& SYNOPSYS_UNCONNECTED_70 $end
-$var wire 1 U& SYNOPSYS_UNCONNECTED_71 $end
-$var wire 1 V& SYNOPSYS_UNCONNECTED_72 $end
-$var wire 1 W& ropt_net_114 $end
-$var wire 1 X& SYNOPSYS_UNCONNECTED_73 $end
-$var wire 1 Y& SYNOPSYS_UNCONNECTED_74 $end
-$var wire 1 Z& SYNOPSYS_UNCONNECTED_75 $end
-$var wire 1 [& SYNOPSYS_UNCONNECTED_76 $end
-$var wire 1 \& SYNOPSYS_UNCONNECTED_77 $end
-$var wire 1 ]& SYNOPSYS_UNCONNECTED_78 $end
-$var wire 1 ^& SYNOPSYS_UNCONNECTED_79 $end
-$var wire 1 _& SYNOPSYS_UNCONNECTED_80 $end
-$var wire 1 `& SYNOPSYS_UNCONNECTED_81 $end
-$var wire 1 a& SYNOPSYS_UNCONNECTED_82 $end
-$var wire 1 b& ropt_net_116 $end
-$var wire 1 c& ropt_net_115 $end
+$var wire 1 Q$ SC_OUT_BOT $end
+$var wire 1 R$ prog_clk_0_S_in $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 T$ prog_clk_0 $end
+$var wire 1 U$ mux_tree_tapbuf_size2_0_sram [0] $end
+$var wire 1 V$ mux_tree_tapbuf_size2_0_sram [1] $end
+$var wire 1 W$ mux_tree_tapbuf_size2_10_sram [0] $end
+$var wire 1 X$ mux_tree_tapbuf_size2_10_sram [1] $end
+$var wire 1 Y$ mux_tree_tapbuf_size2_11_sram [0] $end
+$var wire 1 Z$ mux_tree_tapbuf_size2_11_sram [1] $end
+$var wire 1 [$ mux_tree_tapbuf_size2_12_sram [0] $end
+$var wire 1 \$ mux_tree_tapbuf_size2_12_sram [1] $end
+$var wire 1 ]$ mux_tree_tapbuf_size2_13_sram [0] $end
+$var wire 1 ^$ mux_tree_tapbuf_size2_13_sram [1] $end
+$var wire 1 _$ mux_tree_tapbuf_size2_14_sram [0] $end
+$var wire 1 `$ mux_tree_tapbuf_size2_14_sram [1] $end
+$var wire 1 a$ mux_tree_tapbuf_size2_15_sram [0] $end
+$var wire 1 b$ mux_tree_tapbuf_size2_15_sram [1] $end
+$var wire 1 c$ mux_tree_tapbuf_size2_16_sram [0] $end
+$var wire 1 d$ mux_tree_tapbuf_size2_16_sram [1] $end
+$var wire 1 e$ mux_tree_tapbuf_size2_17_sram [0] $end
+$var wire 1 f$ mux_tree_tapbuf_size2_17_sram [1] $end
+$var wire 1 g$ mux_tree_tapbuf_size2_18_sram [0] $end
+$var wire 1 h$ mux_tree_tapbuf_size2_18_sram [1] $end
+$var wire 1 i$ mux_tree_tapbuf_size2_19_sram [0] $end
+$var wire 1 j$ mux_tree_tapbuf_size2_19_sram [1] $end
+$var wire 1 k$ mux_tree_tapbuf_size2_1_sram [0] $end
+$var wire 1 l$ mux_tree_tapbuf_size2_1_sram [1] $end
+$var wire 1 m$ mux_tree_tapbuf_size2_20_sram [0] $end
+$var wire 1 n$ mux_tree_tapbuf_size2_20_sram [1] $end
+$var wire 1 o$ mux_tree_tapbuf_size2_21_sram [0] $end
+$var wire 1 p$ mux_tree_tapbuf_size2_21_sram [1] $end
+$var wire 1 q$ mux_tree_tapbuf_size2_22_sram [0] $end
+$var wire 1 r$ mux_tree_tapbuf_size2_22_sram [1] $end
+$var wire 1 s$ mux_tree_tapbuf_size2_23_sram [0] $end
+$var wire 1 t$ mux_tree_tapbuf_size2_23_sram [1] $end
+$var wire 1 u$ mux_tree_tapbuf_size2_2_sram [0] $end
+$var wire 1 v$ mux_tree_tapbuf_size2_2_sram [1] $end
+$var wire 1 w$ mux_tree_tapbuf_size2_3_sram [0] $end
+$var wire 1 x$ mux_tree_tapbuf_size2_3_sram [1] $end
+$var wire 1 y$ mux_tree_tapbuf_size2_4_sram [0] $end
+$var wire 1 z$ mux_tree_tapbuf_size2_4_sram [1] $end
+$var wire 1 {$ mux_tree_tapbuf_size2_5_sram [0] $end
+$var wire 1 |$ mux_tree_tapbuf_size2_5_sram [1] $end
+$var wire 1 }$ mux_tree_tapbuf_size2_6_sram [0] $end
+$var wire 1 ~$ mux_tree_tapbuf_size2_6_sram [1] $end
+$var wire 1 !% mux_tree_tapbuf_size2_7_sram [0] $end
+$var wire 1 "% mux_tree_tapbuf_size2_7_sram [1] $end
+$var wire 1 #% mux_tree_tapbuf_size2_8_sram [0] $end
+$var wire 1 $% mux_tree_tapbuf_size2_8_sram [1] $end
+$var wire 1 %% mux_tree_tapbuf_size2_9_sram [0] $end
+$var wire 1 &% mux_tree_tapbuf_size2_9_sram [1] $end
+$var wire 1 '% mux_tree_tapbuf_size2_mem_0_ccff_tail [0] $end
+$var wire 1 (% mux_tree_tapbuf_size2_mem_10_ccff_tail [0] $end
+$var wire 1 )% mux_tree_tapbuf_size2_mem_11_ccff_tail [0] $end
+$var wire 1 *% mux_tree_tapbuf_size2_mem_12_ccff_tail [0] $end
+$var wire 1 +% mux_tree_tapbuf_size2_mem_13_ccff_tail [0] $end
+$var wire 1 ,% mux_tree_tapbuf_size2_mem_14_ccff_tail [0] $end
+$var wire 1 -% mux_tree_tapbuf_size2_mem_15_ccff_tail [0] $end
+$var wire 1 .% mux_tree_tapbuf_size2_mem_16_ccff_tail [0] $end
+$var wire 1 /% mux_tree_tapbuf_size2_mem_17_ccff_tail [0] $end
+$var wire 1 0% mux_tree_tapbuf_size2_mem_18_ccff_tail [0] $end
+$var wire 1 1% mux_tree_tapbuf_size2_mem_19_ccff_tail [0] $end
+$var wire 1 2% mux_tree_tapbuf_size2_mem_1_ccff_tail [0] $end
+$var wire 1 3% mux_tree_tapbuf_size2_mem_20_ccff_tail [0] $end
+$var wire 1 4% mux_tree_tapbuf_size2_mem_21_ccff_tail [0] $end
+$var wire 1 5% mux_tree_tapbuf_size2_mem_22_ccff_tail [0] $end
+$var wire 1 6% mux_tree_tapbuf_size2_mem_2_ccff_tail [0] $end
+$var wire 1 7% mux_tree_tapbuf_size2_mem_3_ccff_tail [0] $end
+$var wire 1 8% mux_tree_tapbuf_size2_mem_4_ccff_tail [0] $end
+$var wire 1 9% mux_tree_tapbuf_size2_mem_5_ccff_tail [0] $end
+$var wire 1 :% mux_tree_tapbuf_size2_mem_6_ccff_tail [0] $end
+$var wire 1 ;% mux_tree_tapbuf_size2_mem_7_ccff_tail [0] $end
+$var wire 1 <% mux_tree_tapbuf_size2_mem_8_ccff_tail [0] $end
+$var wire 1 =% mux_tree_tapbuf_size2_mem_9_ccff_tail [0] $end
+$var wire 1 >% mux_tree_tapbuf_size3_0_sram [0] $end
+$var wire 1 ?% mux_tree_tapbuf_size3_0_sram [1] $end
+$var wire 1 @% mux_tree_tapbuf_size3_1_sram [0] $end
+$var wire 1 A% mux_tree_tapbuf_size3_1_sram [1] $end
+$var wire 1 B% mux_tree_tapbuf_size3_2_sram [0] $end
+$var wire 1 C% mux_tree_tapbuf_size3_2_sram [1] $end
+$var wire 1 D% mux_tree_tapbuf_size3_mem_0_ccff_tail [0] $end
+$var wire 1 E% mux_tree_tapbuf_size3_mem_1_ccff_tail [0] $end
+$var wire 1 F% mux_tree_tapbuf_size3_mem_2_ccff_tail [0] $end
+$var wire 1 G% mux_tree_tapbuf_size5_0_sram [0] $end
+$var wire 1 H% mux_tree_tapbuf_size5_0_sram [1] $end
+$var wire 1 I% mux_tree_tapbuf_size5_0_sram [2] $end
+$var wire 1 J% mux_tree_tapbuf_size5_1_sram [0] $end
+$var wire 1 K% mux_tree_tapbuf_size5_1_sram [1] $end
+$var wire 1 L% mux_tree_tapbuf_size5_1_sram [2] $end
+$var wire 1 M% mux_tree_tapbuf_size5_2_sram [0] $end
+$var wire 1 N% mux_tree_tapbuf_size5_2_sram [1] $end
+$var wire 1 O% mux_tree_tapbuf_size5_2_sram [2] $end
+$var wire 1 P% mux_tree_tapbuf_size5_3_sram [0] $end
+$var wire 1 Q% mux_tree_tapbuf_size5_3_sram [1] $end
+$var wire 1 R% mux_tree_tapbuf_size5_3_sram [2] $end
+$var wire 1 S% mux_tree_tapbuf_size5_mem_0_ccff_tail [0] $end
+$var wire 1 T% mux_tree_tapbuf_size5_mem_1_ccff_tail [0] $end
+$var wire 1 U% mux_tree_tapbuf_size5_mem_2_ccff_tail [0] $end
+$var wire 1 V% mux_tree_tapbuf_size5_mem_3_ccff_tail [0] $end
+$var wire 1 W% mux_tree_tapbuf_size6_0_sram [0] $end
+$var wire 1 X% mux_tree_tapbuf_size6_0_sram [1] $end
+$var wire 1 Y% mux_tree_tapbuf_size6_0_sram [2] $end
+$var wire 1 Z% mux_tree_tapbuf_size6_1_sram [0] $end
+$var wire 1 [% mux_tree_tapbuf_size6_1_sram [1] $end
+$var wire 1 \% mux_tree_tapbuf_size6_1_sram [2] $end
+$var wire 1 ]% mux_tree_tapbuf_size6_2_sram [0] $end
+$var wire 1 ^% mux_tree_tapbuf_size6_2_sram [1] $end
+$var wire 1 _% mux_tree_tapbuf_size6_2_sram [2] $end
+$var wire 1 `% mux_tree_tapbuf_size6_3_sram [0] $end
+$var wire 1 a% mux_tree_tapbuf_size6_3_sram [1] $end
+$var wire 1 b% mux_tree_tapbuf_size6_3_sram [2] $end
+$var wire 1 c% mux_tree_tapbuf_size6_mem_0_ccff_tail [0] $end
+$var wire 1 d% mux_tree_tapbuf_size6_mem_1_ccff_tail [0] $end
+$var wire 1 e% mux_tree_tapbuf_size6_mem_2_ccff_tail [0] $end
+$var wire 1 f% mux_tree_tapbuf_size6_mem_3_ccff_tail [0] $end
+$var wire 1 g% SYNOPSYS_UNCONNECTED_1 $end
+$var wire 1 h% SYNOPSYS_UNCONNECTED_2 $end
+$var wire 1 i% SYNOPSYS_UNCONNECTED_3 $end
+$var wire 1 j% optlc_net_92 $end
+$var wire 1 k% SYNOPSYS_UNCONNECTED_4 $end
+$var wire 1 l% SYNOPSYS_UNCONNECTED_5 $end
+$var wire 1 m% SYNOPSYS_UNCONNECTED_6 $end
+$var wire 1 n% optlc_net_95 $end
+$var wire 1 o% SYNOPSYS_UNCONNECTED_7 $end
+$var wire 1 p% SYNOPSYS_UNCONNECTED_8 $end
+$var wire 1 q% SYNOPSYS_UNCONNECTED_9 $end
+$var wire 1 r% optlc_net_93 $end
+$var wire 1 s% SYNOPSYS_UNCONNECTED_10 $end
+$var wire 1 t% SYNOPSYS_UNCONNECTED_11 $end
+$var wire 1 u% SYNOPSYS_UNCONNECTED_12 $end
+$var wire 1 v% SYNOPSYS_UNCONNECTED_13 $end
+$var wire 1 w% SYNOPSYS_UNCONNECTED_14 $end
+$var wire 1 x% SYNOPSYS_UNCONNECTED_15 $end
+$var wire 1 y% SYNOPSYS_UNCONNECTED_16 $end
+$var wire 1 z% SYNOPSYS_UNCONNECTED_17 $end
+$var wire 1 {% SYNOPSYS_UNCONNECTED_18 $end
+$var wire 1 |% SYNOPSYS_UNCONNECTED_19 $end
+$var wire 1 }% SYNOPSYS_UNCONNECTED_20 $end
+$var wire 1 ~% SYNOPSYS_UNCONNECTED_21 $end
+$var wire 1 !& SYNOPSYS_UNCONNECTED_22 $end
+$var wire 1 "& SYNOPSYS_UNCONNECTED_23 $end
+$var wire 1 #& SYNOPSYS_UNCONNECTED_24 $end
+$var wire 1 $& SYNOPSYS_UNCONNECTED_25 $end
+$var wire 1 %& SYNOPSYS_UNCONNECTED_26 $end
+$var wire 1 && SYNOPSYS_UNCONNECTED_27 $end
+$var wire 1 '& SYNOPSYS_UNCONNECTED_28 $end
+$var wire 1 (& SYNOPSYS_UNCONNECTED_29 $end
+$var wire 1 )& SYNOPSYS_UNCONNECTED_30 $end
+$var wire 1 *& SYNOPSYS_UNCONNECTED_31 $end
+$var wire 1 +& SYNOPSYS_UNCONNECTED_32 $end
+$var wire 1 ,& optlc_net_94 $end
+$var wire 1 -& SYNOPSYS_UNCONNECTED_33 $end
+$var wire 1 .& SYNOPSYS_UNCONNECTED_34 $end
+$var wire 1 /& SYNOPSYS_UNCONNECTED_35 $end
+$var wire 1 0& SYNOPSYS_UNCONNECTED_36 $end
+$var wire 1 1& SYNOPSYS_UNCONNECTED_37 $end
+$var wire 1 2& SYNOPSYS_UNCONNECTED_38 $end
+$var wire 1 3& SYNOPSYS_UNCONNECTED_39 $end
+$var wire 1 4& SYNOPSYS_UNCONNECTED_40 $end
+$var wire 1 5& SYNOPSYS_UNCONNECTED_41 $end
+$var wire 1 6& SYNOPSYS_UNCONNECTED_42 $end
+$var wire 1 7& SYNOPSYS_UNCONNECTED_43 $end
+$var wire 1 8& SYNOPSYS_UNCONNECTED_44 $end
+$var wire 1 9& SYNOPSYS_UNCONNECTED_45 $end
+$var wire 1 :& SYNOPSYS_UNCONNECTED_46 $end
+$var wire 1 ;& optlc_net_91 $end
+$var wire 1 <& SYNOPSYS_UNCONNECTED_47 $end
+$var wire 1 =& SYNOPSYS_UNCONNECTED_48 $end
+$var wire 1 >& SYNOPSYS_UNCONNECTED_49 $end
+$var wire 1 ?& SYNOPSYS_UNCONNECTED_50 $end
+$var wire 1 @& SYNOPSYS_UNCONNECTED_51 $end
+$var wire 1 A& SYNOPSYS_UNCONNECTED_52 $end
+$var wire 1 B& SYNOPSYS_UNCONNECTED_53 $end
+$var wire 1 C& SYNOPSYS_UNCONNECTED_54 $end
+$var wire 1 D& SYNOPSYS_UNCONNECTED_55 $end
+$var wire 1 E& SYNOPSYS_UNCONNECTED_56 $end
+$var wire 1 F& SYNOPSYS_UNCONNECTED_57 $end
+$var wire 1 G& SYNOPSYS_UNCONNECTED_58 $end
+$var wire 1 H& SYNOPSYS_UNCONNECTED_59 $end
+$var wire 1 I& SYNOPSYS_UNCONNECTED_60 $end
+$var wire 1 J& SYNOPSYS_UNCONNECTED_61 $end
+$var wire 1 K& SYNOPSYS_UNCONNECTED_62 $end
+$var wire 1 L& SYNOPSYS_UNCONNECTED_63 $end
+$var wire 1 M& SYNOPSYS_UNCONNECTED_64 $end
+$var wire 1 N& SYNOPSYS_UNCONNECTED_65 $end
+$var wire 1 O& SYNOPSYS_UNCONNECTED_66 $end
+$var wire 1 P& SYNOPSYS_UNCONNECTED_67 $end
+$var wire 1 Q& SYNOPSYS_UNCONNECTED_68 $end
+$var wire 1 R& SYNOPSYS_UNCONNECTED_69 $end
+$var wire 1 S& SYNOPSYS_UNCONNECTED_70 $end
+$var wire 1 T& SYNOPSYS_UNCONNECTED_71 $end
+$var wire 1 U& SYNOPSYS_UNCONNECTED_72 $end
+$var wire 1 V& ropt_net_111 $end
+$var wire 1 W& SYNOPSYS_UNCONNECTED_73 $end
+$var wire 1 X& SYNOPSYS_UNCONNECTED_74 $end
+$var wire 1 Y& SYNOPSYS_UNCONNECTED_75 $end
+$var wire 1 Z& SYNOPSYS_UNCONNECTED_76 $end
+$var wire 1 [& SYNOPSYS_UNCONNECTED_77 $end
+$var wire 1 \& SYNOPSYS_UNCONNECTED_78 $end
+$var wire 1 ]& SYNOPSYS_UNCONNECTED_79 $end
+$var wire 1 ^& SYNOPSYS_UNCONNECTED_80 $end
+$var wire 1 _& SYNOPSYS_UNCONNECTED_81 $end
+$var wire 1 `& SYNOPSYS_UNCONNECTED_82 $end
+$var wire 1 a& SYNOPSYS_UNCONNECTED_83 $end
+$var wire 1 b& ropt_net_112 $end
+$var wire 1 c& ropt_net_113 $end
 
 $scope module mux_bottom_track_1 $end
 $var wire 1 _# in [0] $end
@@ -666,14 +666,14 @@ $var wire 1 c# in [2] $end
 $var wire 1 e# in [3] $end
 $var wire 1 g# in [4] $end
 $var wire 1 i# in [5] $end
-$var wire 1 Y% sram [0] $end
-$var wire 1 Z% sram [1] $end
-$var wire 1 [% sram [2] $end
-$var wire 1 i% sram_inv [0] $end
-$var wire 1 j% sram_inv [1] $end
-$var wire 1 k% sram_inv [2] $end
+$var wire 1 W% sram [0] $end
+$var wire 1 X% sram [1] $end
+$var wire 1 Y% sram [2] $end
+$var wire 1 g% sram_inv [0] $end
+$var wire 1 h% sram_inv [1] $end
+$var wire 1 i% sram_inv [2] $end
 $var wire 1 ($ out [0] $end
-$var wire 1 l% p0 $end
+$var wire 1 j% p0 $end
 $var wire 1 d& sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 e& sky130_fd_sc_hd__mux2_1_1_X [0] $end
 $var wire 1 f& sky130_fd_sc_hd__mux2_1_2_X [0] $end
@@ -700,7 +700,7 @@ $scope module mux_l1_in_0_ $end
 $var wire 1 d& X $end
 $var wire 1 a# A0 $end
 $var wire 1 _# A1 $end
-$var wire 1 Y% S $end
+$var wire 1 W% S $end
 $var supply1 1 o& VPWR $end
 $var supply0 1 p& VGND $end
 $var supply1 1 q& VPB $end
@@ -710,7 +710,7 @@ $scope module base $end
 $var wire 1 d& X $end
 $var wire 1 a# A0 $end
 $var wire 1 _# A1 $end
-$var wire 1 Y% S $end
+$var wire 1 W% S $end
 $var wire 1 s& mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -719,7 +719,7 @@ $scope module mux_l1_in_1_ $end
 $var wire 1 e& X $end
 $var wire 1 e# A0 $end
 $var wire 1 c# A1 $end
-$var wire 1 Y% S $end
+$var wire 1 W% S $end
 $var supply1 1 t& VPWR $end
 $var supply0 1 u& VGND $end
 $var supply1 1 v& VPB $end
@@ -729,7 +729,7 @@ $scope module base $end
 $var wire 1 e& X $end
 $var wire 1 e# A0 $end
 $var wire 1 c# A1 $end
-$var wire 1 Y% S $end
+$var wire 1 W% S $end
 $var wire 1 x& mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -738,7 +738,7 @@ $scope module mux_l1_in_2_ $end
 $var wire 1 f& X $end
 $var wire 1 i# A0 $end
 $var wire 1 g# A1 $end
-$var wire 1 Y% S $end
+$var wire 1 W% S $end
 $var supply1 1 y& VPWR $end
 $var supply0 1 z& VGND $end
 $var supply1 1 {& VPB $end
@@ -748,7 +748,7 @@ $scope module base $end
 $var wire 1 f& X $end
 $var wire 1 i# A0 $end
 $var wire 1 g# A1 $end
-$var wire 1 Y% S $end
+$var wire 1 W% S $end
 $var wire 1 }& mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -757,7 +757,7 @@ $scope module mux_l2_in_0_ $end
 $var wire 1 g& X $end
 $var wire 1 e& A0 $end
 $var wire 1 d& A1 $end
-$var wire 1 Z% S $end
+$var wire 1 X% S $end
 $var supply1 1 ~& VPWR $end
 $var supply0 1 !' VGND $end
 $var supply1 1 "' VPB $end
@@ -767,16 +767,16 @@ $scope module base $end
 $var wire 1 g& X $end
 $var wire 1 e& A0 $end
 $var wire 1 d& A1 $end
-$var wire 1 Z% S $end
+$var wire 1 X% S $end
 $var wire 1 $' mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_1_ $end
 $var wire 1 h& X $end
-$var wire 1 l% A0 $end
+$var wire 1 j% A0 $end
 $var wire 1 f& A1 $end
-$var wire 1 Z% S $end
+$var wire 1 X% S $end
 $var supply1 1 %' VPWR $end
 $var supply0 1 &' VGND $end
 $var supply1 1 '' VPB $end
@@ -784,9 +784,9 @@ $var supply0 1 (' VNB $end
 
 $scope module base $end
 $var wire 1 h& X $end
-$var wire 1 l% A0 $end
+$var wire 1 j% A0 $end
 $var wire 1 f& A1 $end
-$var wire 1 Z% S $end
+$var wire 1 X% S $end
 $var wire 1 )' mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -795,7 +795,7 @@ $scope module mux_l3_in_0_ $end
 $var wire 1 i& X $end
 $var wire 1 h& A0 $end
 $var wire 1 g& A1 $end
-$var wire 1 [% S $end
+$var wire 1 Y% S $end
 $var supply1 1 *' VPWR $end
 $var supply0 1 +' VGND $end
 $var supply1 1 ,' VPB $end
@@ -805,7 +805,7 @@ $scope module base $end
 $var wire 1 i& X $end
 $var wire 1 h& A0 $end
 $var wire 1 g& A1 $end
-$var wire 1 [% S $end
+$var wire 1 Y% S $end
 $var wire 1 .' mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -818,27 +818,27 @@ $var wire 1 c# in [2] $end
 $var wire 1 e# in [3] $end
 $var wire 1 g# in [4] $end
 $var wire 1 k# in [5] $end
-$var wire 1 \% sram [0] $end
-$var wire 1 ]% sram [1] $end
-$var wire 1 ^% sram [2] $end
-$var wire 1 m% sram_inv [0] $end
-$var wire 1 n% sram_inv [1] $end
-$var wire 1 o% sram_inv [2] $end
+$var wire 1 Z% sram [0] $end
+$var wire 1 [% sram [1] $end
+$var wire 1 \% sram [2] $end
+$var wire 1 k% sram_inv [0] $end
+$var wire 1 l% sram_inv [1] $end
+$var wire 1 m% sram_inv [2] $end
 $var wire 1 *$ out [0] $end
-$var wire 1 l% p0 $end
+$var wire 1 n% p0 $end
 $var wire 1 /' sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 0' sky130_fd_sc_hd__mux2_1_1_X [0] $end
 $var wire 1 1' sky130_fd_sc_hd__mux2_1_2_X [0] $end
 $var wire 1 2' sky130_fd_sc_hd__mux2_1_3_X [0] $end
 $var wire 1 3' sky130_fd_sc_hd__mux2_1_4_X [0] $end
 $var wire 1 4' sky130_fd_sc_hd__mux2_1_5_X [0] $end
-$var wire 1 5' BUF_net_43 $end
+$var wire 1 5' BUF_net_42 $end
 
 $scope module mux_l1_in_0_ $end
 $var wire 1 /' X $end
 $var wire 1 a# A0 $end
 $var wire 1 _# A1 $end
-$var wire 1 \% S $end
+$var wire 1 Z% S $end
 $var supply1 1 6' VPWR $end
 $var supply0 1 7' VGND $end
 $var supply1 1 8' VPB $end
@@ -848,7 +848,7 @@ $scope module base $end
 $var wire 1 /' X $end
 $var wire 1 a# A0 $end
 $var wire 1 _# A1 $end
-$var wire 1 \% S $end
+$var wire 1 Z% S $end
 $var wire 1 :' mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -857,7 +857,7 @@ $scope module mux_l1_in_1_ $end
 $var wire 1 0' X $end
 $var wire 1 e# A0 $end
 $var wire 1 c# A1 $end
-$var wire 1 \% S $end
+$var wire 1 Z% S $end
 $var supply1 1 ;' VPWR $end
 $var supply0 1 <' VGND $end
 $var supply1 1 =' VPB $end
@@ -867,7 +867,7 @@ $scope module base $end
 $var wire 1 0' X $end
 $var wire 1 e# A0 $end
 $var wire 1 c# A1 $end
-$var wire 1 \% S $end
+$var wire 1 Z% S $end
 $var wire 1 ?' mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -876,7 +876,7 @@ $scope module mux_l1_in_2_ $end
 $var wire 1 1' X $end
 $var wire 1 k# A0 $end
 $var wire 1 g# A1 $end
-$var wire 1 \% S $end
+$var wire 1 Z% S $end
 $var supply1 1 @' VPWR $end
 $var supply0 1 A' VGND $end
 $var supply1 1 B' VPB $end
@@ -886,7 +886,7 @@ $scope module base $end
 $var wire 1 1' X $end
 $var wire 1 k# A0 $end
 $var wire 1 g# A1 $end
-$var wire 1 \% S $end
+$var wire 1 Z% S $end
 $var wire 1 D' mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -895,7 +895,7 @@ $scope module mux_l2_in_0_ $end
 $var wire 1 2' X $end
 $var wire 1 0' A0 $end
 $var wire 1 /' A1 $end
-$var wire 1 ]% S $end
+$var wire 1 [% S $end
 $var supply1 1 E' VPWR $end
 $var supply0 1 F' VGND $end
 $var supply1 1 G' VPB $end
@@ -905,16 +905,16 @@ $scope module base $end
 $var wire 1 2' X $end
 $var wire 1 0' A0 $end
 $var wire 1 /' A1 $end
-$var wire 1 ]% S $end
+$var wire 1 [% S $end
 $var wire 1 I' mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_1_ $end
 $var wire 1 3' X $end
-$var wire 1 l% A0 $end
+$var wire 1 n% A0 $end
 $var wire 1 1' A1 $end
-$var wire 1 ]% S $end
+$var wire 1 [% S $end
 $var supply1 1 J' VPWR $end
 $var supply0 1 K' VGND $end
 $var supply1 1 L' VPB $end
@@ -922,9 +922,9 @@ $var supply0 1 M' VNB $end
 
 $scope module base $end
 $var wire 1 3' X $end
-$var wire 1 l% A0 $end
+$var wire 1 n% A0 $end
 $var wire 1 1' A1 $end
-$var wire 1 ]% S $end
+$var wire 1 [% S $end
 $var wire 1 N' mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -933,7 +933,7 @@ $scope module mux_l3_in_0_ $end
 $var wire 1 4' X $end
 $var wire 1 3' A0 $end
 $var wire 1 2' A1 $end
-$var wire 1 ^% S $end
+$var wire 1 \% S $end
 $var supply1 1 O' VPWR $end
 $var supply0 1 P' VGND $end
 $var supply1 1 Q' VPB $end
@@ -943,12 +943,12 @@ $scope module base $end
 $var wire 1 4' X $end
 $var wire 1 3' A0 $end
 $var wire 1 2' A1 $end
-$var wire 1 ^% S $end
+$var wire 1 \% S $end
 $var wire 1 S' mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_42 $end
+$scope module BINV_R_41 $end
 $var wire 1 *$ Y $end
 $var wire 1 5' A $end
 $var supply1 1 T' VPWR $end
@@ -963,7 +963,7 @@ $var wire 1 X' not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_43 $end
+$scope module BINV_R_42 $end
 $var wire 1 5' Y $end
 $var wire 1 4' A $end
 $var supply1 1 Y' VPWR $end
@@ -986,27 +986,27 @@ $var wire 1 ~# in [2] $end
 $var wire 1 "$ in [3] $end
 $var wire 1 $$ in [4] $end
 $var wire 1 &$ in [5] $end
-$var wire 1 _% sram [0] $end
-$var wire 1 `% sram [1] $end
-$var wire 1 a% sram [2] $end
-$var wire 1 p% sram_inv [0] $end
-$var wire 1 q% sram_inv [1] $end
-$var wire 1 r% sram_inv [2] $end
+$var wire 1 ]% sram [0] $end
+$var wire 1 ^% sram [1] $end
+$var wire 1 _% sram [2] $end
+$var wire 1 o% sram_inv [0] $end
+$var wire 1 p% sram_inv [1] $end
+$var wire 1 q% sram_inv [2] $end
 $var wire 1 <$ out [0] $end
-$var wire 1 s% p0 $end
+$var wire 1 r% p0 $end
 $var wire 1 ^' sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 _' sky130_fd_sc_hd__mux2_1_1_X [0] $end
 $var wire 1 `' sky130_fd_sc_hd__mux2_1_2_X [0] $end
 $var wire 1 a' sky130_fd_sc_hd__mux2_1_3_X [0] $end
 $var wire 1 b' sky130_fd_sc_hd__mux2_1_4_X [0] $end
 $var wire 1 c' sky130_fd_sc_hd__mux2_1_5_X [0] $end
-$var wire 1 d' BUF_net_45 $end
+$var wire 1 d' BUF_net_44 $end
 
 $scope module mux_l1_in_0_ $end
 $var wire 1 ^' X $end
 $var wire 1 |# A0 $end
 $var wire 1 ^# A1 $end
-$var wire 1 _% S $end
+$var wire 1 ]% S $end
 $var supply1 1 e' VPWR $end
 $var supply0 1 f' VGND $end
 $var supply1 1 g' VPB $end
@@ -1016,7 +1016,7 @@ $scope module base $end
 $var wire 1 ^' X $end
 $var wire 1 |# A0 $end
 $var wire 1 ^# A1 $end
-$var wire 1 _% S $end
+$var wire 1 ]% S $end
 $var wire 1 i' mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -1025,7 +1025,7 @@ $scope module mux_l1_in_1_ $end
 $var wire 1 _' X $end
 $var wire 1 "$ A0 $end
 $var wire 1 ~# A1 $end
-$var wire 1 _% S $end
+$var wire 1 ]% S $end
 $var supply1 1 j' VPWR $end
 $var supply0 1 k' VGND $end
 $var supply1 1 l' VPB $end
@@ -1035,7 +1035,7 @@ $scope module base $end
 $var wire 1 _' X $end
 $var wire 1 "$ A0 $end
 $var wire 1 ~# A1 $end
-$var wire 1 _% S $end
+$var wire 1 ]% S $end
 $var wire 1 n' mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -1044,7 +1044,7 @@ $scope module mux_l1_in_2_ $end
 $var wire 1 `' X $end
 $var wire 1 &$ A0 $end
 $var wire 1 $$ A1 $end
-$var wire 1 _% S $end
+$var wire 1 ]% S $end
 $var supply1 1 o' VPWR $end
 $var supply0 1 p' VGND $end
 $var supply1 1 q' VPB $end
@@ -1054,7 +1054,7 @@ $scope module base $end
 $var wire 1 `' X $end
 $var wire 1 &$ A0 $end
 $var wire 1 $$ A1 $end
-$var wire 1 _% S $end
+$var wire 1 ]% S $end
 $var wire 1 s' mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -1063,7 +1063,7 @@ $scope module mux_l2_in_0_ $end
 $var wire 1 a' X $end
 $var wire 1 _' A0 $end
 $var wire 1 ^' A1 $end
-$var wire 1 `% S $end
+$var wire 1 ^% S $end
 $var supply1 1 t' VPWR $end
 $var supply0 1 u' VGND $end
 $var supply1 1 v' VPB $end
@@ -1073,16 +1073,16 @@ $scope module base $end
 $var wire 1 a' X $end
 $var wire 1 _' A0 $end
 $var wire 1 ^' A1 $end
-$var wire 1 `% S $end
+$var wire 1 ^% S $end
 $var wire 1 x' mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_1_ $end
 $var wire 1 b' X $end
-$var wire 1 s% A0 $end
+$var wire 1 r% A0 $end
 $var wire 1 `' A1 $end
-$var wire 1 `% S $end
+$var wire 1 ^% S $end
 $var supply1 1 y' VPWR $end
 $var supply0 1 z' VGND $end
 $var supply1 1 {' VPB $end
@@ -1090,9 +1090,9 @@ $var supply0 1 |' VNB $end
 
 $scope module base $end
 $var wire 1 b' X $end
-$var wire 1 s% A0 $end
+$var wire 1 r% A0 $end
 $var wire 1 `' A1 $end
-$var wire 1 `% S $end
+$var wire 1 ^% S $end
 $var wire 1 }' mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -1101,7 +1101,7 @@ $scope module mux_l3_in_0_ $end
 $var wire 1 c' X $end
 $var wire 1 b' A0 $end
 $var wire 1 a' A1 $end
-$var wire 1 a% S $end
+$var wire 1 _% S $end
 $var supply1 1 ~' VPWR $end
 $var supply0 1 !( VGND $end
 $var supply1 1 "( VPB $end
@@ -1111,12 +1111,12 @@ $scope module base $end
 $var wire 1 c' X $end
 $var wire 1 b' A0 $end
 $var wire 1 a' A1 $end
-$var wire 1 a% S $end
+$var wire 1 _% S $end
 $var wire 1 $( mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_44 $end
+$scope module BINV_R_43 $end
 $var wire 1 <$ Y $end
 $var wire 1 d' A $end
 $var supply1 1 %( VPWR $end
@@ -1131,7 +1131,7 @@ $var wire 1 )( not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_45 $end
+$scope module BINV_R_44 $end
 $var wire 1 d' Y $end
 $var wire 1 c' A $end
 $var supply1 1 *( VPWR $end
@@ -1154,27 +1154,27 @@ $var wire 1 ~# in [2] $end
 $var wire 1 "$ in [3] $end
 $var wire 1 $$ in [4] $end
 $var wire 1 &$ in [5] $end
-$var wire 1 b% sram [0] $end
-$var wire 1 c% sram [1] $end
-$var wire 1 d% sram [2] $end
-$var wire 1 t% sram_inv [0] $end
-$var wire 1 u% sram_inv [1] $end
-$var wire 1 v% sram_inv [2] $end
+$var wire 1 `% sram [0] $end
+$var wire 1 a% sram [1] $end
+$var wire 1 b% sram [2] $end
+$var wire 1 s% sram_inv [0] $end
+$var wire 1 t% sram_inv [1] $end
+$var wire 1 u% sram_inv [2] $end
 $var wire 1 >$ out [0] $end
-$var wire 1 s% p0 $end
+$var wire 1 r% p0 $end
 $var wire 1 /( sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 0( sky130_fd_sc_hd__mux2_1_1_X [0] $end
 $var wire 1 1( sky130_fd_sc_hd__mux2_1_2_X [0] $end
 $var wire 1 2( sky130_fd_sc_hd__mux2_1_3_X [0] $end
 $var wire 1 3( sky130_fd_sc_hd__mux2_1_4_X [0] $end
 $var wire 1 4( sky130_fd_sc_hd__mux2_1_5_X [0] $end
-$var wire 1 5( BUF_net_47 $end
+$var wire 1 5( BUF_net_46 $end
 
 $scope module mux_l1_in_0_ $end
 $var wire 1 /( X $end
 $var wire 1 |# A0 $end
 $var wire 1 L# A1 $end
-$var wire 1 b% S $end
+$var wire 1 `% S $end
 $var supply1 1 6( VPWR $end
 $var supply0 1 7( VGND $end
 $var supply1 1 8( VPB $end
@@ -1184,7 +1184,7 @@ $scope module base $end
 $var wire 1 /( X $end
 $var wire 1 |# A0 $end
 $var wire 1 L# A1 $end
-$var wire 1 b% S $end
+$var wire 1 `% S $end
 $var wire 1 :( mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -1193,7 +1193,7 @@ $scope module mux_l1_in_1_ $end
 $var wire 1 0( X $end
 $var wire 1 "$ A0 $end
 $var wire 1 ~# A1 $end
-$var wire 1 b% S $end
+$var wire 1 `% S $end
 $var supply1 1 ;( VPWR $end
 $var supply0 1 <( VGND $end
 $var supply1 1 =( VPB $end
@@ -1203,7 +1203,7 @@ $scope module base $end
 $var wire 1 0( X $end
 $var wire 1 "$ A0 $end
 $var wire 1 ~# A1 $end
-$var wire 1 b% S $end
+$var wire 1 `% S $end
 $var wire 1 ?( mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -1212,7 +1212,7 @@ $scope module mux_l1_in_2_ $end
 $var wire 1 1( X $end
 $var wire 1 &$ A0 $end
 $var wire 1 $$ A1 $end
-$var wire 1 b% S $end
+$var wire 1 `% S $end
 $var supply1 1 @( VPWR $end
 $var supply0 1 A( VGND $end
 $var supply1 1 B( VPB $end
@@ -1222,7 +1222,7 @@ $scope module base $end
 $var wire 1 1( X $end
 $var wire 1 &$ A0 $end
 $var wire 1 $$ A1 $end
-$var wire 1 b% S $end
+$var wire 1 `% S $end
 $var wire 1 D( mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -1231,7 +1231,7 @@ $scope module mux_l2_in_0_ $end
 $var wire 1 2( X $end
 $var wire 1 0( A0 $end
 $var wire 1 /( A1 $end
-$var wire 1 c% S $end
+$var wire 1 a% S $end
 $var supply1 1 E( VPWR $end
 $var supply0 1 F( VGND $end
 $var supply1 1 G( VPB $end
@@ -1241,16 +1241,16 @@ $scope module base $end
 $var wire 1 2( X $end
 $var wire 1 0( A0 $end
 $var wire 1 /( A1 $end
-$var wire 1 c% S $end
+$var wire 1 a% S $end
 $var wire 1 I( mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_1_ $end
 $var wire 1 3( X $end
-$var wire 1 s% A0 $end
+$var wire 1 r% A0 $end
 $var wire 1 1( A1 $end
-$var wire 1 c% S $end
+$var wire 1 a% S $end
 $var supply1 1 J( VPWR $end
 $var supply0 1 K( VGND $end
 $var supply1 1 L( VPB $end
@@ -1258,9 +1258,9 @@ $var supply0 1 M( VNB $end
 
 $scope module base $end
 $var wire 1 3( X $end
-$var wire 1 s% A0 $end
+$var wire 1 r% A0 $end
 $var wire 1 1( A1 $end
-$var wire 1 c% S $end
+$var wire 1 a% S $end
 $var wire 1 N( mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -1269,7 +1269,7 @@ $scope module mux_l3_in_0_ $end
 $var wire 1 4( X $end
 $var wire 1 3( A0 $end
 $var wire 1 2( A1 $end
-$var wire 1 d% S $end
+$var wire 1 b% S $end
 $var supply1 1 O( VPWR $end
 $var supply0 1 P( VGND $end
 $var supply1 1 Q( VPB $end
@@ -1279,12 +1279,12 @@ $scope module base $end
 $var wire 1 4( X $end
 $var wire 1 3( A0 $end
 $var wire 1 2( A1 $end
-$var wire 1 d% S $end
+$var wire 1 b% S $end
 $var wire 1 S( mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_46 $end
+$scope module BINV_R_45 $end
 $var wire 1 >$ Y $end
 $var wire 1 5( A $end
 $var supply1 1 T( VPWR $end
@@ -1299,7 +1299,7 @@ $var wire 1 X( not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_47 $end
+$scope module BINV_R_46 $end
 $var wire 1 5( Y $end
 $var wire 1 4( A $end
 $var supply1 1 Y( VPWR $end
@@ -1316,25 +1316,25 @@ $upscope $end
 $upscope $end
 
 $scope module mem_bottom_track_1 $end
-$var wire 1 U$ prog_clk [0] $end
+$var wire 1 S$ prog_clk [0] $end
 $var wire 1 '$ ccff_head [0] $end
-$var wire 1 e% ccff_tail [0] $end
-$var wire 1 Y% mem_out [0] $end
-$var wire 1 Z% mem_out [1] $end
-$var wire 1 [% mem_out [2] $end
-$var wire 1 ^( ropt_net_113 $end
-$var wire 1 _( copt_net_99 $end
-$var wire 1 `( copt_net_102 $end
-$var wire 1 a( copt_net_100 $end
-$var wire 1 b( copt_net_101 $end
-$var wire 1 c( copt_net_103 $end
-$var wire 1 d( copt_net_104 $end
-$var wire 1 e( ropt_net_111 $end
-$var wire 1 f( ropt_net_112 $end
+$var wire 1 c% ccff_tail [0] $end
+$var wire 1 W% mem_out [0] $end
+$var wire 1 X% mem_out [1] $end
+$var wire 1 Y% mem_out [2] $end
+$var wire 1 ^( ropt_net_110 $end
+$var wire 1 _( copt_net_96 $end
+$var wire 1 `( copt_net_97 $end
+$var wire 1 a( copt_net_98 $end
+$var wire 1 b( copt_net_99 $end
+$var wire 1 c( copt_net_100 $end
+$var wire 1 d( copt_net_101 $end
+$var wire 1 e( ropt_net_108 $end
+$var wire 1 f( ropt_net_109 $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 Y% Q $end
-$var wire 1 U$ CLK $end
+$var wire 1 W% Q $end
+$var wire 1 S$ CLK $end
 $var wire 1 ^( D $end
 $var supply1 1 g( VPWR $end
 $var supply0 1 h( VGND $end
@@ -1342,63 +1342,63 @@ $var supply1 1 i( VPB $end
 $var supply0 1 j( VNB $end
 
 $scope module base $end
-$var wire 1 Y% Q $end
-$var wire 1 U$ CLK $end
+$var wire 1 W% Q $end
+$var wire 1 S$ CLK $end
 $var wire 1 ^( D $end
 $var wire 1 k( buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 Z% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 Y% D $end
+$var wire 1 X% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 W% D $end
 $var supply1 1 l( VPWR $end
 $var supply0 1 m( VGND $end
 $var supply1 1 n( VPB $end
 $var supply0 1 o( VNB $end
 
 $scope module base $end
-$var wire 1 Z% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 Y% D $end
+$var wire 1 X% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 W% D $end
 $var wire 1 p( buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_2_ $end
-$var wire 1 [% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 Z% D $end
+$var wire 1 Y% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 X% D $end
 $var supply1 1 q( VPWR $end
 $var supply0 1 r( VGND $end
 $var supply1 1 s( VPB $end
 $var supply0 1 t( VNB $end
 
 $scope module base $end
-$var wire 1 [% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 Z% D $end
+$var wire 1 Y% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 X% D $end
 $var wire 1 u( buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_1__0 $end
-$var wire 1 e% X $end
-$var wire 1 [% A $end
+$var wire 1 c% X $end
+$var wire 1 Y% A $end
 $var supply1 1 v( VPWR $end
 $var supply0 1 w( VGND $end
 $var supply1 1 x( VPB $end
 $var supply0 1 y( VNB $end
 
 $scope module base $end
-$var wire 1 e% X $end
-$var wire 1 [% A $end
+$var wire 1 c% X $end
+$var wire 1 Y% A $end
 $var wire 1 z( buf0_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module copt_h_inst_1263 $end
+$scope module copt_h_inst_1262 $end
 $var wire 1 _( X $end
 $var wire 1 '$ A $end
 $var supply1 1 {( VPWR $end
@@ -1413,52 +1413,52 @@ $var wire 1 !) buf0_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module copt_h_inst_1264 $end
-$var wire 1 a( X $end
-$var wire 1 `( A $end
+$scope module copt_h_inst_1263 $end
+$var wire 1 `( X $end
+$var wire 1 _( A $end
 $var supply1 1 ") VPWR $end
 $var supply0 1 #) VGND $end
 $var supply1 1 $) VPB $end
 $var supply0 1 %) VNB $end
 
 $scope module base $end
-$var wire 1 a( X $end
-$var wire 1 `( A $end
+$var wire 1 `( X $end
+$var wire 1 _( A $end
 $var wire 1 &) buf0_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module copt_h_inst_1265 $end
-$var wire 1 b( X $end
-$var wire 1 a( A $end
+$scope module copt_h_inst_1264 $end
+$var wire 1 a( X $end
+$var wire 1 `( A $end
 $var supply1 1 ') VPWR $end
 $var supply0 1 () VGND $end
 $var supply1 1 )) VPB $end
 $var supply0 1 *) VNB $end
 
 $scope module base $end
-$var wire 1 b( X $end
-$var wire 1 a( A $end
+$var wire 1 a( X $end
+$var wire 1 `( A $end
 $var wire 1 +) buf0_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module copt_h_inst_1266 $end
-$var wire 1 `( X $end
-$var wire 1 _( A $end
+$scope module copt_h_inst_1265 $end
+$var wire 1 b( X $end
+$var wire 1 a( A $end
 $var supply1 1 ,) VPWR $end
 $var supply0 1 -) VGND $end
 $var supply1 1 .) VPB $end
 $var supply0 1 /) VNB $end
 
 $scope module base $end
-$var wire 1 `( X $end
-$var wire 1 _( A $end
+$var wire 1 b( X $end
+$var wire 1 a( A $end
 $var wire 1 0) buf0_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module copt_h_inst_1267 $end
+$scope module copt_h_inst_1266 $end
 $var wire 1 c( X $end
 $var wire 1 b( A $end
 $var supply1 1 1) VPWR $end
@@ -1473,7 +1473,7 @@ $var wire 1 5) buf0_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module copt_h_inst_1268 $end
+$scope module copt_h_inst_1267 $end
 $var wire 1 d( X $end
 $var wire 1 c( A $end
 $var supply1 1 6) VPWR $end
@@ -1488,7 +1488,7 @@ $var wire 1 :) buf0_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module ropt_h_inst_1275 $end
+$scope module ropt_h_inst_1274 $end
 $var wire 1 e( X $end
 $var wire 1 d( A $end
 $var supply1 1 ;) VPWR $end
@@ -1503,7 +1503,7 @@ $var wire 1 ?) buf0_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module ropt_h_inst_1276 $end
+$scope module ropt_h_inst_1275 $end
 $var wire 1 f( X $end
 $var wire 1 e( A $end
 $var supply1 1 @) VPWR $end
@@ -1518,7 +1518,7 @@ $var wire 1 D) buf0_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module ropt_h_inst_1277 $end
+$scope module ropt_h_inst_1276 $end
 $var wire 1 ^( X $end
 $var wire 1 f( A $end
 $var supply1 1 E) VPWR $end
@@ -1535,225 +1535,225 @@ $upscope $end
 $upscope $end
 
 $scope module mem_bottom_track_5 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 U% ccff_head [0] $end
-$var wire 1 f% ccff_tail [0] $end
-$var wire 1 \% mem_out [0] $end
-$var wire 1 ]% mem_out [1] $end
-$var wire 1 ^% mem_out [2] $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 S% ccff_head [0] $end
+$var wire 1 d% ccff_tail [0] $end
+$var wire 1 Z% mem_out [0] $end
+$var wire 1 [% mem_out [1] $end
+$var wire 1 \% mem_out [2] $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 \% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 U% D $end
+$var wire 1 Z% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 S% D $end
 $var supply1 1 J) VPWR $end
 $var supply0 1 K) VGND $end
 $var supply1 1 L) VPB $end
 $var supply0 1 M) VNB $end
 
 $scope module base $end
-$var wire 1 \% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 U% D $end
+$var wire 1 Z% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 S% D $end
 $var wire 1 N) buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 ]% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 \% D $end
+$var wire 1 [% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 Z% D $end
 $var supply1 1 O) VPWR $end
 $var supply0 1 P) VGND $end
 $var supply1 1 Q) VPB $end
 $var supply0 1 R) VNB $end
 
 $scope module base $end
-$var wire 1 ]% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 \% D $end
+$var wire 1 [% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 Z% D $end
 $var wire 1 S) buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_2_ $end
-$var wire 1 ^% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 ]% D $end
+$var wire 1 \% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 [% D $end
 $var supply1 1 T) VPWR $end
 $var supply0 1 U) VGND $end
 $var supply1 1 V) VPB $end
 $var supply0 1 W) VNB $end
 
 $scope module base $end
-$var wire 1 ^% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 ]% D $end
+$var wire 1 \% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 [% D $end
 $var wire 1 X) buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_2__1 $end
-$var wire 1 f% X $end
-$var wire 1 ^% A $end
+$var wire 1 d% X $end
+$var wire 1 \% A $end
 $var supply1 1 Y) VPWR $end
 $var supply0 1 Z) VGND $end
 $var supply1 1 [) VPB $end
 $var supply0 1 \) VNB $end
 
 $scope module base $end
-$var wire 1 f% X $end
-$var wire 1 ^% A $end
+$var wire 1 d% X $end
+$var wire 1 \% A $end
 $var wire 1 ]) buf0_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
 
 $scope module mem_left_track_1 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 ?% ccff_head [0] $end
-$var wire 1 g% ccff_tail [0] $end
-$var wire 1 _% mem_out [0] $end
-$var wire 1 `% mem_out [1] $end
-$var wire 1 a% mem_out [2] $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 =% ccff_head [0] $end
+$var wire 1 e% ccff_tail [0] $end
+$var wire 1 ]% mem_out [0] $end
+$var wire 1 ^% mem_out [1] $end
+$var wire 1 _% mem_out [2] $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 _% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 ?% D $end
+$var wire 1 ]% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 =% D $end
 $var supply1 1 ^) VPWR $end
 $var supply0 1 _) VGND $end
 $var supply1 1 `) VPB $end
 $var supply0 1 a) VNB $end
 
 $scope module base $end
-$var wire 1 _% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 ?% D $end
+$var wire 1 ]% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 =% D $end
 $var wire 1 b) buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 `% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 _% D $end
+$var wire 1 ^% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 ]% D $end
 $var supply1 1 c) VPWR $end
 $var supply0 1 d) VGND $end
 $var supply1 1 e) VPB $end
 $var supply0 1 f) VNB $end
 
 $scope module base $end
-$var wire 1 `% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 _% D $end
+$var wire 1 ^% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 ]% D $end
 $var wire 1 g) buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_2_ $end
-$var wire 1 a% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 `% D $end
+$var wire 1 _% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 ^% D $end
 $var supply1 1 h) VPWR $end
 $var supply0 1 i) VGND $end
 $var supply1 1 j) VPB $end
 $var supply0 1 k) VNB $end
 
 $scope module base $end
-$var wire 1 a% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 `% D $end
+$var wire 1 _% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 ^% D $end
 $var wire 1 l) buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_3__2 $end
-$var wire 1 g% X $end
-$var wire 1 a% A $end
+$var wire 1 e% X $end
+$var wire 1 _% A $end
 $var supply1 1 m) VPWR $end
 $var supply0 1 n) VGND $end
 $var supply1 1 o) VPB $end
 $var supply0 1 p) VNB $end
 
 $scope module base $end
-$var wire 1 g% X $end
-$var wire 1 a% A $end
+$var wire 1 e% X $end
+$var wire 1 _% A $end
 $var wire 1 q) buf0_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
 
 $scope module mem_left_track_5 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 W% ccff_head [0] $end
-$var wire 1 h% ccff_tail [0] $end
-$var wire 1 b% mem_out [0] $end
-$var wire 1 c% mem_out [1] $end
-$var wire 1 d% mem_out [2] $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 U% ccff_head [0] $end
+$var wire 1 f% ccff_tail [0] $end
+$var wire 1 `% mem_out [0] $end
+$var wire 1 a% mem_out [1] $end
+$var wire 1 b% mem_out [2] $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 b% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 W% D $end
+$var wire 1 `% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 U% D $end
 $var supply1 1 r) VPWR $end
 $var supply0 1 s) VGND $end
 $var supply1 1 t) VPB $end
 $var supply0 1 u) VNB $end
 
 $scope module base $end
-$var wire 1 b% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 W% D $end
+$var wire 1 `% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 U% D $end
 $var wire 1 v) buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 c% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 b% D $end
+$var wire 1 a% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 `% D $end
 $var supply1 1 w) VPWR $end
 $var supply0 1 x) VGND $end
 $var supply1 1 y) VPB $end
 $var supply0 1 z) VNB $end
 
 $scope module base $end
-$var wire 1 c% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 b% D $end
+$var wire 1 a% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 `% D $end
 $var wire 1 {) buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_2_ $end
-$var wire 1 d% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 c% D $end
+$var wire 1 b% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 a% D $end
 $var supply1 1 |) VPWR $end
 $var supply0 1 }) VGND $end
 $var supply1 1 ~) VPB $end
 $var supply0 1 !* VNB $end
 
 $scope module base $end
-$var wire 1 d% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 c% D $end
+$var wire 1 b% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 a% D $end
 $var wire 1 "* buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_4__3 $end
-$var wire 1 h% X $end
-$var wire 1 d% A $end
+$var wire 1 f% X $end
+$var wire 1 b% A $end
 $var supply1 1 #* VPWR $end
 $var supply0 1 $* VGND $end
 $var supply1 1 %* VPB $end
 $var supply0 1 &* VNB $end
 
 $scope module base $end
-$var wire 1 h% X $end
-$var wire 1 d% A $end
+$var wire 1 f% X $end
+$var wire 1 b% A $end
 $var wire 1 '* buf0_out_X $end
 $upscope $end
 $upscope $end
@@ -1765,26 +1765,26 @@ $var wire 1 b# in [1] $end
 $var wire 1 d# in [2] $end
 $var wire 1 f# in [3] $end
 $var wire 1 j# in [4] $end
-$var wire 1 I% sram [0] $end
-$var wire 1 J% sram [1] $end
-$var wire 1 K% sram [2] $end
-$var wire 1 w% sram_inv [0] $end
-$var wire 1 x% sram_inv [1] $end
-$var wire 1 y% sram_inv [2] $end
+$var wire 1 G% sram [0] $end
+$var wire 1 H% sram [1] $end
+$var wire 1 I% sram [2] $end
+$var wire 1 v% sram_inv [0] $end
+$var wire 1 w% sram_inv [1] $end
+$var wire 1 x% sram_inv [2] $end
 $var wire 1 )$ out [0] $end
-$var wire 1 l% p0 $end
+$var wire 1 n% p0 $end
 $var wire 1 (* sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 )* sky130_fd_sc_hd__mux2_1_1_X [0] $end
 $var wire 1 ** sky130_fd_sc_hd__mux2_1_2_X [0] $end
 $var wire 1 +* sky130_fd_sc_hd__mux2_1_3_X [0] $end
 $var wire 1 ,* sky130_fd_sc_hd__mux2_1_4_X [0] $end
-$var wire 1 -* BUF_net_49 $end
+$var wire 1 -* BUF_net_48 $end
 
 $scope module mux_l1_in_0_ $end
 $var wire 1 (* X $end
 $var wire 1 b# A0 $end
 $var wire 1 `# A1 $end
-$var wire 1 I% S $end
+$var wire 1 G% S $end
 $var supply1 1 .* VPWR $end
 $var supply0 1 /* VGND $end
 $var supply1 1 0* VPB $end
@@ -1794,7 +1794,7 @@ $scope module base $end
 $var wire 1 (* X $end
 $var wire 1 b# A0 $end
 $var wire 1 `# A1 $end
-$var wire 1 I% S $end
+$var wire 1 G% S $end
 $var wire 1 2* mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -1803,7 +1803,7 @@ $scope module mux_l1_in_1_ $end
 $var wire 1 )* X $end
 $var wire 1 f# A0 $end
 $var wire 1 d# A1 $end
-$var wire 1 I% S $end
+$var wire 1 G% S $end
 $var supply1 1 3* VPWR $end
 $var supply0 1 4* VGND $end
 $var supply1 1 5* VPB $end
@@ -1813,7 +1813,7 @@ $scope module base $end
 $var wire 1 )* X $end
 $var wire 1 f# A0 $end
 $var wire 1 d# A1 $end
-$var wire 1 I% S $end
+$var wire 1 G% S $end
 $var wire 1 7* mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -1822,7 +1822,7 @@ $scope module mux_l2_in_0_ $end
 $var wire 1 ** X $end
 $var wire 1 )* A0 $end
 $var wire 1 (* A1 $end
-$var wire 1 J% S $end
+$var wire 1 H% S $end
 $var supply1 1 8* VPWR $end
 $var supply0 1 9* VGND $end
 $var supply1 1 :* VPB $end
@@ -1832,16 +1832,16 @@ $scope module base $end
 $var wire 1 ** X $end
 $var wire 1 )* A0 $end
 $var wire 1 (* A1 $end
-$var wire 1 J% S $end
+$var wire 1 H% S $end
 $var wire 1 <* mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_1_ $end
 $var wire 1 +* X $end
-$var wire 1 l% A0 $end
+$var wire 1 n% A0 $end
 $var wire 1 j# A1 $end
-$var wire 1 J% S $end
+$var wire 1 H% S $end
 $var supply1 1 =* VPWR $end
 $var supply0 1 >* VGND $end
 $var supply1 1 ?* VPB $end
@@ -1849,9 +1849,9 @@ $var supply0 1 @* VNB $end
 
 $scope module base $end
 $var wire 1 +* X $end
-$var wire 1 l% A0 $end
+$var wire 1 n% A0 $end
 $var wire 1 j# A1 $end
-$var wire 1 J% S $end
+$var wire 1 H% S $end
 $var wire 1 A* mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -1860,7 +1860,7 @@ $scope module mux_l3_in_0_ $end
 $var wire 1 ,* X $end
 $var wire 1 +* A0 $end
 $var wire 1 ** A1 $end
-$var wire 1 K% S $end
+$var wire 1 I% S $end
 $var supply1 1 B* VPWR $end
 $var supply0 1 C* VGND $end
 $var supply1 1 D* VPB $end
@@ -1870,12 +1870,12 @@ $scope module base $end
 $var wire 1 ,* X $end
 $var wire 1 +* A0 $end
 $var wire 1 ** A1 $end
-$var wire 1 K% S $end
+$var wire 1 I% S $end
 $var wire 1 F* mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_48 $end
+$scope module BINV_R_47 $end
 $var wire 1 )$ Y $end
 $var wire 1 -* A $end
 $var supply1 1 G* VPWR $end
@@ -1890,7 +1890,7 @@ $var wire 1 K* not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_49 $end
+$scope module BINV_R_48 $end
 $var wire 1 -* Y $end
 $var wire 1 ,* A $end
 $var supply1 1 L* VPWR $end
@@ -1912,26 +1912,26 @@ $var wire 1 b# in [1] $end
 $var wire 1 d# in [2] $end
 $var wire 1 f# in [3] $end
 $var wire 1 l# in [4] $end
-$var wire 1 L% sram [0] $end
-$var wire 1 M% sram [1] $end
-$var wire 1 N% sram [2] $end
-$var wire 1 z% sram_inv [0] $end
-$var wire 1 {% sram_inv [1] $end
-$var wire 1 |% sram_inv [2] $end
+$var wire 1 J% sram [0] $end
+$var wire 1 K% sram [1] $end
+$var wire 1 L% sram [2] $end
+$var wire 1 y% sram_inv [0] $end
+$var wire 1 z% sram_inv [1] $end
+$var wire 1 {% sram_inv [2] $end
 $var wire 1 +$ out [0] $end
-$var wire 1 l% p0 $end
+$var wire 1 n% p0 $end
 $var wire 1 Q* sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 R* sky130_fd_sc_hd__mux2_1_1_X [0] $end
 $var wire 1 S* sky130_fd_sc_hd__mux2_1_2_X [0] $end
 $var wire 1 T* sky130_fd_sc_hd__mux2_1_3_X [0] $end
 $var wire 1 U* sky130_fd_sc_hd__mux2_1_4_X [0] $end
-$var wire 1 V* BUF_net_51 $end
+$var wire 1 V* BUF_net_50 $end
 
 $scope module mux_l1_in_0_ $end
 $var wire 1 Q* X $end
 $var wire 1 b# A0 $end
 $var wire 1 `# A1 $end
-$var wire 1 L% S $end
+$var wire 1 J% S $end
 $var supply1 1 W* VPWR $end
 $var supply0 1 X* VGND $end
 $var supply1 1 Y* VPB $end
@@ -1941,7 +1941,7 @@ $scope module base $end
 $var wire 1 Q* X $end
 $var wire 1 b# A0 $end
 $var wire 1 `# A1 $end
-$var wire 1 L% S $end
+$var wire 1 J% S $end
 $var wire 1 [* mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -1950,7 +1950,7 @@ $scope module mux_l1_in_1_ $end
 $var wire 1 R* X $end
 $var wire 1 f# A0 $end
 $var wire 1 d# A1 $end
-$var wire 1 L% S $end
+$var wire 1 J% S $end
 $var supply1 1 \* VPWR $end
 $var supply0 1 ]* VGND $end
 $var supply1 1 ^* VPB $end
@@ -1960,7 +1960,7 @@ $scope module base $end
 $var wire 1 R* X $end
 $var wire 1 f# A0 $end
 $var wire 1 d# A1 $end
-$var wire 1 L% S $end
+$var wire 1 J% S $end
 $var wire 1 `* mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -1969,7 +1969,7 @@ $scope module mux_l2_in_0_ $end
 $var wire 1 S* X $end
 $var wire 1 R* A0 $end
 $var wire 1 Q* A1 $end
-$var wire 1 M% S $end
+$var wire 1 K% S $end
 $var supply1 1 a* VPWR $end
 $var supply0 1 b* VGND $end
 $var supply1 1 c* VPB $end
@@ -1979,16 +1979,16 @@ $scope module base $end
 $var wire 1 S* X $end
 $var wire 1 R* A0 $end
 $var wire 1 Q* A1 $end
-$var wire 1 M% S $end
+$var wire 1 K% S $end
 $var wire 1 e* mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_1_ $end
 $var wire 1 T* X $end
-$var wire 1 l% A0 $end
+$var wire 1 n% A0 $end
 $var wire 1 l# A1 $end
-$var wire 1 M% S $end
+$var wire 1 K% S $end
 $var supply1 1 f* VPWR $end
 $var supply0 1 g* VGND $end
 $var supply1 1 h* VPB $end
@@ -1996,9 +1996,9 @@ $var supply0 1 i* VNB $end
 
 $scope module base $end
 $var wire 1 T* X $end
-$var wire 1 l% A0 $end
+$var wire 1 n% A0 $end
 $var wire 1 l# A1 $end
-$var wire 1 M% S $end
+$var wire 1 K% S $end
 $var wire 1 j* mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -2007,7 +2007,7 @@ $scope module mux_l3_in_0_ $end
 $var wire 1 U* X $end
 $var wire 1 T* A0 $end
 $var wire 1 S* A1 $end
-$var wire 1 N% S $end
+$var wire 1 L% S $end
 $var supply1 1 k* VPWR $end
 $var supply0 1 l* VGND $end
 $var supply1 1 m* VPB $end
@@ -2017,12 +2017,12 @@ $scope module base $end
 $var wire 1 U* X $end
 $var wire 1 T* A0 $end
 $var wire 1 S* A1 $end
-$var wire 1 N% S $end
+$var wire 1 L% S $end
 $var wire 1 o* mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_50 $end
+$scope module BINV_R_49 $end
 $var wire 1 +$ Y $end
 $var wire 1 V* A $end
 $var supply1 1 p* VPWR $end
@@ -2037,7 +2037,7 @@ $var wire 1 t* not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_51 $end
+$scope module BINV_R_50 $end
 $var wire 1 V* Y $end
 $var wire 1 U* A $end
 $var supply1 1 u* VPWR $end
@@ -2059,26 +2059,26 @@ $var wire 1 }# in [1] $end
 $var wire 1 !$ in [2] $end
 $var wire 1 #$ in [3] $end
 $var wire 1 %$ in [4] $end
-$var wire 1 O% sram [0] $end
-$var wire 1 P% sram [1] $end
-$var wire 1 Q% sram [2] $end
-$var wire 1 }% sram_inv [0] $end
-$var wire 1 ~% sram_inv [1] $end
-$var wire 1 !& sram_inv [2] $end
+$var wire 1 M% sram [0] $end
+$var wire 1 N% sram [1] $end
+$var wire 1 O% sram [2] $end
+$var wire 1 |% sram_inv [0] $end
+$var wire 1 }% sram_inv [1] $end
+$var wire 1 ~% sram_inv [2] $end
 $var wire 1 =$ out [0] $end
-$var wire 1 s% p0 $end
+$var wire 1 j% p0 $end
 $var wire 1 z* sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 {* sky130_fd_sc_hd__mux2_1_1_X [0] $end
 $var wire 1 |* sky130_fd_sc_hd__mux2_1_2_X [0] $end
 $var wire 1 }* sky130_fd_sc_hd__mux2_1_3_X [0] $end
 $var wire 1 ~* sky130_fd_sc_hd__mux2_1_4_X [0] $end
-$var wire 1 !+ BUF_net_53 $end
+$var wire 1 !+ BUF_net_52 $end
 
 $scope module mux_l1_in_0_ $end
 $var wire 1 z* X $end
 $var wire 1 }# A0 $end
 $var wire 1 K# A1 $end
-$var wire 1 O% S $end
+$var wire 1 M% S $end
 $var supply1 1 "+ VPWR $end
 $var supply0 1 #+ VGND $end
 $var supply1 1 $+ VPB $end
@@ -2088,7 +2088,7 @@ $scope module base $end
 $var wire 1 z* X $end
 $var wire 1 }# A0 $end
 $var wire 1 K# A1 $end
-$var wire 1 O% S $end
+$var wire 1 M% S $end
 $var wire 1 &+ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -2097,7 +2097,7 @@ $scope module mux_l1_in_1_ $end
 $var wire 1 {* X $end
 $var wire 1 #$ A0 $end
 $var wire 1 !$ A1 $end
-$var wire 1 O% S $end
+$var wire 1 M% S $end
 $var supply1 1 '+ VPWR $end
 $var supply0 1 (+ VGND $end
 $var supply1 1 )+ VPB $end
@@ -2107,7 +2107,7 @@ $scope module base $end
 $var wire 1 {* X $end
 $var wire 1 #$ A0 $end
 $var wire 1 !$ A1 $end
-$var wire 1 O% S $end
+$var wire 1 M% S $end
 $var wire 1 ++ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -2116,7 +2116,7 @@ $scope module mux_l2_in_0_ $end
 $var wire 1 |* X $end
 $var wire 1 {* A0 $end
 $var wire 1 z* A1 $end
-$var wire 1 P% S $end
+$var wire 1 N% S $end
 $var supply1 1 ,+ VPWR $end
 $var supply0 1 -+ VGND $end
 $var supply1 1 .+ VPB $end
@@ -2126,16 +2126,16 @@ $scope module base $end
 $var wire 1 |* X $end
 $var wire 1 {* A0 $end
 $var wire 1 z* A1 $end
-$var wire 1 P% S $end
+$var wire 1 N% S $end
 $var wire 1 0+ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_1_ $end
 $var wire 1 }* X $end
-$var wire 1 s% A0 $end
+$var wire 1 j% A0 $end
 $var wire 1 %$ A1 $end
-$var wire 1 P% S $end
+$var wire 1 N% S $end
 $var supply1 1 1+ VPWR $end
 $var supply0 1 2+ VGND $end
 $var supply1 1 3+ VPB $end
@@ -2143,9 +2143,9 @@ $var supply0 1 4+ VNB $end
 
 $scope module base $end
 $var wire 1 }* X $end
-$var wire 1 s% A0 $end
+$var wire 1 j% A0 $end
 $var wire 1 %$ A1 $end
-$var wire 1 P% S $end
+$var wire 1 N% S $end
 $var wire 1 5+ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -2154,7 +2154,7 @@ $scope module mux_l3_in_0_ $end
 $var wire 1 ~* X $end
 $var wire 1 }* A0 $end
 $var wire 1 |* A1 $end
-$var wire 1 Q% S $end
+$var wire 1 O% S $end
 $var supply1 1 6+ VPWR $end
 $var supply0 1 7+ VGND $end
 $var supply1 1 8+ VPB $end
@@ -2164,12 +2164,12 @@ $scope module base $end
 $var wire 1 ~* X $end
 $var wire 1 }* A0 $end
 $var wire 1 |* A1 $end
-$var wire 1 Q% S $end
+$var wire 1 O% S $end
 $var wire 1 :+ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_52 $end
+$scope module BINV_R_51 $end
 $var wire 1 =$ Y $end
 $var wire 1 !+ A $end
 $var supply1 1 ;+ VPWR $end
@@ -2184,7 +2184,7 @@ $var wire 1 ?+ not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_53 $end
+$scope module BINV_R_52 $end
 $var wire 1 !+ Y $end
 $var wire 1 ~* A $end
 $var supply1 1 @+ VPWR $end
@@ -2206,26 +2206,26 @@ $var wire 1 }# in [1] $end
 $var wire 1 !$ in [2] $end
 $var wire 1 #$ in [3] $end
 $var wire 1 %$ in [4] $end
-$var wire 1 R% sram [0] $end
-$var wire 1 S% sram [1] $end
-$var wire 1 T% sram [2] $end
-$var wire 1 "& sram_inv [0] $end
-$var wire 1 #& sram_inv [1] $end
-$var wire 1 $& sram_inv [2] $end
+$var wire 1 P% sram [0] $end
+$var wire 1 Q% sram [1] $end
+$var wire 1 R% sram [2] $end
+$var wire 1 !& sram_inv [0] $end
+$var wire 1 "& sram_inv [1] $end
+$var wire 1 #& sram_inv [2] $end
 $var wire 1 ?$ out [0] $end
-$var wire 1 s% p0 $end
+$var wire 1 j% p0 $end
 $var wire 1 E+ sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 F+ sky130_fd_sc_hd__mux2_1_1_X [0] $end
 $var wire 1 G+ sky130_fd_sc_hd__mux2_1_2_X [0] $end
 $var wire 1 H+ sky130_fd_sc_hd__mux2_1_3_X [0] $end
 $var wire 1 I+ sky130_fd_sc_hd__mux2_1_4_X [0] $end
-$var wire 1 J+ BUF_net_55 $end
+$var wire 1 J+ BUF_net_54 $end
 
 $scope module mux_l1_in_0_ $end
 $var wire 1 E+ X $end
 $var wire 1 }# A0 $end
 $var wire 1 M# A1 $end
-$var wire 1 R% S $end
+$var wire 1 P% S $end
 $var supply1 1 K+ VPWR $end
 $var supply0 1 L+ VGND $end
 $var supply1 1 M+ VPB $end
@@ -2235,7 +2235,7 @@ $scope module base $end
 $var wire 1 E+ X $end
 $var wire 1 }# A0 $end
 $var wire 1 M# A1 $end
-$var wire 1 R% S $end
+$var wire 1 P% S $end
 $var wire 1 O+ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -2244,7 +2244,7 @@ $scope module mux_l1_in_1_ $end
 $var wire 1 F+ X $end
 $var wire 1 #$ A0 $end
 $var wire 1 !$ A1 $end
-$var wire 1 R% S $end
+$var wire 1 P% S $end
 $var supply1 1 P+ VPWR $end
 $var supply0 1 Q+ VGND $end
 $var supply1 1 R+ VPB $end
@@ -2254,7 +2254,7 @@ $scope module base $end
 $var wire 1 F+ X $end
 $var wire 1 #$ A0 $end
 $var wire 1 !$ A1 $end
-$var wire 1 R% S $end
+$var wire 1 P% S $end
 $var wire 1 T+ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -2263,7 +2263,7 @@ $scope module mux_l2_in_0_ $end
 $var wire 1 G+ X $end
 $var wire 1 F+ A0 $end
 $var wire 1 E+ A1 $end
-$var wire 1 S% S $end
+$var wire 1 Q% S $end
 $var supply1 1 U+ VPWR $end
 $var supply0 1 V+ VGND $end
 $var supply1 1 W+ VPB $end
@@ -2273,16 +2273,16 @@ $scope module base $end
 $var wire 1 G+ X $end
 $var wire 1 F+ A0 $end
 $var wire 1 E+ A1 $end
-$var wire 1 S% S $end
+$var wire 1 Q% S $end
 $var wire 1 Y+ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_1_ $end
 $var wire 1 H+ X $end
-$var wire 1 s% A0 $end
+$var wire 1 j% A0 $end
 $var wire 1 %$ A1 $end
-$var wire 1 S% S $end
+$var wire 1 Q% S $end
 $var supply1 1 Z+ VPWR $end
 $var supply0 1 [+ VGND $end
 $var supply1 1 \+ VPB $end
@@ -2290,9 +2290,9 @@ $var supply0 1 ]+ VNB $end
 
 $scope module base $end
 $var wire 1 H+ X $end
-$var wire 1 s% A0 $end
+$var wire 1 j% A0 $end
 $var wire 1 %$ A1 $end
-$var wire 1 S% S $end
+$var wire 1 Q% S $end
 $var wire 1 ^+ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -2301,7 +2301,7 @@ $scope module mux_l3_in_0_ $end
 $var wire 1 I+ X $end
 $var wire 1 H+ A0 $end
 $var wire 1 G+ A1 $end
-$var wire 1 T% S $end
+$var wire 1 R% S $end
 $var supply1 1 _+ VPWR $end
 $var supply0 1 `+ VGND $end
 $var supply1 1 a+ VPB $end
@@ -2311,12 +2311,12 @@ $scope module base $end
 $var wire 1 I+ X $end
 $var wire 1 H+ A0 $end
 $var wire 1 G+ A1 $end
-$var wire 1 T% S $end
+$var wire 1 R% S $end
 $var wire 1 c+ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_54 $end
+$scope module BINV_R_53 $end
 $var wire 1 ?$ Y $end
 $var wire 1 J+ A $end
 $var supply1 1 d+ VPWR $end
@@ -2331,7 +2331,7 @@ $var wire 1 h+ not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_55 $end
+$scope module BINV_R_54 $end
 $var wire 1 J+ Y $end
 $var wire 1 I+ A $end
 $var supply1 1 i+ VPWR $end
@@ -2348,300 +2348,300 @@ $upscope $end
 $upscope $end
 
 $scope module mem_bottom_track_3 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 e% ccff_head [0] $end
-$var wire 1 U% ccff_tail [0] $end
-$var wire 1 I% mem_out [0] $end
-$var wire 1 J% mem_out [1] $end
-$var wire 1 K% mem_out [2] $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 c% ccff_head [0] $end
+$var wire 1 S% ccff_tail [0] $end
+$var wire 1 G% mem_out [0] $end
+$var wire 1 H% mem_out [1] $end
+$var wire 1 I% mem_out [2] $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 I% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 e% D $end
+$var wire 1 G% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 c% D $end
 $var supply1 1 n+ VPWR $end
 $var supply0 1 o+ VGND $end
 $var supply1 1 p+ VPB $end
 $var supply0 1 q+ VNB $end
 
 $scope module base $end
-$var wire 1 I% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 e% D $end
+$var wire 1 G% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 c% D $end
 $var wire 1 r+ buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 J% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 I% D $end
+$var wire 1 H% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 G% D $end
 $var supply1 1 s+ VPWR $end
 $var supply0 1 t+ VGND $end
 $var supply1 1 u+ VPB $end
 $var supply0 1 v+ VNB $end
 
 $scope module base $end
-$var wire 1 J% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 I% D $end
+$var wire 1 H% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 G% D $end
 $var wire 1 w+ buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_2_ $end
-$var wire 1 K% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 J% D $end
+$var wire 1 I% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 H% D $end
 $var supply1 1 x+ VPWR $end
 $var supply0 1 y+ VGND $end
 $var supply1 1 z+ VPB $end
 $var supply0 1 {+ VNB $end
 
 $scope module base $end
-$var wire 1 K% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 J% D $end
+$var wire 1 I% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 H% D $end
 $var wire 1 |+ buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_5__4 $end
-$var wire 1 U% X $end
-$var wire 1 K% A $end
+$var wire 1 S% X $end
+$var wire 1 I% A $end
 $var supply1 1 }+ VPWR $end
 $var supply0 1 ~+ VGND $end
 $var supply1 1 !, VPB $end
 $var supply0 1 ", VNB $end
 
 $scope module base $end
-$var wire 1 U% X $end
-$var wire 1 K% A $end
+$var wire 1 S% X $end
+$var wire 1 I% A $end
 $var wire 1 #, buf0_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
 
 $scope module mem_bottom_track_7 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 f% ccff_head [0] $end
-$var wire 1 V% ccff_tail [0] $end
-$var wire 1 L% mem_out [0] $end
-$var wire 1 M% mem_out [1] $end
-$var wire 1 N% mem_out [2] $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 d% ccff_head [0] $end
+$var wire 1 T% ccff_tail [0] $end
+$var wire 1 J% mem_out [0] $end
+$var wire 1 K% mem_out [1] $end
+$var wire 1 L% mem_out [2] $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 L% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 f% D $end
+$var wire 1 J% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 d% D $end
 $var supply1 1 $, VPWR $end
 $var supply0 1 %, VGND $end
 $var supply1 1 &, VPB $end
 $var supply0 1 ', VNB $end
 
 $scope module base $end
-$var wire 1 L% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 f% D $end
+$var wire 1 J% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 d% D $end
 $var wire 1 (, buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 M% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 L% D $end
+$var wire 1 K% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 J% D $end
 $var supply1 1 ), VPWR $end
 $var supply0 1 *, VGND $end
 $var supply1 1 +, VPB $end
 $var supply0 1 ,, VNB $end
 
 $scope module base $end
-$var wire 1 M% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 L% D $end
+$var wire 1 K% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 J% D $end
 $var wire 1 -, buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_2_ $end
-$var wire 1 N% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 M% D $end
+$var wire 1 L% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 K% D $end
 $var supply1 1 ., VPWR $end
 $var supply0 1 /, VGND $end
 $var supply1 1 0, VPB $end
 $var supply0 1 1, VNB $end
 
 $scope module base $end
-$var wire 1 N% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 M% D $end
+$var wire 1 L% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 K% D $end
 $var wire 1 2, buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_6__5 $end
-$var wire 1 V% X $end
-$var wire 1 N% A $end
+$var wire 1 T% X $end
+$var wire 1 L% A $end
 $var supply1 1 3, VPWR $end
 $var supply0 1 4, VGND $end
 $var supply1 1 5, VPB $end
 $var supply0 1 6, VNB $end
 
 $scope module base $end
-$var wire 1 V% X $end
-$var wire 1 N% A $end
+$var wire 1 T% X $end
+$var wire 1 L% A $end
 $var wire 1 7, buf0_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
 
 $scope module mem_left_track_3 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 g% ccff_head [0] $end
-$var wire 1 W% ccff_tail [0] $end
-$var wire 1 O% mem_out [0] $end
-$var wire 1 P% mem_out [1] $end
-$var wire 1 Q% mem_out [2] $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 e% ccff_head [0] $end
+$var wire 1 U% ccff_tail [0] $end
+$var wire 1 M% mem_out [0] $end
+$var wire 1 N% mem_out [1] $end
+$var wire 1 O% mem_out [2] $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 O% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 g% D $end
+$var wire 1 M% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 e% D $end
 $var supply1 1 8, VPWR $end
 $var supply0 1 9, VGND $end
 $var supply1 1 :, VPB $end
 $var supply0 1 ;, VNB $end
 
 $scope module base $end
-$var wire 1 O% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 g% D $end
+$var wire 1 M% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 e% D $end
 $var wire 1 <, buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 P% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 O% D $end
+$var wire 1 N% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 M% D $end
 $var supply1 1 =, VPWR $end
 $var supply0 1 >, VGND $end
 $var supply1 1 ?, VPB $end
 $var supply0 1 @, VNB $end
 
 $scope module base $end
-$var wire 1 P% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 O% D $end
+$var wire 1 N% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 M% D $end
 $var wire 1 A, buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_2_ $end
-$var wire 1 Q% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 P% D $end
+$var wire 1 O% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 N% D $end
 $var supply1 1 B, VPWR $end
 $var supply0 1 C, VGND $end
 $var supply1 1 D, VPB $end
 $var supply0 1 E, VNB $end
 
 $scope module base $end
-$var wire 1 Q% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 P% D $end
+$var wire 1 O% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 N% D $end
 $var wire 1 F, buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_7__6 $end
-$var wire 1 W% X $end
-$var wire 1 Q% A $end
+$var wire 1 U% X $end
+$var wire 1 O% A $end
 $var supply1 1 G, VPWR $end
 $var supply0 1 H, VGND $end
 $var supply1 1 I, VPB $end
 $var supply0 1 J, VNB $end
 
 $scope module base $end
-$var wire 1 W% X $end
-$var wire 1 Q% A $end
+$var wire 1 U% X $end
+$var wire 1 O% A $end
 $var wire 1 K, buf0_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
 
 $scope module mem_left_track_7 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 h% ccff_head [0] $end
-$var wire 1 X% ccff_tail [0] $end
-$var wire 1 R% mem_out [0] $end
-$var wire 1 S% mem_out [1] $end
-$var wire 1 T% mem_out [2] $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 f% ccff_head [0] $end
+$var wire 1 V% ccff_tail [0] $end
+$var wire 1 P% mem_out [0] $end
+$var wire 1 Q% mem_out [1] $end
+$var wire 1 R% mem_out [2] $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 R% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 h% D $end
+$var wire 1 P% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 f% D $end
 $var supply1 1 L, VPWR $end
 $var supply0 1 M, VGND $end
 $var supply1 1 N, VPB $end
 $var supply0 1 O, VNB $end
 
 $scope module base $end
-$var wire 1 R% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 h% D $end
+$var wire 1 P% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 f% D $end
 $var wire 1 P, buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 S% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 R% D $end
+$var wire 1 Q% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 P% D $end
 $var supply1 1 Q, VPWR $end
 $var supply0 1 R, VGND $end
 $var supply1 1 S, VPB $end
 $var supply0 1 T, VNB $end
 
 $scope module base $end
-$var wire 1 S% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 R% D $end
+$var wire 1 Q% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 P% D $end
 $var wire 1 U, buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_2_ $end
-$var wire 1 T% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 S% D $end
+$var wire 1 R% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 Q% D $end
 $var supply1 1 V, VPWR $end
 $var supply0 1 W, VGND $end
 $var supply1 1 X, VPB $end
 $var supply0 1 Y, VNB $end
 
 $scope module base $end
-$var wire 1 T% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 S% D $end
+$var wire 1 R% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 Q% D $end
 $var wire 1 Z, buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_8__7 $end
-$var wire 1 X% X $end
-$var wire 1 T% A $end
+$var wire 1 V% X $end
+$var wire 1 R% A $end
 $var supply1 1 [, VPWR $end
 $var supply0 1 \, VGND $end
 $var supply1 1 ], VPB $end
 $var supply0 1 ^, VNB $end
 
 $scope module base $end
-$var wire 1 X% X $end
-$var wire 1 T% A $end
+$var wire 1 V% X $end
+$var wire 1 R% A $end
 $var wire 1 _, buf0_out_X $end
 $upscope $end
 $upscope $end
@@ -2650,21 +2650,21 @@ $upscope $end
 $scope module mux_bottom_track_9 $end
 $var wire 1 _# in [0] $end
 $var wire 1 m# in [1] $end
-$var wire 1 W$ sram [0] $end
-$var wire 1 X$ sram [1] $end
-$var wire 1 %& sram_inv [0] $end
-$var wire 1 && sram_inv [1] $end
+$var wire 1 U$ sram [0] $end
+$var wire 1 V$ sram [1] $end
+$var wire 1 $& sram_inv [0] $end
+$var wire 1 %& sram_inv [1] $end
 $var wire 1 ,$ out [0] $end
-$var wire 1 '& p0 $end
+$var wire 1 j% p0 $end
 $var wire 1 `, sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 a, sky130_fd_sc_hd__mux2_1_1_X [0] $end
-$var wire 1 b, BUF_net_57 $end
+$var wire 1 b, BUF_net_56 $end
 
 $scope module mux_l1_in_0_ $end
 $var wire 1 `, X $end
 $var wire 1 m# A0 $end
 $var wire 1 _# A1 $end
-$var wire 1 W$ S $end
+$var wire 1 U$ S $end
 $var supply1 1 c, VPWR $end
 $var supply0 1 d, VGND $end
 $var supply1 1 e, VPB $end
@@ -2674,16 +2674,16 @@ $scope module base $end
 $var wire 1 `, X $end
 $var wire 1 m# A0 $end
 $var wire 1 _# A1 $end
-$var wire 1 W$ S $end
+$var wire 1 U$ S $end
 $var wire 1 g, mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
 $var wire 1 a, X $end
-$var wire 1 '& A0 $end
+$var wire 1 j% A0 $end
 $var wire 1 `, A1 $end
-$var wire 1 X$ S $end
+$var wire 1 V$ S $end
 $var supply1 1 h, VPWR $end
 $var supply0 1 i, VGND $end
 $var supply1 1 j, VPB $end
@@ -2691,14 +2691,14 @@ $var supply0 1 k, VNB $end
 
 $scope module base $end
 $var wire 1 a, X $end
-$var wire 1 '& A0 $end
+$var wire 1 j% A0 $end
 $var wire 1 `, A1 $end
-$var wire 1 X$ S $end
+$var wire 1 V$ S $end
 $var wire 1 l, mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_56 $end
+$scope module BINV_R_55 $end
 $var wire 1 ,$ Y $end
 $var wire 1 b, A $end
 $var supply1 1 m, VPWR $end
@@ -2713,7 +2713,7 @@ $var wire 1 q, not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_57 $end
+$scope module BINV_R_56 $end
 $var wire 1 b, Y $end
 $var wire 1 a, A $end
 $var supply1 1 r, VPWR $end
@@ -2732,81 +2732,65 @@ $upscope $end
 $scope module mux_bottom_track_11 $end
 $var wire 1 `# in [0] $end
 $var wire 1 n# in [1] $end
-$var wire 1 m$ sram [0] $end
-$var wire 1 n$ sram [1] $end
-$var wire 1 (& sram_inv [0] $end
-$var wire 1 )& sram_inv [1] $end
+$var wire 1 k$ sram [0] $end
+$var wire 1 l$ sram [1] $end
+$var wire 1 && sram_inv [0] $end
+$var wire 1 '& sram_inv [1] $end
 $var wire 1 -$ out [0] $end
-$var wire 1 '& p0 $end
+$var wire 1 j% p0 $end
 $var wire 1 w, sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 x, sky130_fd_sc_hd__mux2_1_1_X [0] $end
-$var wire 1 y, BUF_net_59 $end
 
 $scope module mux_l1_in_0_ $end
 $var wire 1 w, X $end
 $var wire 1 n# A0 $end
 $var wire 1 `# A1 $end
-$var wire 1 m$ S $end
-$var supply1 1 z, VPWR $end
-$var supply0 1 {, VGND $end
-$var supply1 1 |, VPB $end
-$var supply0 1 }, VNB $end
+$var wire 1 k$ S $end
+$var supply1 1 y, VPWR $end
+$var supply0 1 z, VGND $end
+$var supply1 1 {, VPB $end
+$var supply0 1 |, VNB $end
 
 $scope module base $end
 $var wire 1 w, X $end
 $var wire 1 n# A0 $end
 $var wire 1 `# A1 $end
-$var wire 1 m$ S $end
-$var wire 1 ~, mux_2to10_out_X $end
+$var wire 1 k$ S $end
+$var wire 1 }, mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
 $var wire 1 x, X $end
-$var wire 1 '& A0 $end
+$var wire 1 j% A0 $end
 $var wire 1 w, A1 $end
-$var wire 1 n$ S $end
-$var supply1 1 !- VPWR $end
-$var supply0 1 "- VGND $end
-$var supply1 1 #- VPB $end
-$var supply0 1 $- VNB $end
+$var wire 1 l$ S $end
+$var supply1 1 ~, VPWR $end
+$var supply0 1 !- VGND $end
+$var supply1 1 "- VPB $end
+$var supply0 1 #- VNB $end
 
 $scope module base $end
 $var wire 1 x, X $end
-$var wire 1 '& A0 $end
+$var wire 1 j% A0 $end
 $var wire 1 w, A1 $end
-$var wire 1 n$ S $end
-$var wire 1 %- mux_2to10_out_X $end
+$var wire 1 l$ S $end
+$var wire 1 $- mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_58 $end
-$var wire 1 -$ Y $end
-$var wire 1 y, A $end
-$var supply1 1 &- VPWR $end
-$var supply0 1 '- VGND $end
-$var supply1 1 (- VPB $end
-$var supply0 1 )- VNB $end
+$scope module BUFT_RR_57 $end
+$var wire 1 -$ X $end
+$var wire 1 x, A $end
+$var supply1 1 %- VPWR $end
+$var supply0 1 &- VGND $end
+$var supply1 1 '- VPB $end
+$var supply0 1 (- VNB $end
 
 $scope module base $end
-$var wire 1 -$ Y $end
-$var wire 1 y, A $end
-$var wire 1 *- not0_out_Y $end
-$upscope $end
-$upscope $end
-
-$scope module BINV_R_59 $end
-$var wire 1 y, Y $end
+$var wire 1 -$ X $end
 $var wire 1 x, A $end
-$var supply1 1 +- VPWR $end
-$var supply0 1 ,- VGND $end
-$var supply1 1 -- VPB $end
-$var supply0 1 .- VNB $end
-
-$scope module base $end
-$var wire 1 y, Y $end
-$var wire 1 x, A $end
-$var wire 1 /- not0_out_Y $end
+$var wire 1 )- buf0_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -2814,65 +2798,65 @@ $upscope $end
 $scope module mux_bottom_track_13 $end
 $var wire 1 a# in [0] $end
 $var wire 1 o# in [1] $end
-$var wire 1 w$ sram [0] $end
-$var wire 1 x$ sram [1] $end
-$var wire 1 *& sram_inv [0] $end
-$var wire 1 +& sram_inv [1] $end
+$var wire 1 u$ sram [0] $end
+$var wire 1 v$ sram [1] $end
+$var wire 1 (& sram_inv [0] $end
+$var wire 1 )& sram_inv [1] $end
 $var wire 1 .$ out [0] $end
-$var wire 1 s% p0 $end
-$var wire 1 0- sky130_fd_sc_hd__mux2_1_0_X [0] $end
-$var wire 1 1- sky130_fd_sc_hd__mux2_1_1_X [0] $end
+$var wire 1 j% p0 $end
+$var wire 1 *- sky130_fd_sc_hd__mux2_1_0_X [0] $end
+$var wire 1 +- sky130_fd_sc_hd__mux2_1_1_X [0] $end
 
 $scope module sky130_fd_sc_hd__buf_4_0_ $end
 $var wire 1 .$ X $end
-$var wire 1 1- A $end
-$var supply1 1 2- VPWR $end
-$var supply0 1 3- VGND $end
-$var supply1 1 4- VPB $end
-$var supply0 1 5- VNB $end
+$var wire 1 +- A $end
+$var supply1 1 ,- VPWR $end
+$var supply0 1 -- VGND $end
+$var supply1 1 .- VPB $end
+$var supply0 1 /- VNB $end
 
 $scope module base $end
 $var wire 1 .$ X $end
-$var wire 1 1- A $end
-$var wire 1 6- buf0_out_X $end
+$var wire 1 +- A $end
+$var wire 1 0- buf0_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l1_in_0_ $end
-$var wire 1 0- X $end
+$var wire 1 *- X $end
 $var wire 1 o# A0 $end
 $var wire 1 a# A1 $end
-$var wire 1 w$ S $end
-$var supply1 1 7- VPWR $end
-$var supply0 1 8- VGND $end
-$var supply1 1 9- VPB $end
-$var supply0 1 :- VNB $end
+$var wire 1 u$ S $end
+$var supply1 1 1- VPWR $end
+$var supply0 1 2- VGND $end
+$var supply1 1 3- VPB $end
+$var supply0 1 4- VNB $end
 
 $scope module base $end
-$var wire 1 0- X $end
+$var wire 1 *- X $end
 $var wire 1 o# A0 $end
 $var wire 1 a# A1 $end
-$var wire 1 w$ S $end
-$var wire 1 ;- mux_2to10_out_X $end
+$var wire 1 u$ S $end
+$var wire 1 5- mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
-$var wire 1 1- X $end
-$var wire 1 s% A0 $end
-$var wire 1 0- A1 $end
-$var wire 1 x$ S $end
-$var supply1 1 <- VPWR $end
-$var supply0 1 =- VGND $end
-$var supply1 1 >- VPB $end
-$var supply0 1 ?- VNB $end
+$var wire 1 +- X $end
+$var wire 1 j% A0 $end
+$var wire 1 *- A1 $end
+$var wire 1 v$ S $end
+$var supply1 1 6- VPWR $end
+$var supply0 1 7- VGND $end
+$var supply1 1 8- VPB $end
+$var supply0 1 9- VNB $end
 
 $scope module base $end
-$var wire 1 1- X $end
-$var wire 1 s% A0 $end
-$var wire 1 0- A1 $end
-$var wire 1 x$ S $end
-$var wire 1 @- mux_2to10_out_X $end
+$var wire 1 +- X $end
+$var wire 1 j% A0 $end
+$var wire 1 *- A1 $end
+$var wire 1 v$ S $end
+$var wire 1 :- mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -2880,81 +2864,81 @@ $upscope $end
 $scope module mux_bottom_track_15 $end
 $var wire 1 b# in [0] $end
 $var wire 1 p# in [1] $end
-$var wire 1 y$ sram [0] $end
-$var wire 1 z$ sram [1] $end
-$var wire 1 ,& sram_inv [0] $end
-$var wire 1 -& sram_inv [1] $end
+$var wire 1 w$ sram [0] $end
+$var wire 1 x$ sram [1] $end
+$var wire 1 *& sram_inv [0] $end
+$var wire 1 +& sram_inv [1] $end
 $var wire 1 /$ out [0] $end
-$var wire 1 '& p0 $end
-$var wire 1 A- sky130_fd_sc_hd__mux2_1_0_X [0] $end
-$var wire 1 B- sky130_fd_sc_hd__mux2_1_1_X [0] $end
-$var wire 1 C- BUF_net_61 $end
+$var wire 1 ,& p0 $end
+$var wire 1 ;- sky130_fd_sc_hd__mux2_1_0_X [0] $end
+$var wire 1 <- sky130_fd_sc_hd__mux2_1_1_X [0] $end
+$var wire 1 =- BUF_net_59 $end
 
 $scope module mux_l1_in_0_ $end
-$var wire 1 A- X $end
+$var wire 1 ;- X $end
 $var wire 1 p# A0 $end
 $var wire 1 b# A1 $end
-$var wire 1 y$ S $end
-$var supply1 1 D- VPWR $end
-$var supply0 1 E- VGND $end
-$var supply1 1 F- VPB $end
-$var supply0 1 G- VNB $end
+$var wire 1 w$ S $end
+$var supply1 1 >- VPWR $end
+$var supply0 1 ?- VGND $end
+$var supply1 1 @- VPB $end
+$var supply0 1 A- VNB $end
 
 $scope module base $end
-$var wire 1 A- X $end
+$var wire 1 ;- X $end
 $var wire 1 p# A0 $end
 $var wire 1 b# A1 $end
-$var wire 1 y$ S $end
-$var wire 1 H- mux_2to10_out_X $end
+$var wire 1 w$ S $end
+$var wire 1 B- mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
-$var wire 1 B- X $end
-$var wire 1 '& A0 $end
-$var wire 1 A- A1 $end
-$var wire 1 z$ S $end
-$var supply1 1 I- VPWR $end
-$var supply0 1 J- VGND $end
-$var supply1 1 K- VPB $end
-$var supply0 1 L- VNB $end
+$var wire 1 <- X $end
+$var wire 1 ,& A0 $end
+$var wire 1 ;- A1 $end
+$var wire 1 x$ S $end
+$var supply1 1 C- VPWR $end
+$var supply0 1 D- VGND $end
+$var supply1 1 E- VPB $end
+$var supply0 1 F- VNB $end
 
 $scope module base $end
-$var wire 1 B- X $end
-$var wire 1 '& A0 $end
-$var wire 1 A- A1 $end
-$var wire 1 z$ S $end
-$var wire 1 M- mux_2to10_out_X $end
+$var wire 1 <- X $end
+$var wire 1 ,& A0 $end
+$var wire 1 ;- A1 $end
+$var wire 1 x$ S $end
+$var wire 1 G- mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_60 $end
+$scope module BINV_R_58 $end
 $var wire 1 /$ Y $end
-$var wire 1 C- A $end
-$var supply1 1 N- VPWR $end
-$var supply0 1 O- VGND $end
-$var supply1 1 P- VPB $end
-$var supply0 1 Q- VNB $end
+$var wire 1 =- A $end
+$var supply1 1 H- VPWR $end
+$var supply0 1 I- VGND $end
+$var supply1 1 J- VPB $end
+$var supply0 1 K- VNB $end
 
 $scope module base $end
 $var wire 1 /$ Y $end
-$var wire 1 C- A $end
-$var wire 1 R- not0_out_Y $end
+$var wire 1 =- A $end
+$var wire 1 L- not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_61 $end
-$var wire 1 C- Y $end
-$var wire 1 B- A $end
-$var supply1 1 S- VPWR $end
-$var supply0 1 T- VGND $end
-$var supply1 1 U- VPB $end
-$var supply0 1 V- VNB $end
+$scope module BINV_R_59 $end
+$var wire 1 =- Y $end
+$var wire 1 <- A $end
+$var supply1 1 M- VPWR $end
+$var supply0 1 N- VGND $end
+$var supply1 1 O- VPB $end
+$var supply0 1 P- VNB $end
 
 $scope module base $end
-$var wire 1 C- Y $end
-$var wire 1 B- A $end
-$var wire 1 W- not0_out_Y $end
+$var wire 1 =- Y $end
+$var wire 1 <- A $end
+$var wire 1 Q- not0_out_Y $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -2962,81 +2946,81 @@ $upscope $end
 $scope module mux_bottom_track_17 $end
 $var wire 1 c# in [0] $end
 $var wire 1 q# in [1] $end
-$var wire 1 {$ sram [0] $end
-$var wire 1 |$ sram [1] $end
-$var wire 1 .& sram_inv [0] $end
-$var wire 1 /& sram_inv [1] $end
+$var wire 1 y$ sram [0] $end
+$var wire 1 z$ sram [1] $end
+$var wire 1 -& sram_inv [0] $end
+$var wire 1 .& sram_inv [1] $end
 $var wire 1 0$ out [0] $end
-$var wire 1 '& p0 $end
-$var wire 1 X- sky130_fd_sc_hd__mux2_1_0_X [0] $end
-$var wire 1 Y- sky130_fd_sc_hd__mux2_1_1_X [0] $end
-$var wire 1 Z- BUF_net_63 $end
+$var wire 1 ,& p0 $end
+$var wire 1 R- sky130_fd_sc_hd__mux2_1_0_X [0] $end
+$var wire 1 S- sky130_fd_sc_hd__mux2_1_1_X [0] $end
+$var wire 1 T- BUF_net_61 $end
 
 $scope module mux_l1_in_0_ $end
-$var wire 1 X- X $end
+$var wire 1 R- X $end
 $var wire 1 q# A0 $end
 $var wire 1 c# A1 $end
-$var wire 1 {$ S $end
-$var supply1 1 [- VPWR $end
-$var supply0 1 \- VGND $end
-$var supply1 1 ]- VPB $end
-$var supply0 1 ^- VNB $end
+$var wire 1 y$ S $end
+$var supply1 1 U- VPWR $end
+$var supply0 1 V- VGND $end
+$var supply1 1 W- VPB $end
+$var supply0 1 X- VNB $end
 
 $scope module base $end
-$var wire 1 X- X $end
+$var wire 1 R- X $end
 $var wire 1 q# A0 $end
 $var wire 1 c# A1 $end
-$var wire 1 {$ S $end
-$var wire 1 _- mux_2to10_out_X $end
+$var wire 1 y$ S $end
+$var wire 1 Y- mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
-$var wire 1 Y- X $end
-$var wire 1 '& A0 $end
-$var wire 1 X- A1 $end
-$var wire 1 |$ S $end
-$var supply1 1 `- VPWR $end
-$var supply0 1 a- VGND $end
-$var supply1 1 b- VPB $end
-$var supply0 1 c- VNB $end
+$var wire 1 S- X $end
+$var wire 1 ,& A0 $end
+$var wire 1 R- A1 $end
+$var wire 1 z$ S $end
+$var supply1 1 Z- VPWR $end
+$var supply0 1 [- VGND $end
+$var supply1 1 \- VPB $end
+$var supply0 1 ]- VNB $end
 
 $scope module base $end
-$var wire 1 Y- X $end
-$var wire 1 '& A0 $end
-$var wire 1 X- A1 $end
-$var wire 1 |$ S $end
-$var wire 1 d- mux_2to10_out_X $end
+$var wire 1 S- X $end
+$var wire 1 ,& A0 $end
+$var wire 1 R- A1 $end
+$var wire 1 z$ S $end
+$var wire 1 ^- mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_62 $end
+$scope module BINV_R_60 $end
 $var wire 1 0$ Y $end
-$var wire 1 Z- A $end
-$var supply1 1 e- VPWR $end
-$var supply0 1 f- VGND $end
-$var supply1 1 g- VPB $end
-$var supply0 1 h- VNB $end
+$var wire 1 T- A $end
+$var supply1 1 _- VPWR $end
+$var supply0 1 `- VGND $end
+$var supply1 1 a- VPB $end
+$var supply0 1 b- VNB $end
 
 $scope module base $end
 $var wire 1 0$ Y $end
-$var wire 1 Z- A $end
-$var wire 1 i- not0_out_Y $end
+$var wire 1 T- A $end
+$var wire 1 c- not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_63 $end
-$var wire 1 Z- Y $end
-$var wire 1 Y- A $end
-$var supply1 1 j- VPWR $end
-$var supply0 1 k- VGND $end
-$var supply1 1 l- VPB $end
-$var supply0 1 m- VNB $end
+$scope module BINV_R_61 $end
+$var wire 1 T- Y $end
+$var wire 1 S- A $end
+$var supply1 1 d- VPWR $end
+$var supply0 1 e- VGND $end
+$var supply1 1 f- VPB $end
+$var supply0 1 g- VNB $end
 
 $scope module base $end
-$var wire 1 Z- Y $end
-$var wire 1 Y- A $end
-$var wire 1 n- not0_out_Y $end
+$var wire 1 T- Y $end
+$var wire 1 S- A $end
+$var wire 1 h- not0_out_Y $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -3044,81 +3028,81 @@ $upscope $end
 $scope module mux_bottom_track_19 $end
 $var wire 1 d# in [0] $end
 $var wire 1 r# in [1] $end
-$var wire 1 }$ sram [0] $end
-$var wire 1 ~$ sram [1] $end
-$var wire 1 0& sram_inv [0] $end
-$var wire 1 1& sram_inv [1] $end
+$var wire 1 {$ sram [0] $end
+$var wire 1 |$ sram [1] $end
+$var wire 1 /& sram_inv [0] $end
+$var wire 1 0& sram_inv [1] $end
 $var wire 1 1$ out [0] $end
-$var wire 1 '& p0 $end
-$var wire 1 o- sky130_fd_sc_hd__mux2_1_0_X [0] $end
-$var wire 1 p- sky130_fd_sc_hd__mux2_1_1_X [0] $end
-$var wire 1 q- BUF_net_65 $end
+$var wire 1 ,& p0 $end
+$var wire 1 i- sky130_fd_sc_hd__mux2_1_0_X [0] $end
+$var wire 1 j- sky130_fd_sc_hd__mux2_1_1_X [0] $end
+$var wire 1 k- BUF_net_63 $end
 
 $scope module mux_l1_in_0_ $end
-$var wire 1 o- X $end
+$var wire 1 i- X $end
 $var wire 1 r# A0 $end
 $var wire 1 d# A1 $end
-$var wire 1 }$ S $end
-$var supply1 1 r- VPWR $end
-$var supply0 1 s- VGND $end
-$var supply1 1 t- VPB $end
-$var supply0 1 u- VNB $end
+$var wire 1 {$ S $end
+$var supply1 1 l- VPWR $end
+$var supply0 1 m- VGND $end
+$var supply1 1 n- VPB $end
+$var supply0 1 o- VNB $end
 
 $scope module base $end
-$var wire 1 o- X $end
+$var wire 1 i- X $end
 $var wire 1 r# A0 $end
 $var wire 1 d# A1 $end
-$var wire 1 }$ S $end
-$var wire 1 v- mux_2to10_out_X $end
+$var wire 1 {$ S $end
+$var wire 1 p- mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
-$var wire 1 p- X $end
-$var wire 1 '& A0 $end
-$var wire 1 o- A1 $end
-$var wire 1 ~$ S $end
-$var supply1 1 w- VPWR $end
-$var supply0 1 x- VGND $end
-$var supply1 1 y- VPB $end
-$var supply0 1 z- VNB $end
+$var wire 1 j- X $end
+$var wire 1 ,& A0 $end
+$var wire 1 i- A1 $end
+$var wire 1 |$ S $end
+$var supply1 1 q- VPWR $end
+$var supply0 1 r- VGND $end
+$var supply1 1 s- VPB $end
+$var supply0 1 t- VNB $end
 
 $scope module base $end
-$var wire 1 p- X $end
-$var wire 1 '& A0 $end
-$var wire 1 o- A1 $end
-$var wire 1 ~$ S $end
-$var wire 1 {- mux_2to10_out_X $end
+$var wire 1 j- X $end
+$var wire 1 ,& A0 $end
+$var wire 1 i- A1 $end
+$var wire 1 |$ S $end
+$var wire 1 u- mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_64 $end
+$scope module BINV_R_62 $end
 $var wire 1 1$ Y $end
-$var wire 1 q- A $end
-$var supply1 1 |- VPWR $end
-$var supply0 1 }- VGND $end
-$var supply1 1 ~- VPB $end
-$var supply0 1 !. VNB $end
+$var wire 1 k- A $end
+$var supply1 1 v- VPWR $end
+$var supply0 1 w- VGND $end
+$var supply1 1 x- VPB $end
+$var supply0 1 y- VNB $end
 
 $scope module base $end
 $var wire 1 1$ Y $end
-$var wire 1 q- A $end
-$var wire 1 ". not0_out_Y $end
+$var wire 1 k- A $end
+$var wire 1 z- not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_65 $end
-$var wire 1 q- Y $end
-$var wire 1 p- A $end
-$var supply1 1 #. VPWR $end
-$var supply0 1 $. VGND $end
-$var supply1 1 %. VPB $end
-$var supply0 1 &. VNB $end
+$scope module BINV_R_63 $end
+$var wire 1 k- Y $end
+$var wire 1 j- A $end
+$var supply1 1 {- VPWR $end
+$var supply0 1 |- VGND $end
+$var supply1 1 }- VPB $end
+$var supply0 1 ~- VNB $end
 
 $scope module base $end
-$var wire 1 q- Y $end
-$var wire 1 p- A $end
-$var wire 1 '. not0_out_Y $end
+$var wire 1 k- Y $end
+$var wire 1 j- A $end
+$var wire 1 !. not0_out_Y $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -3126,65 +3110,81 @@ $upscope $end
 $scope module mux_bottom_track_21 $end
 $var wire 1 e# in [0] $end
 $var wire 1 s# in [1] $end
-$var wire 1 !% sram [0] $end
-$var wire 1 "% sram [1] $end
-$var wire 1 2& sram_inv [0] $end
-$var wire 1 3& sram_inv [1] $end
+$var wire 1 }$ sram [0] $end
+$var wire 1 ~$ sram [1] $end
+$var wire 1 1& sram_inv [0] $end
+$var wire 1 2& sram_inv [1] $end
 $var wire 1 2$ out [0] $end
-$var wire 1 '& p0 $end
-$var wire 1 (. sky130_fd_sc_hd__mux2_1_0_X [0] $end
-$var wire 1 ). sky130_fd_sc_hd__mux2_1_1_X [0] $end
+$var wire 1 ,& p0 $end
+$var wire 1 ". sky130_fd_sc_hd__mux2_1_0_X [0] $end
+$var wire 1 #. sky130_fd_sc_hd__mux2_1_1_X [0] $end
+$var wire 1 $. BUF_net_65 $end
 
-$scope module sky130_fd_sc_hd__buf_4_0_ $end
-$var wire 1 2$ X $end
-$var wire 1 ). A $end
+$scope module mux_l1_in_0_ $end
+$var wire 1 ". X $end
+$var wire 1 s# A0 $end
+$var wire 1 e# A1 $end
+$var wire 1 }$ S $end
+$var supply1 1 %. VPWR $end
+$var supply0 1 &. VGND $end
+$var supply1 1 '. VPB $end
+$var supply0 1 (. VNB $end
+
+$scope module base $end
+$var wire 1 ". X $end
+$var wire 1 s# A0 $end
+$var wire 1 e# A1 $end
+$var wire 1 }$ S $end
+$var wire 1 ). mux_2to10_out_X $end
+$upscope $end
+$upscope $end
+
+$scope module mux_l2_in_0_ $end
+$var wire 1 #. X $end
+$var wire 1 ,& A0 $end
+$var wire 1 ". A1 $end
+$var wire 1 ~$ S $end
 $var supply1 1 *. VPWR $end
 $var supply0 1 +. VGND $end
 $var supply1 1 ,. VPB $end
 $var supply0 1 -. VNB $end
 
 $scope module base $end
-$var wire 1 2$ X $end
-$var wire 1 ). A $end
-$var wire 1 .. buf0_out_X $end
+$var wire 1 #. X $end
+$var wire 1 ,& A0 $end
+$var wire 1 ". A1 $end
+$var wire 1 ~$ S $end
+$var wire 1 .. mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module mux_l1_in_0_ $end
-$var wire 1 (. X $end
-$var wire 1 s# A0 $end
-$var wire 1 e# A1 $end
-$var wire 1 !% S $end
+$scope module BINV_R_64 $end
+$var wire 1 2$ Y $end
+$var wire 1 $. A $end
 $var supply1 1 /. VPWR $end
 $var supply0 1 0. VGND $end
 $var supply1 1 1. VPB $end
 $var supply0 1 2. VNB $end
 
 $scope module base $end
-$var wire 1 (. X $end
-$var wire 1 s# A0 $end
-$var wire 1 e# A1 $end
-$var wire 1 !% S $end
-$var wire 1 3. mux_2to10_out_X $end
+$var wire 1 2$ Y $end
+$var wire 1 $. A $end
+$var wire 1 3. not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module mux_l2_in_0_ $end
-$var wire 1 ). X $end
-$var wire 1 '& A0 $end
-$var wire 1 (. A1 $end
-$var wire 1 "% S $end
+$scope module BINV_R_65 $end
+$var wire 1 $. Y $end
+$var wire 1 #. A $end
 $var supply1 1 4. VPWR $end
 $var supply0 1 5. VGND $end
 $var supply1 1 6. VPB $end
 $var supply0 1 7. VNB $end
 
 $scope module base $end
-$var wire 1 ). X $end
-$var wire 1 '& A0 $end
-$var wire 1 (. A1 $end
-$var wire 1 "% S $end
-$var wire 1 8. mux_2to10_out_X $end
+$var wire 1 $. Y $end
+$var wire 1 #. A $end
+$var wire 1 8. not0_out_Y $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -3192,12 +3192,12 @@ $upscope $end
 $scope module mux_bottom_track_23 $end
 $var wire 1 f# in [0] $end
 $var wire 1 t# in [1] $end
-$var wire 1 #% sram [0] $end
-$var wire 1 $% sram [1] $end
-$var wire 1 4& sram_inv [0] $end
-$var wire 1 5& sram_inv [1] $end
+$var wire 1 !% sram [0] $end
+$var wire 1 "% sram [1] $end
+$var wire 1 3& sram_inv [0] $end
+$var wire 1 4& sram_inv [1] $end
 $var wire 1 3$ out [0] $end
-$var wire 1 '& p0 $end
+$var wire 1 ,& p0 $end
 $var wire 1 9. sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 :. sky130_fd_sc_hd__mux2_1_1_X [0] $end
 
@@ -3205,7 +3205,7 @@ $scope module mux_l1_in_0_ $end
 $var wire 1 9. X $end
 $var wire 1 t# A0 $end
 $var wire 1 f# A1 $end
-$var wire 1 #% S $end
+$var wire 1 !% S $end
 $var supply1 1 ;. VPWR $end
 $var supply0 1 <. VGND $end
 $var supply1 1 =. VPB $end
@@ -3215,16 +3215,16 @@ $scope module base $end
 $var wire 1 9. X $end
 $var wire 1 t# A0 $end
 $var wire 1 f# A1 $end
-$var wire 1 #% S $end
+$var wire 1 !% S $end
 $var wire 1 ?. mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
 $var wire 1 :. X $end
-$var wire 1 '& A0 $end
+$var wire 1 ,& A0 $end
 $var wire 1 9. A1 $end
-$var wire 1 $% S $end
+$var wire 1 "% S $end
 $var supply1 1 @. VPWR $end
 $var supply0 1 A. VGND $end
 $var supply1 1 B. VPB $end
@@ -3232,9 +3232,9 @@ $var supply0 1 C. VNB $end
 
 $scope module base $end
 $var wire 1 :. X $end
-$var wire 1 '& A0 $end
+$var wire 1 ,& A0 $end
 $var wire 1 9. A1 $end
-$var wire 1 $% S $end
+$var wire 1 "% S $end
 $var wire 1 D. mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -3258,12 +3258,12 @@ $upscope $end
 $scope module mux_bottom_track_27 $end
 $var wire 1 `# in [0] $end
 $var wire 1 v# in [1] $end
-$var wire 1 %% sram [0] $end
-$var wire 1 &% sram [1] $end
-$var wire 1 6& sram_inv [0] $end
-$var wire 1 7& sram_inv [1] $end
+$var wire 1 #% sram [0] $end
+$var wire 1 $% sram [1] $end
+$var wire 1 5& sram_inv [0] $end
+$var wire 1 6& sram_inv [1] $end
 $var wire 1 5$ out [0] $end
-$var wire 1 s% p0 $end
+$var wire 1 j% p0 $end
 $var wire 1 J. sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 K. sky130_fd_sc_hd__mux2_1_1_X [0] $end
 $var wire 1 L. BUF_net_68 $end
@@ -3272,7 +3272,7 @@ $scope module mux_l1_in_0_ $end
 $var wire 1 J. X $end
 $var wire 1 v# A0 $end
 $var wire 1 `# A1 $end
-$var wire 1 %% S $end
+$var wire 1 #% S $end
 $var supply1 1 M. VPWR $end
 $var supply0 1 N. VGND $end
 $var supply1 1 O. VPB $end
@@ -3282,16 +3282,16 @@ $scope module base $end
 $var wire 1 J. X $end
 $var wire 1 v# A0 $end
 $var wire 1 `# A1 $end
-$var wire 1 %% S $end
+$var wire 1 #% S $end
 $var wire 1 Q. mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
 $var wire 1 K. X $end
-$var wire 1 s% A0 $end
+$var wire 1 j% A0 $end
 $var wire 1 J. A1 $end
-$var wire 1 &% S $end
+$var wire 1 $% S $end
 $var supply1 1 R. VPWR $end
 $var supply0 1 S. VGND $end
 $var supply1 1 T. VPB $end
@@ -3299,9 +3299,9 @@ $var supply0 1 U. VNB $end
 
 $scope module base $end
 $var wire 1 K. X $end
-$var wire 1 s% A0 $end
+$var wire 1 j% A0 $end
 $var wire 1 J. A1 $end
-$var wire 1 &% S $end
+$var wire 1 $% S $end
 $var wire 1 V. mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -3340,12 +3340,12 @@ $upscope $end
 $scope module mux_bottom_track_29 $end
 $var wire 1 a# in [0] $end
 $var wire 1 w# in [1] $end
-$var wire 1 '% sram [0] $end
-$var wire 1 (% sram [1] $end
-$var wire 1 8& sram_inv [0] $end
-$var wire 1 9& sram_inv [1] $end
+$var wire 1 %% sram [0] $end
+$var wire 1 &% sram [1] $end
+$var wire 1 7& sram_inv [0] $end
+$var wire 1 8& sram_inv [1] $end
 $var wire 1 6$ out [0] $end
-$var wire 1 s% p0 $end
+$var wire 1 r% p0 $end
 $var wire 1 a. sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 b. sky130_fd_sc_hd__mux2_1_1_X [0] $end
 $var wire 1 c. BUF_net_70 $end
@@ -3354,7 +3354,7 @@ $scope module mux_l1_in_0_ $end
 $var wire 1 a. X $end
 $var wire 1 w# A0 $end
 $var wire 1 a# A1 $end
-$var wire 1 '% S $end
+$var wire 1 %% S $end
 $var supply1 1 d. VPWR $end
 $var supply0 1 e. VGND $end
 $var supply1 1 f. VPB $end
@@ -3364,16 +3364,16 @@ $scope module base $end
 $var wire 1 a. X $end
 $var wire 1 w# A0 $end
 $var wire 1 a# A1 $end
-$var wire 1 '% S $end
+$var wire 1 %% S $end
 $var wire 1 h. mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
 $var wire 1 b. X $end
-$var wire 1 s% A0 $end
+$var wire 1 r% A0 $end
 $var wire 1 a. A1 $end
-$var wire 1 (% S $end
+$var wire 1 &% S $end
 $var supply1 1 i. VPWR $end
 $var supply0 1 j. VGND $end
 $var supply1 1 k. VPB $end
@@ -3381,9 +3381,9 @@ $var supply0 1 l. VNB $end
 
 $scope module base $end
 $var wire 1 b. X $end
-$var wire 1 s% A0 $end
+$var wire 1 r% A0 $end
 $var wire 1 a. A1 $end
-$var wire 1 (% S $end
+$var wire 1 &% S $end
 $var wire 1 m. mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -3422,12 +3422,12 @@ $upscope $end
 $scope module mux_left_track_11 $end
 $var wire 1 O# in [0] $end
 $var wire 1 }# in [1] $end
-$var wire 1 Y$ sram [0] $end
-$var wire 1 Z$ sram [1] $end
-$var wire 1 :& sram_inv [0] $end
-$var wire 1 ;& sram_inv [1] $end
+$var wire 1 W$ sram [0] $end
+$var wire 1 X$ sram [1] $end
+$var wire 1 9& sram_inv [0] $end
+$var wire 1 :& sram_inv [1] $end
 $var wire 1 A$ out [0] $end
-$var wire 1 <& p0 $end
+$var wire 1 ;& p0 $end
 $var wire 1 x. sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 y. sky130_fd_sc_hd__mux2_1_1_X [0] $end
 $var wire 1 z. BUF_net_72 $end
@@ -3436,7 +3436,7 @@ $scope module mux_l1_in_0_ $end
 $var wire 1 x. X $end
 $var wire 1 }# A0 $end
 $var wire 1 O# A1 $end
-$var wire 1 Y$ S $end
+$var wire 1 W$ S $end
 $var supply1 1 {. VPWR $end
 $var supply0 1 |. VGND $end
 $var supply1 1 }. VPB $end
@@ -3446,16 +3446,16 @@ $scope module base $end
 $var wire 1 x. X $end
 $var wire 1 }# A0 $end
 $var wire 1 O# A1 $end
-$var wire 1 Y$ S $end
+$var wire 1 W$ S $end
 $var wire 1 !/ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
 $var wire 1 y. X $end
-$var wire 1 <& A0 $end
+$var wire 1 ;& A0 $end
 $var wire 1 x. A1 $end
-$var wire 1 Z$ S $end
+$var wire 1 X$ S $end
 $var supply1 1 "/ VPWR $end
 $var supply0 1 #/ VGND $end
 $var supply1 1 $/ VPB $end
@@ -3463,9 +3463,9 @@ $var supply0 1 %/ VNB $end
 
 $scope module base $end
 $var wire 1 y. X $end
-$var wire 1 <& A0 $end
+$var wire 1 ;& A0 $end
 $var wire 1 x. A1 $end
-$var wire 1 Z$ S $end
+$var wire 1 X$ S $end
 $var wire 1 &/ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -3504,12 +3504,12 @@ $upscope $end
 $scope module mux_left_track_13 $end
 $var wire 1 P# in [0] $end
 $var wire 1 ~# in [1] $end
-$var wire 1 [$ sram [0] $end
-$var wire 1 \$ sram [1] $end
-$var wire 1 =& sram_inv [0] $end
-$var wire 1 >& sram_inv [1] $end
+$var wire 1 Y$ sram [0] $end
+$var wire 1 Z$ sram [1] $end
+$var wire 1 <& sram_inv [0] $end
+$var wire 1 =& sram_inv [1] $end
 $var wire 1 B$ out [0] $end
-$var wire 1 <& p0 $end
+$var wire 1 r% p0 $end
 $var wire 1 1/ sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 2/ sky130_fd_sc_hd__mux2_1_1_X [0] $end
 $var wire 1 3/ BUF_net_74 $end
@@ -3518,7 +3518,7 @@ $scope module mux_l1_in_0_ $end
 $var wire 1 1/ X $end
 $var wire 1 ~# A0 $end
 $var wire 1 P# A1 $end
-$var wire 1 [$ S $end
+$var wire 1 Y$ S $end
 $var supply1 1 4/ VPWR $end
 $var supply0 1 5/ VGND $end
 $var supply1 1 6/ VPB $end
@@ -3528,16 +3528,16 @@ $scope module base $end
 $var wire 1 1/ X $end
 $var wire 1 ~# A0 $end
 $var wire 1 P# A1 $end
-$var wire 1 [$ S $end
+$var wire 1 Y$ S $end
 $var wire 1 8/ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
 $var wire 1 2/ X $end
-$var wire 1 <& A0 $end
+$var wire 1 r% A0 $end
 $var wire 1 1/ A1 $end
-$var wire 1 \$ S $end
+$var wire 1 Z$ S $end
 $var supply1 1 9/ VPWR $end
 $var supply0 1 :/ VGND $end
 $var supply1 1 ;/ VPB $end
@@ -3545,9 +3545,9 @@ $var supply0 1 </ VNB $end
 
 $scope module base $end
 $var wire 1 2/ X $end
-$var wire 1 <& A0 $end
+$var wire 1 r% A0 $end
 $var wire 1 1/ A1 $end
-$var wire 1 \$ S $end
+$var wire 1 Z$ S $end
 $var wire 1 =/ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -3586,12 +3586,12 @@ $upscope $end
 $scope module mux_left_track_15 $end
 $var wire 1 Q# in [0] $end
 $var wire 1 !$ in [1] $end
-$var wire 1 ]$ sram [0] $end
-$var wire 1 ^$ sram [1] $end
-$var wire 1 ?& sram_inv [0] $end
-$var wire 1 @& sram_inv [1] $end
+$var wire 1 [$ sram [0] $end
+$var wire 1 \$ sram [1] $end
+$var wire 1 >& sram_inv [0] $end
+$var wire 1 ?& sram_inv [1] $end
 $var wire 1 C$ out [0] $end
-$var wire 1 <& p0 $end
+$var wire 1 ;& p0 $end
 $var wire 1 H/ sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 I/ sky130_fd_sc_hd__mux2_1_1_X [0] $end
 $var wire 1 J/ BUF_net_76 $end
@@ -3600,7 +3600,7 @@ $scope module mux_l1_in_0_ $end
 $var wire 1 H/ X $end
 $var wire 1 !$ A0 $end
 $var wire 1 Q# A1 $end
-$var wire 1 ]$ S $end
+$var wire 1 [$ S $end
 $var supply1 1 K/ VPWR $end
 $var supply0 1 L/ VGND $end
 $var supply1 1 M/ VPB $end
@@ -3610,16 +3610,16 @@ $scope module base $end
 $var wire 1 H/ X $end
 $var wire 1 !$ A0 $end
 $var wire 1 Q# A1 $end
-$var wire 1 ]$ S $end
+$var wire 1 [$ S $end
 $var wire 1 O/ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
 $var wire 1 I/ X $end
-$var wire 1 <& A0 $end
+$var wire 1 ;& A0 $end
 $var wire 1 H/ A1 $end
-$var wire 1 ^$ S $end
+$var wire 1 \$ S $end
 $var supply1 1 P/ VPWR $end
 $var supply0 1 Q/ VGND $end
 $var supply1 1 R/ VPB $end
@@ -3627,9 +3627,9 @@ $var supply0 1 S/ VNB $end
 
 $scope module base $end
 $var wire 1 I/ X $end
-$var wire 1 <& A0 $end
+$var wire 1 ;& A0 $end
 $var wire 1 H/ A1 $end
-$var wire 1 ^$ S $end
+$var wire 1 \$ S $end
 $var wire 1 T/ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -3668,12 +3668,12 @@ $upscope $end
 $scope module mux_left_track_17 $end
 $var wire 1 R# in [0] $end
 $var wire 1 "$ in [1] $end
-$var wire 1 _$ sram [0] $end
-$var wire 1 `$ sram [1] $end
-$var wire 1 A& sram_inv [0] $end
-$var wire 1 B& sram_inv [1] $end
+$var wire 1 ]$ sram [0] $end
+$var wire 1 ^$ sram [1] $end
+$var wire 1 @& sram_inv [0] $end
+$var wire 1 A& sram_inv [1] $end
 $var wire 1 D$ out [0] $end
-$var wire 1 <& p0 $end
+$var wire 1 r% p0 $end
 $var wire 1 _/ sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 `/ sky130_fd_sc_hd__mux2_1_1_X [0] $end
 
@@ -3696,7 +3696,7 @@ $scope module mux_l1_in_0_ $end
 $var wire 1 _/ X $end
 $var wire 1 "$ A0 $end
 $var wire 1 R# A1 $end
-$var wire 1 _$ S $end
+$var wire 1 ]$ S $end
 $var supply1 1 f/ VPWR $end
 $var supply0 1 g/ VGND $end
 $var supply1 1 h/ VPB $end
@@ -3706,16 +3706,16 @@ $scope module base $end
 $var wire 1 _/ X $end
 $var wire 1 "$ A0 $end
 $var wire 1 R# A1 $end
-$var wire 1 _$ S $end
+$var wire 1 ]$ S $end
 $var wire 1 j/ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
 $var wire 1 `/ X $end
-$var wire 1 <& A0 $end
+$var wire 1 r% A0 $end
 $var wire 1 _/ A1 $end
-$var wire 1 `$ S $end
+$var wire 1 ^$ S $end
 $var supply1 1 k/ VPWR $end
 $var supply0 1 l/ VGND $end
 $var supply1 1 m/ VPB $end
@@ -3723,9 +3723,9 @@ $var supply0 1 n/ VNB $end
 
 $scope module base $end
 $var wire 1 `/ X $end
-$var wire 1 <& A0 $end
+$var wire 1 r% A0 $end
 $var wire 1 _/ A1 $end
-$var wire 1 `$ S $end
+$var wire 1 ^$ S $end
 $var wire 1 o/ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -3734,12 +3734,12 @@ $upscope $end
 $scope module mux_left_track_19 $end
 $var wire 1 S# in [0] $end
 $var wire 1 #$ in [1] $end
-$var wire 1 a$ sram [0] $end
-$var wire 1 b$ sram [1] $end
-$var wire 1 C& sram_inv [0] $end
-$var wire 1 D& sram_inv [1] $end
+$var wire 1 _$ sram [0] $end
+$var wire 1 `$ sram [1] $end
+$var wire 1 B& sram_inv [0] $end
+$var wire 1 C& sram_inv [1] $end
 $var wire 1 E$ out [0] $end
-$var wire 1 s% p0 $end
+$var wire 1 ;& p0 $end
 $var wire 1 p/ sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 q/ sky130_fd_sc_hd__mux2_1_1_X [0] $end
 
@@ -3762,7 +3762,7 @@ $scope module mux_l1_in_0_ $end
 $var wire 1 p/ X $end
 $var wire 1 #$ A0 $end
 $var wire 1 S# A1 $end
-$var wire 1 a$ S $end
+$var wire 1 _$ S $end
 $var supply1 1 w/ VPWR $end
 $var supply0 1 x/ VGND $end
 $var supply1 1 y/ VPB $end
@@ -3772,16 +3772,16 @@ $scope module base $end
 $var wire 1 p/ X $end
 $var wire 1 #$ A0 $end
 $var wire 1 S# A1 $end
-$var wire 1 a$ S $end
+$var wire 1 _$ S $end
 $var wire 1 {/ mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
 $var wire 1 q/ X $end
-$var wire 1 s% A0 $end
+$var wire 1 ;& A0 $end
 $var wire 1 p/ A1 $end
-$var wire 1 b$ S $end
+$var wire 1 `$ S $end
 $var supply1 1 |/ VPWR $end
 $var supply0 1 }/ VGND $end
 $var supply1 1 ~/ VPB $end
@@ -3789,9 +3789,9 @@ $var supply0 1 !0 VNB $end
 
 $scope module base $end
 $var wire 1 q/ X $end
-$var wire 1 s% A0 $end
+$var wire 1 ;& A0 $end
 $var wire 1 p/ A1 $end
-$var wire 1 b$ S $end
+$var wire 1 `$ S $end
 $var wire 1 "0 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -3800,12 +3800,12 @@ $upscope $end
 $scope module mux_left_track_21 $end
 $var wire 1 T# in [0] $end
 $var wire 1 $$ in [1] $end
-$var wire 1 c$ sram [0] $end
-$var wire 1 d$ sram [1] $end
-$var wire 1 E& sram_inv [0] $end
-$var wire 1 F& sram_inv [1] $end
+$var wire 1 a$ sram [0] $end
+$var wire 1 b$ sram [1] $end
+$var wire 1 D& sram_inv [0] $end
+$var wire 1 E& sram_inv [1] $end
 $var wire 1 F$ out [0] $end
-$var wire 1 s% p0 $end
+$var wire 1 j% p0 $end
 $var wire 1 #0 sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 $0 sky130_fd_sc_hd__mux2_1_1_X [0] $end
 $var wire 1 %0 BUF_net_78 $end
@@ -3814,7 +3814,7 @@ $scope module mux_l1_in_0_ $end
 $var wire 1 #0 X $end
 $var wire 1 $$ A0 $end
 $var wire 1 T# A1 $end
-$var wire 1 c$ S $end
+$var wire 1 a$ S $end
 $var supply1 1 &0 VPWR $end
 $var supply0 1 '0 VGND $end
 $var supply1 1 (0 VPB $end
@@ -3824,16 +3824,16 @@ $scope module base $end
 $var wire 1 #0 X $end
 $var wire 1 $$ A0 $end
 $var wire 1 T# A1 $end
-$var wire 1 c$ S $end
+$var wire 1 a$ S $end
 $var wire 1 *0 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
 $var wire 1 $0 X $end
-$var wire 1 s% A0 $end
+$var wire 1 j% A0 $end
 $var wire 1 #0 A1 $end
-$var wire 1 d$ S $end
+$var wire 1 b$ S $end
 $var supply1 1 +0 VPWR $end
 $var supply0 1 ,0 VGND $end
 $var supply1 1 -0 VPB $end
@@ -3841,9 +3841,9 @@ $var supply0 1 .0 VNB $end
 
 $scope module base $end
 $var wire 1 $0 X $end
-$var wire 1 s% A0 $end
+$var wire 1 j% A0 $end
 $var wire 1 #0 A1 $end
-$var wire 1 d$ S $end
+$var wire 1 b$ S $end
 $var wire 1 /0 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
@@ -3882,81 +3882,65 @@ $upscope $end
 $scope module mux_left_track_23 $end
 $var wire 1 U# in [0] $end
 $var wire 1 %$ in [1] $end
-$var wire 1 e$ sram [0] $end
-$var wire 1 f$ sram [1] $end
-$var wire 1 G& sram_inv [0] $end
-$var wire 1 H& sram_inv [1] $end
+$var wire 1 c$ sram [0] $end
+$var wire 1 d$ sram [1] $end
+$var wire 1 F& sram_inv [0] $end
+$var wire 1 G& sram_inv [1] $end
 $var wire 1 G$ out [0] $end
-$var wire 1 '& p0 $end
+$var wire 1 ,& p0 $end
 $var wire 1 :0 sky130_fd_sc_hd__mux2_1_0_X [0] $end
 $var wire 1 ;0 sky130_fd_sc_hd__mux2_1_1_X [0] $end
-$var wire 1 <0 BUF_net_80 $end
+
+$scope module sky130_fd_sc_hd__buf_4_0_ $end
+$var wire 1 G$ X $end
+$var wire 1 ;0 A $end
+$var supply1 1 <0 VPWR $end
+$var supply0 1 =0 VGND $end
+$var supply1 1 >0 VPB $end
+$var supply0 1 ?0 VNB $end
+
+$scope module base $end
+$var wire 1 G$ X $end
+$var wire 1 ;0 A $end
+$var wire 1 @0 buf0_out_X $end
+$upscope $end
+$upscope $end
 
 $scope module mux_l1_in_0_ $end
 $var wire 1 :0 X $end
 $var wire 1 %$ A0 $end
 $var wire 1 U# A1 $end
-$var wire 1 e$ S $end
-$var supply1 1 =0 VPWR $end
-$var supply0 1 >0 VGND $end
-$var supply1 1 ?0 VPB $end
-$var supply0 1 @0 VNB $end
+$var wire 1 c$ S $end
+$var supply1 1 A0 VPWR $end
+$var supply0 1 B0 VGND $end
+$var supply1 1 C0 VPB $end
+$var supply0 1 D0 VNB $end
 
 $scope module base $end
 $var wire 1 :0 X $end
 $var wire 1 %$ A0 $end
 $var wire 1 U# A1 $end
-$var wire 1 e$ S $end
-$var wire 1 A0 mux_2to10_out_X $end
+$var wire 1 c$ S $end
+$var wire 1 E0 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
 $var wire 1 ;0 X $end
-$var wire 1 '& A0 $end
+$var wire 1 ,& A0 $end
 $var wire 1 :0 A1 $end
-$var wire 1 f$ S $end
-$var supply1 1 B0 VPWR $end
-$var supply0 1 C0 VGND $end
-$var supply1 1 D0 VPB $end
-$var supply0 1 E0 VNB $end
+$var wire 1 d$ S $end
+$var supply1 1 F0 VPWR $end
+$var supply0 1 G0 VGND $end
+$var supply1 1 H0 VPB $end
+$var supply0 1 I0 VNB $end
 
 $scope module base $end
 $var wire 1 ;0 X $end
-$var wire 1 '& A0 $end
+$var wire 1 ,& A0 $end
 $var wire 1 :0 A1 $end
-$var wire 1 f$ S $end
-$var wire 1 F0 mux_2to10_out_X $end
-$upscope $end
-$upscope $end
-
-$scope module BINV_R_79 $end
-$var wire 1 G$ Y $end
-$var wire 1 <0 A $end
-$var supply1 1 G0 VPWR $end
-$var supply0 1 H0 VGND $end
-$var supply1 1 I0 VPB $end
-$var supply0 1 J0 VNB $end
-
-$scope module base $end
-$var wire 1 G$ Y $end
-$var wire 1 <0 A $end
-$var wire 1 K0 not0_out_Y $end
-$upscope $end
-$upscope $end
-
-$scope module BINV_R_80 $end
-$var wire 1 <0 Y $end
-$var wire 1 ;0 A $end
-$var supply1 1 L0 VPWR $end
-$var supply0 1 M0 VGND $end
-$var supply1 1 N0 VPB $end
-$var supply0 1 O0 VNB $end
-
-$scope module base $end
-$var wire 1 <0 Y $end
-$var wire 1 ;0 A $end
-$var wire 1 P0 not0_out_Y $end
+$var wire 1 d$ S $end
+$var wire 1 J0 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -3964,81 +3948,65 @@ $upscope $end
 $scope module mux_left_track_27 $end
 $var wire 1 W# in [0] $end
 $var wire 1 }# in [1] $end
-$var wire 1 g$ sram [0] $end
-$var wire 1 h$ sram [1] $end
-$var wire 1 I& sram_inv [0] $end
-$var wire 1 J& sram_inv [1] $end
+$var wire 1 e$ sram [0] $end
+$var wire 1 f$ sram [1] $end
+$var wire 1 H& sram_inv [0] $end
+$var wire 1 I& sram_inv [1] $end
 $var wire 1 I$ out [0] $end
-$var wire 1 <& p0 $end
-$var wire 1 Q0 sky130_fd_sc_hd__mux2_1_0_X [0] $end
-$var wire 1 R0 sky130_fd_sc_hd__mux2_1_1_X [0] $end
-$var wire 1 S0 BUF_net_82 $end
+$var wire 1 ;& p0 $end
+$var wire 1 K0 sky130_fd_sc_hd__mux2_1_0_X [0] $end
+$var wire 1 L0 sky130_fd_sc_hd__mux2_1_1_X [0] $end
 
-$scope module mux_l1_in_0_ $end
-$var wire 1 Q0 X $end
-$var wire 1 }# A0 $end
-$var wire 1 W# A1 $end
-$var wire 1 g$ S $end
-$var supply1 1 T0 VPWR $end
-$var supply0 1 U0 VGND $end
-$var supply1 1 V0 VPB $end
-$var supply0 1 W0 VNB $end
+$scope module sky130_fd_sc_hd__buf_4_0_ $end
+$var wire 1 I$ X $end
+$var wire 1 L0 A $end
+$var supply1 1 M0 VPWR $end
+$var supply0 1 N0 VGND $end
+$var supply1 1 O0 VPB $end
+$var supply0 1 P0 VNB $end
 
 $scope module base $end
-$var wire 1 Q0 X $end
+$var wire 1 I$ X $end
+$var wire 1 L0 A $end
+$var wire 1 Q0 buf0_out_X $end
+$upscope $end
+$upscope $end
+
+$scope module mux_l1_in_0_ $end
+$var wire 1 K0 X $end
 $var wire 1 }# A0 $end
 $var wire 1 W# A1 $end
-$var wire 1 g$ S $end
-$var wire 1 X0 mux_2to10_out_X $end
+$var wire 1 e$ S $end
+$var supply1 1 R0 VPWR $end
+$var supply0 1 S0 VGND $end
+$var supply1 1 T0 VPB $end
+$var supply0 1 U0 VNB $end
+
+$scope module base $end
+$var wire 1 K0 X $end
+$var wire 1 }# A0 $end
+$var wire 1 W# A1 $end
+$var wire 1 e$ S $end
+$var wire 1 V0 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
-$var wire 1 R0 X $end
-$var wire 1 <& A0 $end
-$var wire 1 Q0 A1 $end
-$var wire 1 h$ S $end
-$var supply1 1 Y0 VPWR $end
-$var supply0 1 Z0 VGND $end
-$var supply1 1 [0 VPB $end
-$var supply0 1 \0 VNB $end
+$var wire 1 L0 X $end
+$var wire 1 ;& A0 $end
+$var wire 1 K0 A1 $end
+$var wire 1 f$ S $end
+$var supply1 1 W0 VPWR $end
+$var supply0 1 X0 VGND $end
+$var supply1 1 Y0 VPB $end
+$var supply0 1 Z0 VNB $end
 
 $scope module base $end
-$var wire 1 R0 X $end
-$var wire 1 <& A0 $end
-$var wire 1 Q0 A1 $end
-$var wire 1 h$ S $end
-$var wire 1 ]0 mux_2to10_out_X $end
-$upscope $end
-$upscope $end
-
-$scope module BINV_R_81 $end
-$var wire 1 I$ Y $end
-$var wire 1 S0 A $end
-$var supply1 1 ^0 VPWR $end
-$var supply0 1 _0 VGND $end
-$var supply1 1 `0 VPB $end
-$var supply0 1 a0 VNB $end
-
-$scope module base $end
-$var wire 1 I$ Y $end
-$var wire 1 S0 A $end
-$var wire 1 b0 not0_out_Y $end
-$upscope $end
-$upscope $end
-
-$scope module BINV_R_82 $end
-$var wire 1 S0 Y $end
-$var wire 1 R0 A $end
-$var supply1 1 c0 VPWR $end
-$var supply0 1 d0 VGND $end
-$var supply1 1 e0 VPB $end
-$var supply0 1 f0 VNB $end
-
-$scope module base $end
-$var wire 1 S0 Y $end
-$var wire 1 R0 A $end
-$var wire 1 g0 not0_out_Y $end
+$var wire 1 L0 X $end
+$var wire 1 ;& A0 $end
+$var wire 1 K0 A1 $end
+$var wire 1 f$ S $end
+$var wire 1 [0 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -4046,81 +4014,81 @@ $upscope $end
 $scope module mux_left_track_29 $end
 $var wire 1 X# in [0] $end
 $var wire 1 ~# in [1] $end
-$var wire 1 i$ sram [0] $end
-$var wire 1 j$ sram [1] $end
-$var wire 1 K& sram_inv [0] $end
-$var wire 1 L& sram_inv [1] $end
+$var wire 1 g$ sram [0] $end
+$var wire 1 h$ sram [1] $end
+$var wire 1 J& sram_inv [0] $end
+$var wire 1 K& sram_inv [1] $end
 $var wire 1 J$ out [0] $end
-$var wire 1 <& p0 $end
-$var wire 1 h0 sky130_fd_sc_hd__mux2_1_0_X [0] $end
-$var wire 1 i0 sky130_fd_sc_hd__mux2_1_1_X [0] $end
-$var wire 1 j0 BUF_net_84 $end
+$var wire 1 ;& p0 $end
+$var wire 1 \0 sky130_fd_sc_hd__mux2_1_0_X [0] $end
+$var wire 1 ]0 sky130_fd_sc_hd__mux2_1_1_X [0] $end
+$var wire 1 ^0 BUF_net_80 $end
 
 $scope module mux_l1_in_0_ $end
-$var wire 1 h0 X $end
+$var wire 1 \0 X $end
 $var wire 1 ~# A0 $end
 $var wire 1 X# A1 $end
-$var wire 1 i$ S $end
-$var supply1 1 k0 VPWR $end
-$var supply0 1 l0 VGND $end
-$var supply1 1 m0 VPB $end
-$var supply0 1 n0 VNB $end
+$var wire 1 g$ S $end
+$var supply1 1 _0 VPWR $end
+$var supply0 1 `0 VGND $end
+$var supply1 1 a0 VPB $end
+$var supply0 1 b0 VNB $end
 
 $scope module base $end
-$var wire 1 h0 X $end
+$var wire 1 \0 X $end
 $var wire 1 ~# A0 $end
 $var wire 1 X# A1 $end
-$var wire 1 i$ S $end
-$var wire 1 o0 mux_2to10_out_X $end
+$var wire 1 g$ S $end
+$var wire 1 c0 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
-$var wire 1 i0 X $end
-$var wire 1 <& A0 $end
-$var wire 1 h0 A1 $end
-$var wire 1 j$ S $end
-$var supply1 1 p0 VPWR $end
-$var supply0 1 q0 VGND $end
-$var supply1 1 r0 VPB $end
-$var supply0 1 s0 VNB $end
+$var wire 1 ]0 X $end
+$var wire 1 ;& A0 $end
+$var wire 1 \0 A1 $end
+$var wire 1 h$ S $end
+$var supply1 1 d0 VPWR $end
+$var supply0 1 e0 VGND $end
+$var supply1 1 f0 VPB $end
+$var supply0 1 g0 VNB $end
 
 $scope module base $end
-$var wire 1 i0 X $end
-$var wire 1 <& A0 $end
-$var wire 1 h0 A1 $end
-$var wire 1 j$ S $end
-$var wire 1 t0 mux_2to10_out_X $end
+$var wire 1 ]0 X $end
+$var wire 1 ;& A0 $end
+$var wire 1 \0 A1 $end
+$var wire 1 h$ S $end
+$var wire 1 h0 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_83 $end
+$scope module BINV_R_79 $end
 $var wire 1 J$ Y $end
-$var wire 1 j0 A $end
-$var supply1 1 u0 VPWR $end
-$var supply0 1 v0 VGND $end
-$var supply1 1 w0 VPB $end
-$var supply0 1 x0 VNB $end
+$var wire 1 ^0 A $end
+$var supply1 1 i0 VPWR $end
+$var supply0 1 j0 VGND $end
+$var supply1 1 k0 VPB $end
+$var supply0 1 l0 VNB $end
 
 $scope module base $end
 $var wire 1 J$ Y $end
-$var wire 1 j0 A $end
-$var wire 1 y0 not0_out_Y $end
+$var wire 1 ^0 A $end
+$var wire 1 m0 not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_84 $end
-$var wire 1 j0 Y $end
-$var wire 1 i0 A $end
-$var supply1 1 z0 VPWR $end
-$var supply0 1 {0 VGND $end
-$var supply1 1 |0 VPB $end
-$var supply0 1 }0 VNB $end
+$scope module BINV_R_80 $end
+$var wire 1 ^0 Y $end
+$var wire 1 ]0 A $end
+$var supply1 1 n0 VPWR $end
+$var supply0 1 o0 VGND $end
+$var supply1 1 p0 VPB $end
+$var supply0 1 q0 VNB $end
 
 $scope module base $end
-$var wire 1 j0 Y $end
-$var wire 1 i0 A $end
-$var wire 1 ~0 not0_out_Y $end
+$var wire 1 ^0 Y $end
+$var wire 1 ]0 A $end
+$var wire 1 r0 not0_out_Y $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -4128,81 +4096,81 @@ $upscope $end
 $scope module mux_left_track_31 $end
 $var wire 1 Y# in [0] $end
 $var wire 1 !$ in [1] $end
-$var wire 1 k$ sram [0] $end
-$var wire 1 l$ sram [1] $end
-$var wire 1 M& sram_inv [0] $end
-$var wire 1 N& sram_inv [1] $end
+$var wire 1 i$ sram [0] $end
+$var wire 1 j$ sram [1] $end
+$var wire 1 L& sram_inv [0] $end
+$var wire 1 M& sram_inv [1] $end
 $var wire 1 K$ out [0] $end
-$var wire 1 <& p0 $end
-$var wire 1 !1 sky130_fd_sc_hd__mux2_1_0_X [0] $end
-$var wire 1 "1 sky130_fd_sc_hd__mux2_1_1_X [0] $end
-$var wire 1 #1 BUF_net_86 $end
+$var wire 1 ;& p0 $end
+$var wire 1 s0 sky130_fd_sc_hd__mux2_1_0_X [0] $end
+$var wire 1 t0 sky130_fd_sc_hd__mux2_1_1_X [0] $end
+$var wire 1 u0 BUF_net_82 $end
 
 $scope module mux_l1_in_0_ $end
-$var wire 1 !1 X $end
+$var wire 1 s0 X $end
 $var wire 1 !$ A0 $end
 $var wire 1 Y# A1 $end
-$var wire 1 k$ S $end
-$var supply1 1 $1 VPWR $end
-$var supply0 1 %1 VGND $end
-$var supply1 1 &1 VPB $end
-$var supply0 1 '1 VNB $end
+$var wire 1 i$ S $end
+$var supply1 1 v0 VPWR $end
+$var supply0 1 w0 VGND $end
+$var supply1 1 x0 VPB $end
+$var supply0 1 y0 VNB $end
 
 $scope module base $end
-$var wire 1 !1 X $end
+$var wire 1 s0 X $end
 $var wire 1 !$ A0 $end
 $var wire 1 Y# A1 $end
-$var wire 1 k$ S $end
-$var wire 1 (1 mux_2to10_out_X $end
+$var wire 1 i$ S $end
+$var wire 1 z0 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
-$var wire 1 "1 X $end
-$var wire 1 <& A0 $end
-$var wire 1 !1 A1 $end
-$var wire 1 l$ S $end
-$var supply1 1 )1 VPWR $end
-$var supply0 1 *1 VGND $end
-$var supply1 1 +1 VPB $end
-$var supply0 1 ,1 VNB $end
+$var wire 1 t0 X $end
+$var wire 1 ;& A0 $end
+$var wire 1 s0 A1 $end
+$var wire 1 j$ S $end
+$var supply1 1 {0 VPWR $end
+$var supply0 1 |0 VGND $end
+$var supply1 1 }0 VPB $end
+$var supply0 1 ~0 VNB $end
 
 $scope module base $end
-$var wire 1 "1 X $end
-$var wire 1 <& A0 $end
-$var wire 1 !1 A1 $end
-$var wire 1 l$ S $end
-$var wire 1 -1 mux_2to10_out_X $end
+$var wire 1 t0 X $end
+$var wire 1 ;& A0 $end
+$var wire 1 s0 A1 $end
+$var wire 1 j$ S $end
+$var wire 1 !1 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_85 $end
+$scope module BINV_R_81 $end
 $var wire 1 K$ Y $end
-$var wire 1 #1 A $end
-$var supply1 1 .1 VPWR $end
-$var supply0 1 /1 VGND $end
-$var supply1 1 01 VPB $end
-$var supply0 1 11 VNB $end
+$var wire 1 u0 A $end
+$var supply1 1 "1 VPWR $end
+$var supply0 1 #1 VGND $end
+$var supply1 1 $1 VPB $end
+$var supply0 1 %1 VNB $end
 
 $scope module base $end
 $var wire 1 K$ Y $end
-$var wire 1 #1 A $end
-$var wire 1 21 not0_out_Y $end
+$var wire 1 u0 A $end
+$var wire 1 &1 not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_86 $end
-$var wire 1 #1 Y $end
-$var wire 1 "1 A $end
-$var supply1 1 31 VPWR $end
-$var supply0 1 41 VGND $end
-$var supply1 1 51 VPB $end
-$var supply0 1 61 VNB $end
+$scope module BINV_R_82 $end
+$var wire 1 u0 Y $end
+$var wire 1 t0 A $end
+$var supply1 1 '1 VPWR $end
+$var supply0 1 (1 VGND $end
+$var supply1 1 )1 VPB $end
+$var supply0 1 *1 VNB $end
 
 $scope module base $end
-$var wire 1 #1 Y $end
-$var wire 1 "1 A $end
-$var wire 1 71 not0_out_Y $end
+$var wire 1 u0 Y $end
+$var wire 1 t0 A $end
+$var wire 1 +1 not0_out_Y $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -4210,81 +4178,81 @@ $upscope $end
 $scope module mux_left_track_33 $end
 $var wire 1 Z# in [0] $end
 $var wire 1 "$ in [1] $end
-$var wire 1 o$ sram [0] $end
-$var wire 1 p$ sram [1] $end
-$var wire 1 O& sram_inv [0] $end
-$var wire 1 P& sram_inv [1] $end
+$var wire 1 m$ sram [0] $end
+$var wire 1 n$ sram [1] $end
+$var wire 1 N& sram_inv [0] $end
+$var wire 1 O& sram_inv [1] $end
 $var wire 1 L$ out [0] $end
-$var wire 1 <& p0 $end
-$var wire 1 81 sky130_fd_sc_hd__mux2_1_0_X [0] $end
-$var wire 1 91 sky130_fd_sc_hd__mux2_1_1_X [0] $end
-$var wire 1 :1 BUF_net_88 $end
+$var wire 1 ;& p0 $end
+$var wire 1 ,1 sky130_fd_sc_hd__mux2_1_0_X [0] $end
+$var wire 1 -1 sky130_fd_sc_hd__mux2_1_1_X [0] $end
+$var wire 1 .1 BUF_net_84 $end
 
 $scope module mux_l1_in_0_ $end
-$var wire 1 81 X $end
+$var wire 1 ,1 X $end
 $var wire 1 "$ A0 $end
 $var wire 1 Z# A1 $end
-$var wire 1 o$ S $end
-$var supply1 1 ;1 VPWR $end
-$var supply0 1 <1 VGND $end
-$var supply1 1 =1 VPB $end
-$var supply0 1 >1 VNB $end
+$var wire 1 m$ S $end
+$var supply1 1 /1 VPWR $end
+$var supply0 1 01 VGND $end
+$var supply1 1 11 VPB $end
+$var supply0 1 21 VNB $end
 
 $scope module base $end
-$var wire 1 81 X $end
+$var wire 1 ,1 X $end
 $var wire 1 "$ A0 $end
 $var wire 1 Z# A1 $end
-$var wire 1 o$ S $end
-$var wire 1 ?1 mux_2to10_out_X $end
+$var wire 1 m$ S $end
+$var wire 1 31 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
-$var wire 1 91 X $end
-$var wire 1 <& A0 $end
-$var wire 1 81 A1 $end
-$var wire 1 p$ S $end
-$var supply1 1 @1 VPWR $end
-$var supply0 1 A1 VGND $end
-$var supply1 1 B1 VPB $end
-$var supply0 1 C1 VNB $end
+$var wire 1 -1 X $end
+$var wire 1 ;& A0 $end
+$var wire 1 ,1 A1 $end
+$var wire 1 n$ S $end
+$var supply1 1 41 VPWR $end
+$var supply0 1 51 VGND $end
+$var supply1 1 61 VPB $end
+$var supply0 1 71 VNB $end
 
 $scope module base $end
-$var wire 1 91 X $end
-$var wire 1 <& A0 $end
-$var wire 1 81 A1 $end
-$var wire 1 p$ S $end
-$var wire 1 D1 mux_2to10_out_X $end
+$var wire 1 -1 X $end
+$var wire 1 ;& A0 $end
+$var wire 1 ,1 A1 $end
+$var wire 1 n$ S $end
+$var wire 1 81 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_87 $end
+$scope module BINV_R_83 $end
 $var wire 1 L$ Y $end
-$var wire 1 :1 A $end
-$var supply1 1 E1 VPWR $end
-$var supply0 1 F1 VGND $end
-$var supply1 1 G1 VPB $end
-$var supply0 1 H1 VNB $end
+$var wire 1 .1 A $end
+$var supply1 1 91 VPWR $end
+$var supply0 1 :1 VGND $end
+$var supply1 1 ;1 VPB $end
+$var supply0 1 <1 VNB $end
 
 $scope module base $end
 $var wire 1 L$ Y $end
-$var wire 1 :1 A $end
-$var wire 1 I1 not0_out_Y $end
+$var wire 1 .1 A $end
+$var wire 1 =1 not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_88 $end
-$var wire 1 :1 Y $end
-$var wire 1 91 A $end
-$var supply1 1 J1 VPWR $end
-$var supply0 1 K1 VGND $end
-$var supply1 1 L1 VPB $end
-$var supply0 1 M1 VNB $end
+$scope module BINV_R_84 $end
+$var wire 1 .1 Y $end
+$var wire 1 -1 A $end
+$var supply1 1 >1 VPWR $end
+$var supply0 1 ?1 VGND $end
+$var supply1 1 @1 VPB $end
+$var supply0 1 A1 VNB $end
 
 $scope module base $end
-$var wire 1 :1 Y $end
-$var wire 1 91 A $end
-$var wire 1 N1 not0_out_Y $end
+$var wire 1 .1 Y $end
+$var wire 1 -1 A $end
+$var wire 1 B1 not0_out_Y $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -4292,65 +4260,65 @@ $upscope $end
 $scope module mux_left_track_35 $end
 $var wire 1 [# in [0] $end
 $var wire 1 #$ in [1] $end
-$var wire 1 q$ sram [0] $end
-$var wire 1 r$ sram [1] $end
-$var wire 1 Q& sram_inv [0] $end
-$var wire 1 R& sram_inv [1] $end
+$var wire 1 o$ sram [0] $end
+$var wire 1 p$ sram [1] $end
+$var wire 1 P& sram_inv [0] $end
+$var wire 1 Q& sram_inv [1] $end
 $var wire 1 M$ out [0] $end
-$var wire 1 <& p0 $end
-$var wire 1 O1 sky130_fd_sc_hd__mux2_1_0_X [0] $end
-$var wire 1 P1 sky130_fd_sc_hd__mux2_1_1_X [0] $end
+$var wire 1 ;& p0 $end
+$var wire 1 C1 sky130_fd_sc_hd__mux2_1_0_X [0] $end
+$var wire 1 D1 sky130_fd_sc_hd__mux2_1_1_X [0] $end
 
 $scope module sky130_fd_sc_hd__buf_4_0_ $end
 $var wire 1 M$ X $end
-$var wire 1 P1 A $end
-$var supply1 1 Q1 VPWR $end
-$var supply0 1 R1 VGND $end
-$var supply1 1 S1 VPB $end
-$var supply0 1 T1 VNB $end
+$var wire 1 D1 A $end
+$var supply1 1 E1 VPWR $end
+$var supply0 1 F1 VGND $end
+$var supply1 1 G1 VPB $end
+$var supply0 1 H1 VNB $end
 
 $scope module base $end
 $var wire 1 M$ X $end
-$var wire 1 P1 A $end
-$var wire 1 U1 buf0_out_X $end
+$var wire 1 D1 A $end
+$var wire 1 I1 buf0_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l1_in_0_ $end
-$var wire 1 O1 X $end
+$var wire 1 C1 X $end
 $var wire 1 #$ A0 $end
 $var wire 1 [# A1 $end
-$var wire 1 q$ S $end
-$var supply1 1 V1 VPWR $end
-$var supply0 1 W1 VGND $end
-$var supply1 1 X1 VPB $end
-$var supply0 1 Y1 VNB $end
+$var wire 1 o$ S $end
+$var supply1 1 J1 VPWR $end
+$var supply0 1 K1 VGND $end
+$var supply1 1 L1 VPB $end
+$var supply0 1 M1 VNB $end
 
 $scope module base $end
-$var wire 1 O1 X $end
+$var wire 1 C1 X $end
 $var wire 1 #$ A0 $end
 $var wire 1 [# A1 $end
-$var wire 1 q$ S $end
-$var wire 1 Z1 mux_2to10_out_X $end
+$var wire 1 o$ S $end
+$var wire 1 N1 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
-$var wire 1 P1 X $end
-$var wire 1 <& A0 $end
-$var wire 1 O1 A1 $end
-$var wire 1 r$ S $end
-$var supply1 1 [1 VPWR $end
-$var supply0 1 \1 VGND $end
-$var supply1 1 ]1 VPB $end
-$var supply0 1 ^1 VNB $end
+$var wire 1 D1 X $end
+$var wire 1 ;& A0 $end
+$var wire 1 C1 A1 $end
+$var wire 1 p$ S $end
+$var supply1 1 O1 VPWR $end
+$var supply0 1 P1 VGND $end
+$var supply1 1 Q1 VPB $end
+$var supply0 1 R1 VNB $end
 
 $scope module base $end
-$var wire 1 P1 X $end
-$var wire 1 <& A0 $end
-$var wire 1 O1 A1 $end
-$var wire 1 r$ S $end
-$var wire 1 _1 mux_2to10_out_X $end
+$var wire 1 D1 X $end
+$var wire 1 ;& A0 $end
+$var wire 1 C1 A1 $end
+$var wire 1 p$ S $end
+$var wire 1 S1 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -4358,65 +4326,65 @@ $upscope $end
 $scope module mux_left_track_37 $end
 $var wire 1 \# in [0] $end
 $var wire 1 $$ in [1] $end
-$var wire 1 s$ sram [0] $end
-$var wire 1 t$ sram [1] $end
-$var wire 1 S& sram_inv [0] $end
-$var wire 1 T& sram_inv [1] $end
+$var wire 1 q$ sram [0] $end
+$var wire 1 r$ sram [1] $end
+$var wire 1 R& sram_inv [0] $end
+$var wire 1 S& sram_inv [1] $end
 $var wire 1 N$ out [0] $end
-$var wire 1 '& p0 $end
-$var wire 1 `1 sky130_fd_sc_hd__mux2_1_0_X [0] $end
-$var wire 1 a1 sky130_fd_sc_hd__mux2_1_1_X [0] $end
+$var wire 1 ;& p0 $end
+$var wire 1 T1 sky130_fd_sc_hd__mux2_1_0_X [0] $end
+$var wire 1 U1 sky130_fd_sc_hd__mux2_1_1_X [0] $end
 
 $scope module sky130_fd_sc_hd__buf_4_0_ $end
 $var wire 1 N$ X $end
-$var wire 1 a1 A $end
-$var supply1 1 b1 VPWR $end
-$var supply0 1 c1 VGND $end
-$var supply1 1 d1 VPB $end
-$var supply0 1 e1 VNB $end
+$var wire 1 U1 A $end
+$var supply1 1 V1 VPWR $end
+$var supply0 1 W1 VGND $end
+$var supply1 1 X1 VPB $end
+$var supply0 1 Y1 VNB $end
 
 $scope module base $end
 $var wire 1 N$ X $end
-$var wire 1 a1 A $end
-$var wire 1 f1 buf0_out_X $end
+$var wire 1 U1 A $end
+$var wire 1 Z1 buf0_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l1_in_0_ $end
-$var wire 1 `1 X $end
+$var wire 1 T1 X $end
 $var wire 1 $$ A0 $end
 $var wire 1 \# A1 $end
-$var wire 1 s$ S $end
-$var supply1 1 g1 VPWR $end
-$var supply0 1 h1 VGND $end
-$var supply1 1 i1 VPB $end
-$var supply0 1 j1 VNB $end
+$var wire 1 q$ S $end
+$var supply1 1 [1 VPWR $end
+$var supply0 1 \1 VGND $end
+$var supply1 1 ]1 VPB $end
+$var supply0 1 ^1 VNB $end
 
 $scope module base $end
-$var wire 1 `1 X $end
+$var wire 1 T1 X $end
 $var wire 1 $$ A0 $end
 $var wire 1 \# A1 $end
-$var wire 1 s$ S $end
-$var wire 1 k1 mux_2to10_out_X $end
+$var wire 1 q$ S $end
+$var wire 1 _1 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
-$var wire 1 a1 X $end
-$var wire 1 '& A0 $end
-$var wire 1 `1 A1 $end
-$var wire 1 t$ S $end
-$var supply1 1 l1 VPWR $end
-$var supply0 1 m1 VGND $end
-$var supply1 1 n1 VPB $end
-$var supply0 1 o1 VNB $end
+$var wire 1 U1 X $end
+$var wire 1 ;& A0 $end
+$var wire 1 T1 A1 $end
+$var wire 1 r$ S $end
+$var supply1 1 `1 VPWR $end
+$var supply0 1 a1 VGND $end
+$var supply1 1 b1 VPB $end
+$var supply0 1 c1 VNB $end
 
 $scope module base $end
-$var wire 1 a1 X $end
-$var wire 1 '& A0 $end
-$var wire 1 `1 A1 $end
-$var wire 1 t$ S $end
-$var wire 1 p1 mux_2to10_out_X $end
+$var wire 1 U1 X $end
+$var wire 1 ;& A0 $end
+$var wire 1 T1 A1 $end
+$var wire 1 r$ S $end
+$var wire 1 d1 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -4424,1529 +4392,1529 @@ $upscope $end
 $scope module mux_left_track_39 $end
 $var wire 1 ]# in [0] $end
 $var wire 1 %$ in [1] $end
-$var wire 1 u$ sram [0] $end
-$var wire 1 v$ sram [1] $end
-$var wire 1 U& sram_inv [0] $end
-$var wire 1 V& sram_inv [1] $end
+$var wire 1 s$ sram [0] $end
+$var wire 1 t$ sram [1] $end
+$var wire 1 T& sram_inv [0] $end
+$var wire 1 U& sram_inv [1] $end
 $var wire 1 O$ out [0] $end
-$var wire 1 '& p0 $end
-$var wire 1 q1 sky130_fd_sc_hd__mux2_1_0_X [0] $end
-$var wire 1 r1 sky130_fd_sc_hd__mux2_1_1_X [0] $end
+$var wire 1 ,& p0 $end
+$var wire 1 e1 sky130_fd_sc_hd__mux2_1_0_X [0] $end
+$var wire 1 f1 sky130_fd_sc_hd__mux2_1_1_X [0] $end
 
 $scope module sky130_fd_sc_hd__buf_4_0_ $end
 $var wire 1 O$ X $end
-$var wire 1 r1 A $end
-$var supply1 1 s1 VPWR $end
-$var supply0 1 t1 VGND $end
-$var supply1 1 u1 VPB $end
-$var supply0 1 v1 VNB $end
+$var wire 1 f1 A $end
+$var supply1 1 g1 VPWR $end
+$var supply0 1 h1 VGND $end
+$var supply1 1 i1 VPB $end
+$var supply0 1 j1 VNB $end
 
 $scope module base $end
 $var wire 1 O$ X $end
-$var wire 1 r1 A $end
-$var wire 1 w1 buf0_out_X $end
+$var wire 1 f1 A $end
+$var wire 1 k1 buf0_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l1_in_0_ $end
-$var wire 1 q1 X $end
+$var wire 1 e1 X $end
 $var wire 1 %$ A0 $end
 $var wire 1 ]# A1 $end
-$var wire 1 u$ S $end
-$var supply1 1 x1 VPWR $end
-$var supply0 1 y1 VGND $end
-$var supply1 1 z1 VPB $end
-$var supply0 1 {1 VNB $end
+$var wire 1 s$ S $end
+$var supply1 1 l1 VPWR $end
+$var supply0 1 m1 VGND $end
+$var supply1 1 n1 VPB $end
+$var supply0 1 o1 VNB $end
 
 $scope module base $end
-$var wire 1 q1 X $end
+$var wire 1 e1 X $end
 $var wire 1 %$ A0 $end
 $var wire 1 ]# A1 $end
-$var wire 1 u$ S $end
-$var wire 1 |1 mux_2to10_out_X $end
+$var wire 1 s$ S $end
+$var wire 1 p1 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
-$var wire 1 r1 X $end
-$var wire 1 '& A0 $end
-$var wire 1 q1 A1 $end
-$var wire 1 v$ S $end
-$var supply1 1 }1 VPWR $end
-$var supply0 1 ~1 VGND $end
-$var supply1 1 !2 VPB $end
-$var supply0 1 "2 VNB $end
+$var wire 1 f1 X $end
+$var wire 1 ,& A0 $end
+$var wire 1 e1 A1 $end
+$var wire 1 t$ S $end
+$var supply1 1 q1 VPWR $end
+$var supply0 1 r1 VGND $end
+$var supply1 1 s1 VPB $end
+$var supply0 1 t1 VNB $end
 
 $scope module base $end
-$var wire 1 r1 X $end
-$var wire 1 '& A0 $end
-$var wire 1 q1 A1 $end
-$var wire 1 v$ S $end
-$var wire 1 #2 mux_2to10_out_X $end
+$var wire 1 f1 X $end
+$var wire 1 ,& A0 $end
+$var wire 1 e1 A1 $end
+$var wire 1 t$ S $end
+$var wire 1 u1 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
 
 $scope module mem_bottom_track_9 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 V% ccff_head [0] $end
-$var wire 1 )% ccff_tail [0] $end
-$var wire 1 W$ mem_out [0] $end
-$var wire 1 X$ mem_out [1] $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 T% ccff_head [0] $end
+$var wire 1 '% ccff_tail [0] $end
+$var wire 1 U$ mem_out [0] $end
+$var wire 1 V$ mem_out [1] $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 W$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 V% D $end
-$var supply1 1 $2 VPWR $end
-$var supply0 1 %2 VGND $end
-$var supply1 1 &2 VPB $end
-$var supply0 1 '2 VNB $end
+$var wire 1 U$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 T% D $end
+$var supply1 1 v1 VPWR $end
+$var supply0 1 w1 VGND $end
+$var supply1 1 x1 VPB $end
+$var supply0 1 y1 VNB $end
 
 $scope module base $end
-$var wire 1 W$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 V% D $end
-$var wire 1 (2 buf_Q $end
+$var wire 1 U$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 T% D $end
+$var wire 1 z1 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 X$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 W$ D $end
-$var supply1 1 )2 VPWR $end
-$var supply0 1 *2 VGND $end
-$var supply1 1 +2 VPB $end
-$var supply0 1 ,2 VNB $end
+$var wire 1 V$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 U$ D $end
+$var supply1 1 {1 VPWR $end
+$var supply0 1 |1 VGND $end
+$var supply1 1 }1 VPB $end
+$var supply0 1 ~1 VNB $end
 
 $scope module base $end
-$var wire 1 X$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 W$ D $end
-$var wire 1 -2 buf_Q $end
+$var wire 1 V$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 U$ D $end
+$var wire 1 !2 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_9__8 $end
-$var wire 1 )% X $end
-$var wire 1 X$ A $end
-$var supply1 1 .2 VPWR $end
-$var supply0 1 /2 VGND $end
-$var supply1 1 02 VPB $end
-$var supply0 1 12 VNB $end
+$var wire 1 '% X $end
+$var wire 1 V$ A $end
+$var supply1 1 "2 VPWR $end
+$var supply0 1 #2 VGND $end
+$var supply1 1 $2 VPB $end
+$var supply0 1 %2 VNB $end
 
 $scope module base $end
-$var wire 1 )% X $end
-$var wire 1 X$ A $end
-$var wire 1 22 buf0_out_X $end
+$var wire 1 '% X $end
+$var wire 1 V$ A $end
+$var wire 1 &2 buf0_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
 
 $scope module mem_bottom_track_11 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 )% ccff_head [0] $end
-$var wire 1 4% ccff_tail [0] $end
-$var wire 1 m$ mem_out [0] $end
-$var wire 1 n$ mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 m$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 )% D $end
-$var supply1 1 32 VPWR $end
-$var supply0 1 42 VGND $end
-$var supply1 1 52 VPB $end
-$var supply0 1 62 VNB $end
-
-$scope module base $end
-$var wire 1 m$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 )% D $end
-$var wire 1 72 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 n$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 m$ D $end
-$var supply1 1 82 VPWR $end
-$var supply0 1 92 VGND $end
-$var supply1 1 :2 VPB $end
-$var supply0 1 ;2 VNB $end
-
-$scope module base $end
-$var wire 1 n$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 m$ D $end
-$var wire 1 <2 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_10__9 $end
-$var wire 1 4% X $end
-$var wire 1 n$ A $end
-$var supply1 1 =2 VPWR $end
-$var supply0 1 >2 VGND $end
-$var supply1 1 ?2 VPB $end
-$var supply0 1 @2 VNB $end
-
-$scope module base $end
-$var wire 1 4% X $end
-$var wire 1 n$ A $end
-$var wire 1 A2 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_bottom_track_13 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 4% ccff_head [0] $end
-$var wire 1 8% ccff_tail [0] $end
-$var wire 1 w$ mem_out [0] $end
-$var wire 1 x$ mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 w$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 4% D $end
-$var supply1 1 B2 VPWR $end
-$var supply0 1 C2 VGND $end
-$var supply1 1 D2 VPB $end
-$var supply0 1 E2 VNB $end
-
-$scope module base $end
-$var wire 1 w$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 4% D $end
-$var wire 1 F2 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 x$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 w$ D $end
-$var supply1 1 G2 VPWR $end
-$var supply0 1 H2 VGND $end
-$var supply1 1 I2 VPB $end
-$var supply0 1 J2 VNB $end
-
-$scope module base $end
-$var wire 1 x$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 w$ D $end
-$var wire 1 K2 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_11__10 $end
-$var wire 1 8% X $end
-$var wire 1 x$ A $end
-$var supply1 1 L2 VPWR $end
-$var supply0 1 M2 VGND $end
-$var supply1 1 N2 VPB $end
-$var supply0 1 O2 VNB $end
-
-$scope module base $end
-$var wire 1 8% X $end
-$var wire 1 x$ A $end
-$var wire 1 P2 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_bottom_track_15 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 8% ccff_head [0] $end
-$var wire 1 9% ccff_tail [0] $end
-$var wire 1 y$ mem_out [0] $end
-$var wire 1 z$ mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 y$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 8% D $end
-$var supply1 1 Q2 VPWR $end
-$var supply0 1 R2 VGND $end
-$var supply1 1 S2 VPB $end
-$var supply0 1 T2 VNB $end
-
-$scope module base $end
-$var wire 1 y$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 8% D $end
-$var wire 1 U2 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 z$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 y$ D $end
-$var supply1 1 V2 VPWR $end
-$var supply0 1 W2 VGND $end
-$var supply1 1 X2 VPB $end
-$var supply0 1 Y2 VNB $end
-
-$scope module base $end
-$var wire 1 z$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 y$ D $end
-$var wire 1 Z2 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_12__11 $end
-$var wire 1 9% X $end
-$var wire 1 z$ A $end
-$var supply1 1 [2 VPWR $end
-$var supply0 1 \2 VGND $end
-$var supply1 1 ]2 VPB $end
-$var supply0 1 ^2 VNB $end
-
-$scope module base $end
-$var wire 1 9% X $end
-$var wire 1 z$ A $end
-$var wire 1 _2 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_bottom_track_17 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 9% ccff_head [0] $end
-$var wire 1 :% ccff_tail [0] $end
-$var wire 1 {$ mem_out [0] $end
-$var wire 1 |$ mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 {$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 9% D $end
-$var supply1 1 `2 VPWR $end
-$var supply0 1 a2 VGND $end
-$var supply1 1 b2 VPB $end
-$var supply0 1 c2 VNB $end
-
-$scope module base $end
-$var wire 1 {$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 9% D $end
-$var wire 1 d2 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 |$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 {$ D $end
-$var supply1 1 e2 VPWR $end
-$var supply0 1 f2 VGND $end
-$var supply1 1 g2 VPB $end
-$var supply0 1 h2 VNB $end
-
-$scope module base $end
-$var wire 1 |$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 {$ D $end
-$var wire 1 i2 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_13__12 $end
-$var wire 1 :% X $end
-$var wire 1 |$ A $end
-$var supply1 1 j2 VPWR $end
-$var supply0 1 k2 VGND $end
-$var supply1 1 l2 VPB $end
-$var supply0 1 m2 VNB $end
-
-$scope module base $end
-$var wire 1 :% X $end
-$var wire 1 |$ A $end
-$var wire 1 n2 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_bottom_track_19 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 :% ccff_head [0] $end
-$var wire 1 ;% ccff_tail [0] $end
-$var wire 1 }$ mem_out [0] $end
-$var wire 1 ~$ mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 }$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 :% D $end
-$var supply1 1 o2 VPWR $end
-$var supply0 1 p2 VGND $end
-$var supply1 1 q2 VPB $end
-$var supply0 1 r2 VNB $end
-
-$scope module base $end
-$var wire 1 }$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 :% D $end
-$var wire 1 s2 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 ~$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 }$ D $end
-$var supply1 1 t2 VPWR $end
-$var supply0 1 u2 VGND $end
-$var supply1 1 v2 VPB $end
-$var supply0 1 w2 VNB $end
-
-$scope module base $end
-$var wire 1 ~$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 }$ D $end
-$var wire 1 x2 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_14__13 $end
-$var wire 1 ;% X $end
-$var wire 1 ~$ A $end
-$var supply1 1 y2 VPWR $end
-$var supply0 1 z2 VGND $end
-$var supply1 1 {2 VPB $end
-$var supply0 1 |2 VNB $end
-
-$scope module base $end
-$var wire 1 ;% X $end
-$var wire 1 ~$ A $end
-$var wire 1 }2 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_bottom_track_21 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 ;% ccff_head [0] $end
-$var wire 1 <% ccff_tail [0] $end
-$var wire 1 !% mem_out [0] $end
-$var wire 1 "% mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 !% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 ;% D $end
-$var supply1 1 ~2 VPWR $end
-$var supply0 1 !3 VGND $end
-$var supply1 1 "3 VPB $end
-$var supply0 1 #3 VNB $end
-
-$scope module base $end
-$var wire 1 !% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 ;% D $end
-$var wire 1 $3 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 "% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 !% D $end
-$var supply1 1 %3 VPWR $end
-$var supply0 1 &3 VGND $end
-$var supply1 1 '3 VPB $end
-$var supply0 1 (3 VNB $end
-
-$scope module base $end
-$var wire 1 "% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 !% D $end
-$var wire 1 )3 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_15__14 $end
-$var wire 1 <% X $end
-$var wire 1 "% A $end
-$var supply1 1 *3 VPWR $end
-$var supply0 1 +3 VGND $end
-$var supply1 1 ,3 VPB $end
-$var supply0 1 -3 VNB $end
-
-$scope module base $end
-$var wire 1 <% X $end
-$var wire 1 "% A $end
-$var wire 1 .3 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_bottom_track_23 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 <% ccff_head [0] $end
-$var wire 1 =% ccff_tail [0] $end
-$var wire 1 #% mem_out [0] $end
-$var wire 1 $% mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 #% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 <% D $end
-$var supply1 1 /3 VPWR $end
-$var supply0 1 03 VGND $end
-$var supply1 1 13 VPB $end
-$var supply0 1 23 VNB $end
-
-$scope module base $end
-$var wire 1 #% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 <% D $end
-$var wire 1 33 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 $% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 #% D $end
-$var supply1 1 43 VPWR $end
-$var supply0 1 53 VGND $end
-$var supply1 1 63 VPB $end
-$var supply0 1 73 VNB $end
-
-$scope module base $end
-$var wire 1 $% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 #% D $end
-$var wire 1 83 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_16__15 $end
-$var wire 1 =% X $end
-$var wire 1 $% A $end
-$var supply1 1 93 VPWR $end
-$var supply0 1 :3 VGND $end
-$var supply1 1 ;3 VPB $end
-$var supply0 1 <3 VNB $end
-
-$scope module base $end
-$var wire 1 =% X $end
-$var wire 1 $% A $end
-$var wire 1 =3 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_bottom_track_27 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 F% ccff_head [0] $end
-$var wire 1 >% ccff_tail [0] $end
-$var wire 1 %% mem_out [0] $end
-$var wire 1 &% mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 %% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 F% D $end
-$var supply1 1 >3 VPWR $end
-$var supply0 1 ?3 VGND $end
-$var supply1 1 @3 VPB $end
-$var supply0 1 A3 VNB $end
-
-$scope module base $end
-$var wire 1 %% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 F% D $end
-$var wire 1 B3 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 &% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 %% D $end
-$var supply1 1 C3 VPWR $end
-$var supply0 1 D3 VGND $end
-$var supply1 1 E3 VPB $end
-$var supply0 1 F3 VNB $end
-
-$scope module base $end
-$var wire 1 &% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 %% D $end
-$var wire 1 G3 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_17__16 $end
-$var wire 1 >% X $end
-$var wire 1 &% A $end
-$var supply1 1 H3 VPWR $end
-$var supply0 1 I3 VGND $end
-$var supply1 1 J3 VPB $end
-$var supply0 1 K3 VNB $end
-
-$scope module base $end
-$var wire 1 >% X $end
-$var wire 1 &% A $end
-$var wire 1 L3 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_bottom_track_29 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 >% ccff_head [0] $end
-$var wire 1 ?% ccff_tail [0] $end
-$var wire 1 '% mem_out [0] $end
-$var wire 1 (% mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 '% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 >% D $end
-$var supply1 1 M3 VPWR $end
-$var supply0 1 N3 VGND $end
-$var supply1 1 O3 VPB $end
-$var supply0 1 P3 VNB $end
-
-$scope module base $end
-$var wire 1 '% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 >% D $end
-$var wire 1 Q3 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 (% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 '% D $end
-$var supply1 1 R3 VPWR $end
-$var supply0 1 S3 VGND $end
-$var supply1 1 T3 VPB $end
-$var supply0 1 U3 VNB $end
-
-$scope module base $end
-$var wire 1 (% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 '% D $end
-$var wire 1 V3 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_18__17 $end
-$var wire 1 ?% X $end
-$var wire 1 (% A $end
-$var supply1 1 W3 VPWR $end
-$var supply0 1 X3 VGND $end
-$var supply1 1 Y3 VPB $end
-$var supply0 1 Z3 VNB $end
-
-$scope module base $end
-$var wire 1 ?% X $end
-$var wire 1 (% A $end
-$var wire 1 [3 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_left_track_11 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 G% ccff_head [0] $end
-$var wire 1 *% ccff_tail [0] $end
-$var wire 1 Y$ mem_out [0] $end
-$var wire 1 Z$ mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 Y$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 G% D $end
-$var supply1 1 \3 VPWR $end
-$var supply0 1 ]3 VGND $end
-$var supply1 1 ^3 VPB $end
-$var supply0 1 _3 VNB $end
-
-$scope module base $end
-$var wire 1 Y$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 G% D $end
-$var wire 1 `3 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 Z$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 Y$ D $end
-$var supply1 1 a3 VPWR $end
-$var supply0 1 b3 VGND $end
-$var supply1 1 c3 VPB $end
-$var supply0 1 d3 VNB $end
-
-$scope module base $end
-$var wire 1 Z$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 Y$ D $end
-$var wire 1 e3 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_19__18 $end
-$var wire 1 *% X $end
-$var wire 1 Z$ A $end
-$var supply1 1 f3 VPWR $end
-$var supply0 1 g3 VGND $end
-$var supply1 1 h3 VPB $end
-$var supply0 1 i3 VNB $end
-
-$scope module base $end
-$var wire 1 *% X $end
-$var wire 1 Z$ A $end
-$var wire 1 j3 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_left_track_13 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 *% ccff_head [0] $end
-$var wire 1 +% ccff_tail [0] $end
-$var wire 1 [$ mem_out [0] $end
-$var wire 1 \$ mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 [$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 *% D $end
-$var supply1 1 k3 VPWR $end
-$var supply0 1 l3 VGND $end
-$var supply1 1 m3 VPB $end
-$var supply0 1 n3 VNB $end
-
-$scope module base $end
-$var wire 1 [$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 *% D $end
-$var wire 1 o3 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 \$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 [$ D $end
-$var supply1 1 p3 VPWR $end
-$var supply0 1 q3 VGND $end
-$var supply1 1 r3 VPB $end
-$var supply0 1 s3 VNB $end
-
-$scope module base $end
-$var wire 1 \$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 [$ D $end
-$var wire 1 t3 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_20__19 $end
-$var wire 1 +% X $end
-$var wire 1 \$ A $end
-$var supply1 1 u3 VPWR $end
-$var supply0 1 v3 VGND $end
-$var supply1 1 w3 VPB $end
-$var supply0 1 x3 VNB $end
-
-$scope module base $end
-$var wire 1 +% X $end
-$var wire 1 \$ A $end
-$var wire 1 y3 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_left_track_15 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 +% ccff_head [0] $end
-$var wire 1 ,% ccff_tail [0] $end
-$var wire 1 ]$ mem_out [0] $end
-$var wire 1 ^$ mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 ]$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 +% D $end
-$var supply1 1 z3 VPWR $end
-$var supply0 1 {3 VGND $end
-$var supply1 1 |3 VPB $end
-$var supply0 1 }3 VNB $end
-
-$scope module base $end
-$var wire 1 ]$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 +% D $end
-$var wire 1 ~3 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 ^$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 ]$ D $end
-$var supply1 1 !4 VPWR $end
-$var supply0 1 "4 VGND $end
-$var supply1 1 #4 VPB $end
-$var supply0 1 $4 VNB $end
-
-$scope module base $end
-$var wire 1 ^$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 ]$ D $end
-$var wire 1 %4 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_21__20 $end
-$var wire 1 ,% X $end
-$var wire 1 ^$ A $end
-$var supply1 1 &4 VPWR $end
-$var supply0 1 '4 VGND $end
-$var supply1 1 (4 VPB $end
-$var supply0 1 )4 VNB $end
-
-$scope module base $end
-$var wire 1 ,% X $end
-$var wire 1 ^$ A $end
-$var wire 1 *4 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_left_track_17 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 ,% ccff_head [0] $end
-$var wire 1 -% ccff_tail [0] $end
-$var wire 1 _$ mem_out [0] $end
-$var wire 1 `$ mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 _$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 ,% D $end
-$var supply1 1 +4 VPWR $end
-$var supply0 1 ,4 VGND $end
-$var supply1 1 -4 VPB $end
-$var supply0 1 .4 VNB $end
-
-$scope module base $end
-$var wire 1 _$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 ,% D $end
-$var wire 1 /4 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 `$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 _$ D $end
-$var supply1 1 04 VPWR $end
-$var supply0 1 14 VGND $end
-$var supply1 1 24 VPB $end
-$var supply0 1 34 VNB $end
-
-$scope module base $end
-$var wire 1 `$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 _$ D $end
-$var wire 1 44 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_22__21 $end
-$var wire 1 -% X $end
-$var wire 1 `$ A $end
-$var supply1 1 54 VPWR $end
-$var supply0 1 64 VGND $end
-$var supply1 1 74 VPB $end
-$var supply0 1 84 VNB $end
-
-$scope module base $end
-$var wire 1 -% X $end
-$var wire 1 `$ A $end
-$var wire 1 94 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_left_track_19 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 -% ccff_head [0] $end
-$var wire 1 .% ccff_tail [0] $end
-$var wire 1 a$ mem_out [0] $end
-$var wire 1 b$ mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 a$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 -% D $end
-$var supply1 1 :4 VPWR $end
-$var supply0 1 ;4 VGND $end
-$var supply1 1 <4 VPB $end
-$var supply0 1 =4 VNB $end
-
-$scope module base $end
-$var wire 1 a$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 -% D $end
-$var wire 1 >4 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 b$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 a$ D $end
-$var supply1 1 ?4 VPWR $end
-$var supply0 1 @4 VGND $end
-$var supply1 1 A4 VPB $end
-$var supply0 1 B4 VNB $end
-
-$scope module base $end
-$var wire 1 b$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 a$ D $end
-$var wire 1 C4 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_23__22 $end
-$var wire 1 .% X $end
-$var wire 1 b$ A $end
-$var supply1 1 D4 VPWR $end
-$var supply0 1 E4 VGND $end
-$var supply1 1 F4 VPB $end
-$var supply0 1 G4 VNB $end
-
-$scope module base $end
-$var wire 1 .% X $end
-$var wire 1 b$ A $end
-$var wire 1 H4 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_left_track_21 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 .% ccff_head [0] $end
-$var wire 1 /% ccff_tail [0] $end
-$var wire 1 c$ mem_out [0] $end
-$var wire 1 d$ mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 c$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 .% D $end
-$var supply1 1 I4 VPWR $end
-$var supply0 1 J4 VGND $end
-$var supply1 1 K4 VPB $end
-$var supply0 1 L4 VNB $end
-
-$scope module base $end
-$var wire 1 c$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 .% D $end
-$var wire 1 M4 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 d$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 c$ D $end
-$var supply1 1 N4 VPWR $end
-$var supply0 1 O4 VGND $end
-$var supply1 1 P4 VPB $end
-$var supply0 1 Q4 VNB $end
-
-$scope module base $end
-$var wire 1 d$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 c$ D $end
-$var wire 1 R4 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_24__23 $end
-$var wire 1 /% X $end
-$var wire 1 d$ A $end
-$var supply1 1 S4 VPWR $end
-$var supply0 1 T4 VGND $end
-$var supply1 1 U4 VPB $end
-$var supply0 1 V4 VNB $end
-
-$scope module base $end
-$var wire 1 /% X $end
-$var wire 1 d$ A $end
-$var wire 1 W4 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_left_track_23 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 /% ccff_head [0] $end
-$var wire 1 0% ccff_tail [0] $end
-$var wire 1 e$ mem_out [0] $end
-$var wire 1 f$ mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 e$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 /% D $end
-$var supply1 1 X4 VPWR $end
-$var supply0 1 Y4 VGND $end
-$var supply1 1 Z4 VPB $end
-$var supply0 1 [4 VNB $end
-
-$scope module base $end
-$var wire 1 e$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 /% D $end
-$var wire 1 \4 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 f$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 e$ D $end
-$var supply1 1 ]4 VPWR $end
-$var supply0 1 ^4 VGND $end
-$var supply1 1 _4 VPB $end
-$var supply0 1 `4 VNB $end
-
-$scope module base $end
-$var wire 1 f$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 e$ D $end
-$var wire 1 a4 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_25__24 $end
-$var wire 1 0% X $end
-$var wire 1 f$ A $end
-$var supply1 1 b4 VPWR $end
-$var supply0 1 c4 VGND $end
-$var supply1 1 d4 VPB $end
-$var supply0 1 e4 VNB $end
-
-$scope module base $end
-$var wire 1 0% X $end
-$var wire 1 f$ A $end
-$var wire 1 f4 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_left_track_27 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 H% ccff_head [0] $end
-$var wire 1 1% ccff_tail [0] $end
-$var wire 1 g$ mem_out [0] $end
-$var wire 1 h$ mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 g$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 H% D $end
-$var supply1 1 g4 VPWR $end
-$var supply0 1 h4 VGND $end
-$var supply1 1 i4 VPB $end
-$var supply0 1 j4 VNB $end
-
-$scope module base $end
-$var wire 1 g$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 H% D $end
-$var wire 1 k4 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 h$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 g$ D $end
-$var supply1 1 l4 VPWR $end
-$var supply0 1 m4 VGND $end
-$var supply1 1 n4 VPB $end
-$var supply0 1 o4 VNB $end
-
-$scope module base $end
-$var wire 1 h$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 g$ D $end
-$var wire 1 p4 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_26__25 $end
-$var wire 1 1% X $end
-$var wire 1 h$ A $end
-$var supply1 1 q4 VPWR $end
-$var supply0 1 r4 VGND $end
-$var supply1 1 s4 VPB $end
-$var supply0 1 t4 VNB $end
-
-$scope module base $end
-$var wire 1 1% X $end
-$var wire 1 h$ A $end
-$var wire 1 u4 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_left_track_29 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 1% ccff_head [0] $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 '% ccff_head [0] $end
 $var wire 1 2% ccff_tail [0] $end
-$var wire 1 i$ mem_out [0] $end
-$var wire 1 j$ mem_out [1] $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 i$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 1% D $end
-$var supply1 1 v4 VPWR $end
-$var supply0 1 w4 VGND $end
-$var supply1 1 x4 VPB $end
-$var supply0 1 y4 VNB $end
-
-$scope module base $end
-$var wire 1 i$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 1% D $end
-$var wire 1 z4 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 j$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 i$ D $end
-$var supply1 1 {4 VPWR $end
-$var supply0 1 |4 VGND $end
-$var supply1 1 }4 VPB $end
-$var supply0 1 ~4 VNB $end
-
-$scope module base $end
-$var wire 1 j$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 i$ D $end
-$var wire 1 !5 buf_Q $end
-$upscope $end
-$upscope $end
-
-$scope module FTB_27__26 $end
-$var wire 1 2% X $end
-$var wire 1 j$ A $end
-$var supply1 1 "5 VPWR $end
-$var supply0 1 #5 VGND $end
-$var supply1 1 $5 VPB $end
-$var supply0 1 %5 VNB $end
-
-$scope module base $end
-$var wire 1 2% X $end
-$var wire 1 j$ A $end
-$var wire 1 &5 buf0_out_X $end
-$upscope $end
-$upscope $end
-$upscope $end
-
-$scope module mem_left_track_31 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 2% ccff_head [0] $end
-$var wire 1 3% ccff_tail [0] $end
 $var wire 1 k$ mem_out [0] $end
 $var wire 1 l$ mem_out [1] $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
 $var wire 1 k$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 2% D $end
-$var supply1 1 '5 VPWR $end
-$var supply0 1 (5 VGND $end
-$var supply1 1 )5 VPB $end
-$var supply0 1 *5 VNB $end
+$var wire 1 S$ CLK $end
+$var wire 1 '% D $end
+$var supply1 1 '2 VPWR $end
+$var supply0 1 (2 VGND $end
+$var supply1 1 )2 VPB $end
+$var supply0 1 *2 VNB $end
 
 $scope module base $end
 $var wire 1 k$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 2% D $end
-$var wire 1 +5 buf_Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 '% D $end
+$var wire 1 +2 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
 $var wire 1 l$ Q $end
-$var wire 1 U$ CLK $end
+$var wire 1 S$ CLK $end
 $var wire 1 k$ D $end
-$var supply1 1 ,5 VPWR $end
-$var supply0 1 -5 VGND $end
-$var supply1 1 .5 VPB $end
-$var supply0 1 /5 VNB $end
+$var supply1 1 ,2 VPWR $end
+$var supply0 1 -2 VGND $end
+$var supply1 1 .2 VPB $end
+$var supply0 1 /2 VNB $end
 
 $scope module base $end
 $var wire 1 l$ Q $end
-$var wire 1 U$ CLK $end
+$var wire 1 S$ CLK $end
 $var wire 1 k$ D $end
-$var wire 1 05 buf_Q $end
+$var wire 1 02 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_10__9 $end
+$var wire 1 2% X $end
+$var wire 1 l$ A $end
+$var supply1 1 12 VPWR $end
+$var supply0 1 22 VGND $end
+$var supply1 1 32 VPB $end
+$var supply0 1 42 VNB $end
+
+$scope module base $end
+$var wire 1 2% X $end
+$var wire 1 l$ A $end
+$var wire 1 52 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_bottom_track_13 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 2% ccff_head [0] $end
+$var wire 1 6% ccff_tail [0] $end
+$var wire 1 u$ mem_out [0] $end
+$var wire 1 v$ mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 u$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 2% D $end
+$var supply1 1 62 VPWR $end
+$var supply0 1 72 VGND $end
+$var supply1 1 82 VPB $end
+$var supply0 1 92 VNB $end
+
+$scope module base $end
+$var wire 1 u$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 2% D $end
+$var wire 1 :2 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 v$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 u$ D $end
+$var supply1 1 ;2 VPWR $end
+$var supply0 1 <2 VGND $end
+$var supply1 1 =2 VPB $end
+$var supply0 1 >2 VNB $end
+
+$scope module base $end
+$var wire 1 v$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 u$ D $end
+$var wire 1 ?2 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_11__10 $end
+$var wire 1 6% X $end
+$var wire 1 v$ A $end
+$var supply1 1 @2 VPWR $end
+$var supply0 1 A2 VGND $end
+$var supply1 1 B2 VPB $end
+$var supply0 1 C2 VNB $end
+
+$scope module base $end
+$var wire 1 6% X $end
+$var wire 1 v$ A $end
+$var wire 1 D2 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_bottom_track_15 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 6% ccff_head [0] $end
+$var wire 1 7% ccff_tail [0] $end
+$var wire 1 w$ mem_out [0] $end
+$var wire 1 x$ mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 w$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 6% D $end
+$var supply1 1 E2 VPWR $end
+$var supply0 1 F2 VGND $end
+$var supply1 1 G2 VPB $end
+$var supply0 1 H2 VNB $end
+
+$scope module base $end
+$var wire 1 w$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 6% D $end
+$var wire 1 I2 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 x$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 w$ D $end
+$var supply1 1 J2 VPWR $end
+$var supply0 1 K2 VGND $end
+$var supply1 1 L2 VPB $end
+$var supply0 1 M2 VNB $end
+
+$scope module base $end
+$var wire 1 x$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 w$ D $end
+$var wire 1 N2 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_12__11 $end
+$var wire 1 7% X $end
+$var wire 1 x$ A $end
+$var supply1 1 O2 VPWR $end
+$var supply0 1 P2 VGND $end
+$var supply1 1 Q2 VPB $end
+$var supply0 1 R2 VNB $end
+
+$scope module base $end
+$var wire 1 7% X $end
+$var wire 1 x$ A $end
+$var wire 1 S2 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_bottom_track_17 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 7% ccff_head [0] $end
+$var wire 1 8% ccff_tail [0] $end
+$var wire 1 y$ mem_out [0] $end
+$var wire 1 z$ mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 y$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 7% D $end
+$var supply1 1 T2 VPWR $end
+$var supply0 1 U2 VGND $end
+$var supply1 1 V2 VPB $end
+$var supply0 1 W2 VNB $end
+
+$scope module base $end
+$var wire 1 y$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 7% D $end
+$var wire 1 X2 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 z$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 y$ D $end
+$var supply1 1 Y2 VPWR $end
+$var supply0 1 Z2 VGND $end
+$var supply1 1 [2 VPB $end
+$var supply0 1 \2 VNB $end
+
+$scope module base $end
+$var wire 1 z$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 y$ D $end
+$var wire 1 ]2 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_13__12 $end
+$var wire 1 8% X $end
+$var wire 1 z$ A $end
+$var supply1 1 ^2 VPWR $end
+$var supply0 1 _2 VGND $end
+$var supply1 1 `2 VPB $end
+$var supply0 1 a2 VNB $end
+
+$scope module base $end
+$var wire 1 8% X $end
+$var wire 1 z$ A $end
+$var wire 1 b2 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_bottom_track_19 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 8% ccff_head [0] $end
+$var wire 1 9% ccff_tail [0] $end
+$var wire 1 {$ mem_out [0] $end
+$var wire 1 |$ mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 {$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 8% D $end
+$var supply1 1 c2 VPWR $end
+$var supply0 1 d2 VGND $end
+$var supply1 1 e2 VPB $end
+$var supply0 1 f2 VNB $end
+
+$scope module base $end
+$var wire 1 {$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 8% D $end
+$var wire 1 g2 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 |$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 {$ D $end
+$var supply1 1 h2 VPWR $end
+$var supply0 1 i2 VGND $end
+$var supply1 1 j2 VPB $end
+$var supply0 1 k2 VNB $end
+
+$scope module base $end
+$var wire 1 |$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 {$ D $end
+$var wire 1 l2 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_14__13 $end
+$var wire 1 9% X $end
+$var wire 1 |$ A $end
+$var supply1 1 m2 VPWR $end
+$var supply0 1 n2 VGND $end
+$var supply1 1 o2 VPB $end
+$var supply0 1 p2 VNB $end
+
+$scope module base $end
+$var wire 1 9% X $end
+$var wire 1 |$ A $end
+$var wire 1 q2 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_bottom_track_21 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 9% ccff_head [0] $end
+$var wire 1 :% ccff_tail [0] $end
+$var wire 1 }$ mem_out [0] $end
+$var wire 1 ~$ mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 }$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 9% D $end
+$var supply1 1 r2 VPWR $end
+$var supply0 1 s2 VGND $end
+$var supply1 1 t2 VPB $end
+$var supply0 1 u2 VNB $end
+
+$scope module base $end
+$var wire 1 }$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 9% D $end
+$var wire 1 v2 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 ~$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 }$ D $end
+$var supply1 1 w2 VPWR $end
+$var supply0 1 x2 VGND $end
+$var supply1 1 y2 VPB $end
+$var supply0 1 z2 VNB $end
+
+$scope module base $end
+$var wire 1 ~$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 }$ D $end
+$var wire 1 {2 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_15__14 $end
+$var wire 1 :% X $end
+$var wire 1 ~$ A $end
+$var supply1 1 |2 VPWR $end
+$var supply0 1 }2 VGND $end
+$var supply1 1 ~2 VPB $end
+$var supply0 1 !3 VNB $end
+
+$scope module base $end
+$var wire 1 :% X $end
+$var wire 1 ~$ A $end
+$var wire 1 "3 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_bottom_track_23 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 :% ccff_head [0] $end
+$var wire 1 ;% ccff_tail [0] $end
+$var wire 1 !% mem_out [0] $end
+$var wire 1 "% mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 !% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 :% D $end
+$var supply1 1 #3 VPWR $end
+$var supply0 1 $3 VGND $end
+$var supply1 1 %3 VPB $end
+$var supply0 1 &3 VNB $end
+
+$scope module base $end
+$var wire 1 !% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 :% D $end
+$var wire 1 '3 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 "% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 !% D $end
+$var supply1 1 (3 VPWR $end
+$var supply0 1 )3 VGND $end
+$var supply1 1 *3 VPB $end
+$var supply0 1 +3 VNB $end
+
+$scope module base $end
+$var wire 1 "% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 !% D $end
+$var wire 1 ,3 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_16__15 $end
+$var wire 1 ;% X $end
+$var wire 1 "% A $end
+$var supply1 1 -3 VPWR $end
+$var supply0 1 .3 VGND $end
+$var supply1 1 /3 VPB $end
+$var supply0 1 03 VNB $end
+
+$scope module base $end
+$var wire 1 ;% X $end
+$var wire 1 "% A $end
+$var wire 1 13 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_bottom_track_27 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 D% ccff_head [0] $end
+$var wire 1 <% ccff_tail [0] $end
+$var wire 1 #% mem_out [0] $end
+$var wire 1 $% mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 #% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 D% D $end
+$var supply1 1 23 VPWR $end
+$var supply0 1 33 VGND $end
+$var supply1 1 43 VPB $end
+$var supply0 1 53 VNB $end
+
+$scope module base $end
+$var wire 1 #% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 D% D $end
+$var wire 1 63 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 $% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 #% D $end
+$var supply1 1 73 VPWR $end
+$var supply0 1 83 VGND $end
+$var supply1 1 93 VPB $end
+$var supply0 1 :3 VNB $end
+
+$scope module base $end
+$var wire 1 $% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 #% D $end
+$var wire 1 ;3 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_17__16 $end
+$var wire 1 <% X $end
+$var wire 1 $% A $end
+$var supply1 1 <3 VPWR $end
+$var supply0 1 =3 VGND $end
+$var supply1 1 >3 VPB $end
+$var supply0 1 ?3 VNB $end
+
+$scope module base $end
+$var wire 1 <% X $end
+$var wire 1 $% A $end
+$var wire 1 @3 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_bottom_track_29 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 <% ccff_head [0] $end
+$var wire 1 =% ccff_tail [0] $end
+$var wire 1 %% mem_out [0] $end
+$var wire 1 &% mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 %% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 <% D $end
+$var supply1 1 A3 VPWR $end
+$var supply0 1 B3 VGND $end
+$var supply1 1 C3 VPB $end
+$var supply0 1 D3 VNB $end
+
+$scope module base $end
+$var wire 1 %% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 <% D $end
+$var wire 1 E3 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 &% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 %% D $end
+$var supply1 1 F3 VPWR $end
+$var supply0 1 G3 VGND $end
+$var supply1 1 H3 VPB $end
+$var supply0 1 I3 VNB $end
+
+$scope module base $end
+$var wire 1 &% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 %% D $end
+$var wire 1 J3 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_18__17 $end
+$var wire 1 =% X $end
+$var wire 1 &% A $end
+$var supply1 1 K3 VPWR $end
+$var supply0 1 L3 VGND $end
+$var supply1 1 M3 VPB $end
+$var supply0 1 N3 VNB $end
+
+$scope module base $end
+$var wire 1 =% X $end
+$var wire 1 &% A $end
+$var wire 1 O3 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_left_track_11 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 E% ccff_head [0] $end
+$var wire 1 (% ccff_tail [0] $end
+$var wire 1 W$ mem_out [0] $end
+$var wire 1 X$ mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 W$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 E% D $end
+$var supply1 1 P3 VPWR $end
+$var supply0 1 Q3 VGND $end
+$var supply1 1 R3 VPB $end
+$var supply0 1 S3 VNB $end
+
+$scope module base $end
+$var wire 1 W$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 E% D $end
+$var wire 1 T3 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 X$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 W$ D $end
+$var supply1 1 U3 VPWR $end
+$var supply0 1 V3 VGND $end
+$var supply1 1 W3 VPB $end
+$var supply0 1 X3 VNB $end
+
+$scope module base $end
+$var wire 1 X$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 W$ D $end
+$var wire 1 Y3 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_19__18 $end
+$var wire 1 (% X $end
+$var wire 1 X$ A $end
+$var supply1 1 Z3 VPWR $end
+$var supply0 1 [3 VGND $end
+$var supply1 1 \3 VPB $end
+$var supply0 1 ]3 VNB $end
+
+$scope module base $end
+$var wire 1 (% X $end
+$var wire 1 X$ A $end
+$var wire 1 ^3 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_left_track_13 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 (% ccff_head [0] $end
+$var wire 1 )% ccff_tail [0] $end
+$var wire 1 Y$ mem_out [0] $end
+$var wire 1 Z$ mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 Y$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 (% D $end
+$var supply1 1 _3 VPWR $end
+$var supply0 1 `3 VGND $end
+$var supply1 1 a3 VPB $end
+$var supply0 1 b3 VNB $end
+
+$scope module base $end
+$var wire 1 Y$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 (% D $end
+$var wire 1 c3 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 Z$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 Y$ D $end
+$var supply1 1 d3 VPWR $end
+$var supply0 1 e3 VGND $end
+$var supply1 1 f3 VPB $end
+$var supply0 1 g3 VNB $end
+
+$scope module base $end
+$var wire 1 Z$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 Y$ D $end
+$var wire 1 h3 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_20__19 $end
+$var wire 1 )% X $end
+$var wire 1 Z$ A $end
+$var supply1 1 i3 VPWR $end
+$var supply0 1 j3 VGND $end
+$var supply1 1 k3 VPB $end
+$var supply0 1 l3 VNB $end
+
+$scope module base $end
+$var wire 1 )% X $end
+$var wire 1 Z$ A $end
+$var wire 1 m3 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_left_track_15 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 )% ccff_head [0] $end
+$var wire 1 *% ccff_tail [0] $end
+$var wire 1 [$ mem_out [0] $end
+$var wire 1 \$ mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 [$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 )% D $end
+$var supply1 1 n3 VPWR $end
+$var supply0 1 o3 VGND $end
+$var supply1 1 p3 VPB $end
+$var supply0 1 q3 VNB $end
+
+$scope module base $end
+$var wire 1 [$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 )% D $end
+$var wire 1 r3 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 \$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 [$ D $end
+$var supply1 1 s3 VPWR $end
+$var supply0 1 t3 VGND $end
+$var supply1 1 u3 VPB $end
+$var supply0 1 v3 VNB $end
+
+$scope module base $end
+$var wire 1 \$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 [$ D $end
+$var wire 1 w3 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_21__20 $end
+$var wire 1 *% X $end
+$var wire 1 \$ A $end
+$var supply1 1 x3 VPWR $end
+$var supply0 1 y3 VGND $end
+$var supply1 1 z3 VPB $end
+$var supply0 1 {3 VNB $end
+
+$scope module base $end
+$var wire 1 *% X $end
+$var wire 1 \$ A $end
+$var wire 1 |3 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_left_track_17 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 *% ccff_head [0] $end
+$var wire 1 +% ccff_tail [0] $end
+$var wire 1 ]$ mem_out [0] $end
+$var wire 1 ^$ mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 ]$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 *% D $end
+$var supply1 1 }3 VPWR $end
+$var supply0 1 ~3 VGND $end
+$var supply1 1 !4 VPB $end
+$var supply0 1 "4 VNB $end
+
+$scope module base $end
+$var wire 1 ]$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 *% D $end
+$var wire 1 #4 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 ^$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 ]$ D $end
+$var supply1 1 $4 VPWR $end
+$var supply0 1 %4 VGND $end
+$var supply1 1 &4 VPB $end
+$var supply0 1 '4 VNB $end
+
+$scope module base $end
+$var wire 1 ^$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 ]$ D $end
+$var wire 1 (4 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_22__21 $end
+$var wire 1 +% X $end
+$var wire 1 ^$ A $end
+$var supply1 1 )4 VPWR $end
+$var supply0 1 *4 VGND $end
+$var supply1 1 +4 VPB $end
+$var supply0 1 ,4 VNB $end
+
+$scope module base $end
+$var wire 1 +% X $end
+$var wire 1 ^$ A $end
+$var wire 1 -4 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_left_track_19 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 +% ccff_head [0] $end
+$var wire 1 ,% ccff_tail [0] $end
+$var wire 1 _$ mem_out [0] $end
+$var wire 1 `$ mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 _$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 +% D $end
+$var supply1 1 .4 VPWR $end
+$var supply0 1 /4 VGND $end
+$var supply1 1 04 VPB $end
+$var supply0 1 14 VNB $end
+
+$scope module base $end
+$var wire 1 _$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 +% D $end
+$var wire 1 24 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 `$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 _$ D $end
+$var supply1 1 34 VPWR $end
+$var supply0 1 44 VGND $end
+$var supply1 1 54 VPB $end
+$var supply0 1 64 VNB $end
+
+$scope module base $end
+$var wire 1 `$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 _$ D $end
+$var wire 1 74 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_23__22 $end
+$var wire 1 ,% X $end
+$var wire 1 `$ A $end
+$var supply1 1 84 VPWR $end
+$var supply0 1 94 VGND $end
+$var supply1 1 :4 VPB $end
+$var supply0 1 ;4 VNB $end
+
+$scope module base $end
+$var wire 1 ,% X $end
+$var wire 1 `$ A $end
+$var wire 1 <4 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_left_track_21 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 ,% ccff_head [0] $end
+$var wire 1 -% ccff_tail [0] $end
+$var wire 1 a$ mem_out [0] $end
+$var wire 1 b$ mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 a$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 ,% D $end
+$var supply1 1 =4 VPWR $end
+$var supply0 1 >4 VGND $end
+$var supply1 1 ?4 VPB $end
+$var supply0 1 @4 VNB $end
+
+$scope module base $end
+$var wire 1 a$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 ,% D $end
+$var wire 1 A4 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 b$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 a$ D $end
+$var supply1 1 B4 VPWR $end
+$var supply0 1 C4 VGND $end
+$var supply1 1 D4 VPB $end
+$var supply0 1 E4 VNB $end
+
+$scope module base $end
+$var wire 1 b$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 a$ D $end
+$var wire 1 F4 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_24__23 $end
+$var wire 1 -% X $end
+$var wire 1 b$ A $end
+$var supply1 1 G4 VPWR $end
+$var supply0 1 H4 VGND $end
+$var supply1 1 I4 VPB $end
+$var supply0 1 J4 VNB $end
+
+$scope module base $end
+$var wire 1 -% X $end
+$var wire 1 b$ A $end
+$var wire 1 K4 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_left_track_23 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 -% ccff_head [0] $end
+$var wire 1 .% ccff_tail [0] $end
+$var wire 1 c$ mem_out [0] $end
+$var wire 1 d$ mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 c$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 -% D $end
+$var supply1 1 L4 VPWR $end
+$var supply0 1 M4 VGND $end
+$var supply1 1 N4 VPB $end
+$var supply0 1 O4 VNB $end
+
+$scope module base $end
+$var wire 1 c$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 -% D $end
+$var wire 1 P4 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 d$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 c$ D $end
+$var supply1 1 Q4 VPWR $end
+$var supply0 1 R4 VGND $end
+$var supply1 1 S4 VPB $end
+$var supply0 1 T4 VNB $end
+
+$scope module base $end
+$var wire 1 d$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 c$ D $end
+$var wire 1 U4 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_25__24 $end
+$var wire 1 .% X $end
+$var wire 1 d$ A $end
+$var supply1 1 V4 VPWR $end
+$var supply0 1 W4 VGND $end
+$var supply1 1 X4 VPB $end
+$var supply0 1 Y4 VNB $end
+
+$scope module base $end
+$var wire 1 .% X $end
+$var wire 1 d$ A $end
+$var wire 1 Z4 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_left_track_27 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 F% ccff_head [0] $end
+$var wire 1 /% ccff_tail [0] $end
+$var wire 1 e$ mem_out [0] $end
+$var wire 1 f$ mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 e$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 F% D $end
+$var supply1 1 [4 VPWR $end
+$var supply0 1 \4 VGND $end
+$var supply1 1 ]4 VPB $end
+$var supply0 1 ^4 VNB $end
+
+$scope module base $end
+$var wire 1 e$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 F% D $end
+$var wire 1 _4 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 f$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 e$ D $end
+$var supply1 1 `4 VPWR $end
+$var supply0 1 a4 VGND $end
+$var supply1 1 b4 VPB $end
+$var supply0 1 c4 VNB $end
+
+$scope module base $end
+$var wire 1 f$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 e$ D $end
+$var wire 1 d4 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_26__25 $end
+$var wire 1 /% X $end
+$var wire 1 f$ A $end
+$var supply1 1 e4 VPWR $end
+$var supply0 1 f4 VGND $end
+$var supply1 1 g4 VPB $end
+$var supply0 1 h4 VNB $end
+
+$scope module base $end
+$var wire 1 /% X $end
+$var wire 1 f$ A $end
+$var wire 1 i4 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_left_track_29 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 /% ccff_head [0] $end
+$var wire 1 0% ccff_tail [0] $end
+$var wire 1 g$ mem_out [0] $end
+$var wire 1 h$ mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 g$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 /% D $end
+$var supply1 1 j4 VPWR $end
+$var supply0 1 k4 VGND $end
+$var supply1 1 l4 VPB $end
+$var supply0 1 m4 VNB $end
+
+$scope module base $end
+$var wire 1 g$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 /% D $end
+$var wire 1 n4 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 h$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 g$ D $end
+$var supply1 1 o4 VPWR $end
+$var supply0 1 p4 VGND $end
+$var supply1 1 q4 VPB $end
+$var supply0 1 r4 VNB $end
+
+$scope module base $end
+$var wire 1 h$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 g$ D $end
+$var wire 1 s4 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module FTB_27__26 $end
+$var wire 1 0% X $end
+$var wire 1 h$ A $end
+$var supply1 1 t4 VPWR $end
+$var supply0 1 u4 VGND $end
+$var supply1 1 v4 VPB $end
+$var supply0 1 w4 VNB $end
+
+$scope module base $end
+$var wire 1 0% X $end
+$var wire 1 h$ A $end
+$var wire 1 x4 buf0_out_X $end
+$upscope $end
+$upscope $end
+$upscope $end
+
+$scope module mem_left_track_31 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 0% ccff_head [0] $end
+$var wire 1 1% ccff_tail [0] $end
+$var wire 1 i$ mem_out [0] $end
+$var wire 1 j$ mem_out [1] $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
+$var wire 1 i$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 0% D $end
+$var supply1 1 y4 VPWR $end
+$var supply0 1 z4 VGND $end
+$var supply1 1 {4 VPB $end
+$var supply0 1 |4 VNB $end
+
+$scope module base $end
+$var wire 1 i$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 0% D $end
+$var wire 1 }4 buf_Q $end
+$upscope $end
+$upscope $end
+
+$scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
+$var wire 1 j$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 i$ D $end
+$var supply1 1 ~4 VPWR $end
+$var supply0 1 !5 VGND $end
+$var supply1 1 "5 VPB $end
+$var supply0 1 #5 VNB $end
+
+$scope module base $end
+$var wire 1 j$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 i$ D $end
+$var wire 1 $5 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_28__27 $end
-$var wire 1 3% X $end
-$var wire 1 l$ A $end
-$var supply1 1 15 VPWR $end
-$var supply0 1 25 VGND $end
-$var supply1 1 35 VPB $end
-$var supply0 1 45 VNB $end
+$var wire 1 1% X $end
+$var wire 1 j$ A $end
+$var supply1 1 %5 VPWR $end
+$var supply0 1 &5 VGND $end
+$var supply1 1 '5 VPB $end
+$var supply0 1 (5 VNB $end
 
 $scope module base $end
-$var wire 1 3% X $end
-$var wire 1 l$ A $end
-$var wire 1 55 buf0_out_X $end
+$var wire 1 1% X $end
+$var wire 1 j$ A $end
+$var wire 1 )5 buf0_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
 
 $scope module mem_left_track_33 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 3% ccff_head [0] $end
-$var wire 1 5% ccff_tail [0] $end
-$var wire 1 o$ mem_out [0] $end
-$var wire 1 p$ mem_out [1] $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 1% ccff_head [0] $end
+$var wire 1 3% ccff_tail [0] $end
+$var wire 1 m$ mem_out [0] $end
+$var wire 1 n$ mem_out [1] $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 o$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 3% D $end
-$var supply1 1 65 VPWR $end
-$var supply0 1 75 VGND $end
-$var supply1 1 85 VPB $end
-$var supply0 1 95 VNB $end
+$var wire 1 m$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 1% D $end
+$var supply1 1 *5 VPWR $end
+$var supply0 1 +5 VGND $end
+$var supply1 1 ,5 VPB $end
+$var supply0 1 -5 VNB $end
 
 $scope module base $end
-$var wire 1 o$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 3% D $end
-$var wire 1 :5 buf_Q $end
+$var wire 1 m$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 1% D $end
+$var wire 1 .5 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 p$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 o$ D $end
-$var supply1 1 ;5 VPWR $end
-$var supply0 1 <5 VGND $end
-$var supply1 1 =5 VPB $end
-$var supply0 1 >5 VNB $end
+$var wire 1 n$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 m$ D $end
+$var supply1 1 /5 VPWR $end
+$var supply0 1 05 VGND $end
+$var supply1 1 15 VPB $end
+$var supply0 1 25 VNB $end
 
 $scope module base $end
-$var wire 1 p$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 o$ D $end
-$var wire 1 ?5 buf_Q $end
+$var wire 1 n$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 m$ D $end
+$var wire 1 35 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_29__28 $end
-$var wire 1 5% X $end
-$var wire 1 p$ A $end
-$var supply1 1 @5 VPWR $end
-$var supply0 1 A5 VGND $end
-$var supply1 1 B5 VPB $end
-$var supply0 1 C5 VNB $end
+$var wire 1 3% X $end
+$var wire 1 n$ A $end
+$var supply1 1 45 VPWR $end
+$var supply0 1 55 VGND $end
+$var supply1 1 65 VPB $end
+$var supply0 1 75 VNB $end
 
 $scope module base $end
-$var wire 1 5% X $end
-$var wire 1 p$ A $end
-$var wire 1 D5 buf0_out_X $end
+$var wire 1 3% X $end
+$var wire 1 n$ A $end
+$var wire 1 85 buf0_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
 
 $scope module mem_left_track_35 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 5% ccff_head [0] $end
-$var wire 1 6% ccff_tail [0] $end
-$var wire 1 q$ mem_out [0] $end
-$var wire 1 r$ mem_out [1] $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 3% ccff_head [0] $end
+$var wire 1 4% ccff_tail [0] $end
+$var wire 1 o$ mem_out [0] $end
+$var wire 1 p$ mem_out [1] $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 q$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 5% D $end
-$var supply1 1 E5 VPWR $end
-$var supply0 1 F5 VGND $end
-$var supply1 1 G5 VPB $end
-$var supply0 1 H5 VNB $end
+$var wire 1 o$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 3% D $end
+$var supply1 1 95 VPWR $end
+$var supply0 1 :5 VGND $end
+$var supply1 1 ;5 VPB $end
+$var supply0 1 <5 VNB $end
 
 $scope module base $end
-$var wire 1 q$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 5% D $end
-$var wire 1 I5 buf_Q $end
+$var wire 1 o$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 3% D $end
+$var wire 1 =5 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 r$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 q$ D $end
-$var supply1 1 J5 VPWR $end
-$var supply0 1 K5 VGND $end
-$var supply1 1 L5 VPB $end
-$var supply0 1 M5 VNB $end
+$var wire 1 p$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 o$ D $end
+$var supply1 1 >5 VPWR $end
+$var supply0 1 ?5 VGND $end
+$var supply1 1 @5 VPB $end
+$var supply0 1 A5 VNB $end
 
 $scope module base $end
-$var wire 1 r$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 q$ D $end
-$var wire 1 N5 buf_Q $end
+$var wire 1 p$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 o$ D $end
+$var wire 1 B5 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_30__29 $end
-$var wire 1 6% X $end
-$var wire 1 r$ A $end
-$var supply1 1 O5 VPWR $end
-$var supply0 1 P5 VGND $end
-$var supply1 1 Q5 VPB $end
-$var supply0 1 R5 VNB $end
+$var wire 1 4% X $end
+$var wire 1 p$ A $end
+$var supply1 1 C5 VPWR $end
+$var supply0 1 D5 VGND $end
+$var supply1 1 E5 VPB $end
+$var supply0 1 F5 VNB $end
 
 $scope module base $end
-$var wire 1 6% X $end
-$var wire 1 r$ A $end
-$var wire 1 S5 buf0_out_X $end
+$var wire 1 4% X $end
+$var wire 1 p$ A $end
+$var wire 1 G5 buf0_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
 
 $scope module mem_left_track_37 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 6% ccff_head [0] $end
-$var wire 1 7% ccff_tail [0] $end
-$var wire 1 s$ mem_out [0] $end
-$var wire 1 t$ mem_out [1] $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 4% ccff_head [0] $end
+$var wire 1 5% ccff_tail [0] $end
+$var wire 1 q$ mem_out [0] $end
+$var wire 1 r$ mem_out [1] $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 s$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 6% D $end
-$var supply1 1 T5 VPWR $end
-$var supply0 1 U5 VGND $end
-$var supply1 1 V5 VPB $end
-$var supply0 1 W5 VNB $end
+$var wire 1 q$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 4% D $end
+$var supply1 1 H5 VPWR $end
+$var supply0 1 I5 VGND $end
+$var supply1 1 J5 VPB $end
+$var supply0 1 K5 VNB $end
 
 $scope module base $end
-$var wire 1 s$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 6% D $end
-$var wire 1 X5 buf_Q $end
+$var wire 1 q$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 4% D $end
+$var wire 1 L5 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 t$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 s$ D $end
-$var supply1 1 Y5 VPWR $end
-$var supply0 1 Z5 VGND $end
-$var supply1 1 [5 VPB $end
-$var supply0 1 \5 VNB $end
+$var wire 1 r$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 q$ D $end
+$var supply1 1 M5 VPWR $end
+$var supply0 1 N5 VGND $end
+$var supply1 1 O5 VPB $end
+$var supply0 1 P5 VNB $end
 
 $scope module base $end
-$var wire 1 t$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 s$ D $end
-$var wire 1 ]5 buf_Q $end
+$var wire 1 r$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 q$ D $end
+$var wire 1 Q5 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_31__30 $end
-$var wire 1 7% X $end
-$var wire 1 t$ A $end
-$var supply1 1 ^5 VPWR $end
-$var supply0 1 _5 VGND $end
-$var supply1 1 `5 VPB $end
-$var supply0 1 a5 VNB $end
+$var wire 1 5% X $end
+$var wire 1 r$ A $end
+$var supply1 1 R5 VPWR $end
+$var supply0 1 S5 VGND $end
+$var supply1 1 T5 VPB $end
+$var supply0 1 U5 VNB $end
 
 $scope module base $end
-$var wire 1 7% X $end
-$var wire 1 t$ A $end
-$var wire 1 b5 buf0_out_X $end
+$var wire 1 5% X $end
+$var wire 1 r$ A $end
+$var wire 1 V5 buf0_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
 
 $scope module mem_left_track_39 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 7% ccff_head [0] $end
-$var wire 1 W& ccff_tail [0] $end
-$var wire 1 u$ mem_out [0] $end
-$var wire 1 v$ mem_out [1] $end
-$var wire 1 c5 copt_net_109 $end
-$var wire 1 d5 copt_net_105 $end
-$var wire 1 e5 copt_net_110 $end
-$var wire 1 f5 copt_net_106 $end
-$var wire 1 g5 copt_net_107 $end
-$var wire 1 h5 copt_net_108 $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 5% ccff_head [0] $end
+$var wire 1 V& ccff_tail [0] $end
+$var wire 1 s$ mem_out [0] $end
+$var wire 1 t$ mem_out [1] $end
+$var wire 1 W5 copt_net_107 $end
+$var wire 1 X5 copt_net_102 $end
+$var wire 1 Y5 copt_net_103 $end
+$var wire 1 Z5 copt_net_105 $end
+$var wire 1 [5 copt_net_104 $end
+$var wire 1 \5 copt_net_106 $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 u$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 7% D $end
-$var supply1 1 i5 VPWR $end
-$var supply0 1 j5 VGND $end
-$var supply1 1 k5 VPB $end
-$var supply0 1 l5 VNB $end
+$var wire 1 s$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 5% D $end
+$var supply1 1 ]5 VPWR $end
+$var supply0 1 ^5 VGND $end
+$var supply1 1 _5 VPB $end
+$var supply0 1 `5 VNB $end
 
 $scope module base $end
-$var wire 1 u$ Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 7% D $end
-$var wire 1 m5 buf_Q $end
+$var wire 1 s$ Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 5% D $end
+$var wire 1 a5 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 c5 Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 u$ D $end
-$var supply1 1 n5 VPWR $end
-$var supply0 1 o5 VGND $end
-$var supply1 1 p5 VPB $end
-$var supply0 1 q5 VNB $end
+$var wire 1 W5 Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 s$ D $end
+$var supply1 1 b5 VPWR $end
+$var supply0 1 c5 VGND $end
+$var supply1 1 d5 VPB $end
+$var supply0 1 e5 VNB $end
 
 $scope module base $end
-$var wire 1 c5 Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 u$ D $end
-$var wire 1 r5 buf_Q $end
+$var wire 1 W5 Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 s$ D $end
+$var wire 1 f5 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_32__31 $end
-$var wire 1 W& X $end
-$var wire 1 v$ A $end
-$var supply1 1 s5 VPWR $end
-$var supply0 1 t5 VGND $end
-$var supply1 1 u5 VPB $end
-$var supply0 1 v5 VNB $end
+$var wire 1 V& X $end
+$var wire 1 t$ A $end
+$var supply1 1 g5 VPWR $end
+$var supply0 1 h5 VGND $end
+$var supply1 1 i5 VPB $end
+$var supply0 1 j5 VNB $end
 
 $scope module base $end
-$var wire 1 W& X $end
-$var wire 1 v$ A $end
-$var wire 1 w5 buf0_out_X $end
+$var wire 1 V& X $end
+$var wire 1 t$ A $end
+$var wire 1 k5 buf0_out_X $end
+$upscope $end
+$upscope $end
+
+$scope module copt_h_inst_1268 $end
+$var wire 1 X5 X $end
+$var wire 1 W5 A $end
+$var supply1 1 l5 VPWR $end
+$var supply0 1 m5 VGND $end
+$var supply1 1 n5 VPB $end
+$var supply0 1 o5 VNB $end
+
+$scope module base $end
+$var wire 1 X5 X $end
+$var wire 1 W5 A $end
+$var wire 1 p5 buf0_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module copt_h_inst_1269 $end
-$var wire 1 d5 X $end
-$var wire 1 c5 A $end
-$var supply1 1 x5 VPWR $end
-$var supply0 1 y5 VGND $end
-$var supply1 1 z5 VPB $end
-$var supply0 1 {5 VNB $end
+$var wire 1 Y5 X $end
+$var wire 1 X5 A $end
+$var supply1 1 q5 VPWR $end
+$var supply0 1 r5 VGND $end
+$var supply1 1 s5 VPB $end
+$var supply0 1 t5 VNB $end
 
 $scope module base $end
-$var wire 1 d5 X $end
-$var wire 1 c5 A $end
-$var wire 1 |5 buf0_out_X $end
+$var wire 1 Y5 X $end
+$var wire 1 X5 A $end
+$var wire 1 u5 buf0_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module copt_h_inst_1270 $end
-$var wire 1 f5 X $end
-$var wire 1 e5 A $end
-$var supply1 1 }5 VPWR $end
-$var supply0 1 ~5 VGND $end
-$var supply1 1 !6 VPB $end
-$var supply0 1 "6 VNB $end
+$var wire 1 [5 X $end
+$var wire 1 Z5 A $end
+$var supply1 1 v5 VPWR $end
+$var supply0 1 w5 VGND $end
+$var supply1 1 x5 VPB $end
+$var supply0 1 y5 VNB $end
 
 $scope module base $end
-$var wire 1 f5 X $end
-$var wire 1 e5 A $end
-$var wire 1 #6 buf0_out_X $end
+$var wire 1 [5 X $end
+$var wire 1 Z5 A $end
+$var wire 1 z5 buf0_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module copt_h_inst_1271 $end
-$var wire 1 g5 X $end
-$var wire 1 f5 A $end
-$var supply1 1 $6 VPWR $end
-$var supply0 1 %6 VGND $end
-$var supply1 1 &6 VPB $end
-$var supply0 1 '6 VNB $end
+$var wire 1 Z5 X $end
+$var wire 1 Y5 A $end
+$var supply1 1 {5 VPWR $end
+$var supply0 1 |5 VGND $end
+$var supply1 1 }5 VPB $end
+$var supply0 1 ~5 VNB $end
 
 $scope module base $end
-$var wire 1 g5 X $end
-$var wire 1 f5 A $end
-$var wire 1 (6 buf0_out_X $end
+$var wire 1 Z5 X $end
+$var wire 1 Y5 A $end
+$var wire 1 !6 buf0_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module copt_h_inst_1272 $end
-$var wire 1 h5 X $end
-$var wire 1 g5 A $end
-$var supply1 1 )6 VPWR $end
-$var supply0 1 *6 VGND $end
-$var supply1 1 +6 VPB $end
-$var supply0 1 ,6 VNB $end
+$var wire 1 \5 X $end
+$var wire 1 [5 A $end
+$var supply1 1 "6 VPWR $end
+$var supply0 1 #6 VGND $end
+$var supply1 1 $6 VPB $end
+$var supply0 1 %6 VNB $end
 
 $scope module base $end
-$var wire 1 h5 X $end
-$var wire 1 g5 A $end
-$var wire 1 -6 buf0_out_X $end
+$var wire 1 \5 X $end
+$var wire 1 [5 A $end
+$var wire 1 &6 buf0_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module copt_h_inst_1273 $end
-$var wire 1 v$ X $end
-$var wire 1 h5 A $end
-$var supply1 1 .6 VPWR $end
-$var supply0 1 /6 VGND $end
-$var supply1 1 06 VPB $end
-$var supply0 1 16 VNB $end
+$var wire 1 t$ X $end
+$var wire 1 \5 A $end
+$var supply1 1 '6 VPWR $end
+$var supply0 1 (6 VGND $end
+$var supply1 1 )6 VPB $end
+$var supply0 1 *6 VNB $end
 
 $scope module base $end
-$var wire 1 v$ X $end
-$var wire 1 h5 A $end
-$var wire 1 26 buf0_out_X $end
-$upscope $end
-$upscope $end
-
-$scope module copt_h_inst_1274 $end
-$var wire 1 e5 X $end
-$var wire 1 d5 A $end
-$var supply1 1 36 VPWR $end
-$var supply0 1 46 VGND $end
-$var supply1 1 56 VPB $end
-$var supply0 1 66 VNB $end
-
-$scope module base $end
-$var wire 1 e5 X $end
-$var wire 1 d5 A $end
-$var wire 1 76 buf0_out_X $end
+$var wire 1 t$ X $end
+$var wire 1 \5 A $end
+$var wire 1 +6 buf0_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -5955,101 +5923,101 @@ $scope module mux_bottom_track_25 $end
 $var wire 1 _# in [0] $end
 $var wire 1 g# in [1] $end
 $var wire 1 u# in [2] $end
-$var wire 1 @% sram [0] $end
-$var wire 1 A% sram [1] $end
-$var wire 1 X& sram_inv [0] $end
-$var wire 1 Y& sram_inv [1] $end
+$var wire 1 >% sram [0] $end
+$var wire 1 ?% sram [1] $end
+$var wire 1 W& sram_inv [0] $end
+$var wire 1 X& sram_inv [1] $end
 $var wire 1 4$ out [0] $end
-$var wire 1 '& p0 $end
-$var wire 1 86 sky130_fd_sc_hd__mux2_1_0_X [0] $end
-$var wire 1 96 sky130_fd_sc_hd__mux2_1_1_X [0] $end
-$var wire 1 :6 sky130_fd_sc_hd__mux2_1_2_X [0] $end
-$var wire 1 ;6 BUF_net_90 $end
+$var wire 1 j% p0 $end
+$var wire 1 ,6 sky130_fd_sc_hd__mux2_1_0_X [0] $end
+$var wire 1 -6 sky130_fd_sc_hd__mux2_1_1_X [0] $end
+$var wire 1 .6 sky130_fd_sc_hd__mux2_1_2_X [0] $end
+$var wire 1 /6 BUF_net_86 $end
 
 $scope module mux_l1_in_0_ $end
-$var wire 1 86 X $end
+$var wire 1 ,6 X $end
 $var wire 1 g# A0 $end
 $var wire 1 _# A1 $end
-$var wire 1 @% S $end
-$var supply1 1 <6 VPWR $end
-$var supply0 1 =6 VGND $end
-$var supply1 1 >6 VPB $end
-$var supply0 1 ?6 VNB $end
+$var wire 1 >% S $end
+$var supply1 1 06 VPWR $end
+$var supply0 1 16 VGND $end
+$var supply1 1 26 VPB $end
+$var supply0 1 36 VNB $end
 
 $scope module base $end
-$var wire 1 86 X $end
+$var wire 1 ,6 X $end
 $var wire 1 g# A0 $end
 $var wire 1 _# A1 $end
-$var wire 1 @% S $end
-$var wire 1 @6 mux_2to10_out_X $end
+$var wire 1 >% S $end
+$var wire 1 46 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l1_in_1_ $end
-$var wire 1 96 X $end
-$var wire 1 '& A0 $end
+$var wire 1 -6 X $end
+$var wire 1 j% A0 $end
 $var wire 1 u# A1 $end
-$var wire 1 @% S $end
-$var supply1 1 A6 VPWR $end
-$var supply0 1 B6 VGND $end
-$var supply1 1 C6 VPB $end
-$var supply0 1 D6 VNB $end
+$var wire 1 >% S $end
+$var supply1 1 56 VPWR $end
+$var supply0 1 66 VGND $end
+$var supply1 1 76 VPB $end
+$var supply0 1 86 VNB $end
 
 $scope module base $end
-$var wire 1 96 X $end
-$var wire 1 '& A0 $end
+$var wire 1 -6 X $end
+$var wire 1 j% A0 $end
 $var wire 1 u# A1 $end
-$var wire 1 @% S $end
-$var wire 1 E6 mux_2to10_out_X $end
+$var wire 1 >% S $end
+$var wire 1 96 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
-$var wire 1 :6 X $end
-$var wire 1 96 A0 $end
-$var wire 1 86 A1 $end
-$var wire 1 A% S $end
-$var supply1 1 F6 VPWR $end
-$var supply0 1 G6 VGND $end
-$var supply1 1 H6 VPB $end
-$var supply0 1 I6 VNB $end
+$var wire 1 .6 X $end
+$var wire 1 -6 A0 $end
+$var wire 1 ,6 A1 $end
+$var wire 1 ?% S $end
+$var supply1 1 :6 VPWR $end
+$var supply0 1 ;6 VGND $end
+$var supply1 1 <6 VPB $end
+$var supply0 1 =6 VNB $end
 
 $scope module base $end
-$var wire 1 :6 X $end
-$var wire 1 96 A0 $end
-$var wire 1 86 A1 $end
-$var wire 1 A% S $end
-$var wire 1 J6 mux_2to10_out_X $end
+$var wire 1 .6 X $end
+$var wire 1 -6 A0 $end
+$var wire 1 ,6 A1 $end
+$var wire 1 ?% S $end
+$var wire 1 >6 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_89 $end
+$scope module BINV_R_85 $end
 $var wire 1 4$ Y $end
-$var wire 1 ;6 A $end
-$var supply1 1 K6 VPWR $end
-$var supply0 1 L6 VGND $end
-$var supply1 1 M6 VPB $end
-$var supply0 1 N6 VNB $end
+$var wire 1 /6 A $end
+$var supply1 1 ?6 VPWR $end
+$var supply0 1 @6 VGND $end
+$var supply1 1 A6 VPB $end
+$var supply0 1 B6 VNB $end
 
 $scope module base $end
 $var wire 1 4$ Y $end
-$var wire 1 ;6 A $end
-$var wire 1 O6 not0_out_Y $end
+$var wire 1 /6 A $end
+$var wire 1 C6 not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_90 $end
-$var wire 1 ;6 Y $end
-$var wire 1 :6 A $end
-$var supply1 1 P6 VPWR $end
-$var supply0 1 Q6 VGND $end
-$var supply1 1 R6 VPB $end
-$var supply0 1 S6 VNB $end
+$scope module BINV_R_86 $end
+$var wire 1 /6 Y $end
+$var wire 1 .6 A $end
+$var supply1 1 D6 VPWR $end
+$var supply0 1 E6 VGND $end
+$var supply1 1 F6 VPB $end
+$var supply0 1 G6 VNB $end
 
 $scope module base $end
-$var wire 1 ;6 Y $end
-$var wire 1 :6 A $end
-$var wire 1 T6 not0_out_Y $end
+$var wire 1 /6 Y $end
+$var wire 1 .6 A $end
+$var wire 1 H6 not0_out_Y $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -6058,101 +6026,101 @@ $scope module mux_left_track_9 $end
 $var wire 1 N# in [0] $end
 $var wire 1 |# in [1] $end
 $var wire 1 &$ in [2] $end
-$var wire 1 B% sram [0] $end
-$var wire 1 C% sram [1] $end
-$var wire 1 Z& sram_inv [0] $end
-$var wire 1 [& sram_inv [1] $end
+$var wire 1 @% sram [0] $end
+$var wire 1 A% sram [1] $end
+$var wire 1 Y& sram_inv [0] $end
+$var wire 1 Z& sram_inv [1] $end
 $var wire 1 @$ out [0] $end
-$var wire 1 <& p0 $end
-$var wire 1 U6 sky130_fd_sc_hd__mux2_1_0_X [0] $end
-$var wire 1 V6 sky130_fd_sc_hd__mux2_1_1_X [0] $end
-$var wire 1 W6 sky130_fd_sc_hd__mux2_1_2_X [0] $end
-$var wire 1 X6 BUF_net_92 $end
+$var wire 1 r% p0 $end
+$var wire 1 I6 sky130_fd_sc_hd__mux2_1_0_X [0] $end
+$var wire 1 J6 sky130_fd_sc_hd__mux2_1_1_X [0] $end
+$var wire 1 K6 sky130_fd_sc_hd__mux2_1_2_X [0] $end
+$var wire 1 L6 BUF_net_88 $end
 
 $scope module mux_l1_in_0_ $end
-$var wire 1 U6 X $end
+$var wire 1 I6 X $end
 $var wire 1 |# A0 $end
 $var wire 1 N# A1 $end
-$var wire 1 B% S $end
-$var supply1 1 Y6 VPWR $end
-$var supply0 1 Z6 VGND $end
-$var supply1 1 [6 VPB $end
-$var supply0 1 \6 VNB $end
+$var wire 1 @% S $end
+$var supply1 1 M6 VPWR $end
+$var supply0 1 N6 VGND $end
+$var supply1 1 O6 VPB $end
+$var supply0 1 P6 VNB $end
 
 $scope module base $end
-$var wire 1 U6 X $end
+$var wire 1 I6 X $end
 $var wire 1 |# A0 $end
 $var wire 1 N# A1 $end
-$var wire 1 B% S $end
-$var wire 1 ]6 mux_2to10_out_X $end
+$var wire 1 @% S $end
+$var wire 1 Q6 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l1_in_1_ $end
-$var wire 1 V6 X $end
-$var wire 1 <& A0 $end
+$var wire 1 J6 X $end
+$var wire 1 r% A0 $end
 $var wire 1 &$ A1 $end
-$var wire 1 B% S $end
-$var supply1 1 ^6 VPWR $end
-$var supply0 1 _6 VGND $end
-$var supply1 1 `6 VPB $end
-$var supply0 1 a6 VNB $end
+$var wire 1 @% S $end
+$var supply1 1 R6 VPWR $end
+$var supply0 1 S6 VGND $end
+$var supply1 1 T6 VPB $end
+$var supply0 1 U6 VNB $end
 
 $scope module base $end
-$var wire 1 V6 X $end
-$var wire 1 <& A0 $end
+$var wire 1 J6 X $end
+$var wire 1 r% A0 $end
 $var wire 1 &$ A1 $end
-$var wire 1 B% S $end
-$var wire 1 b6 mux_2to10_out_X $end
+$var wire 1 @% S $end
+$var wire 1 V6 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
-$var wire 1 W6 X $end
-$var wire 1 V6 A0 $end
-$var wire 1 U6 A1 $end
-$var wire 1 C% S $end
-$var supply1 1 c6 VPWR $end
-$var supply0 1 d6 VGND $end
-$var supply1 1 e6 VPB $end
-$var supply0 1 f6 VNB $end
+$var wire 1 K6 X $end
+$var wire 1 J6 A0 $end
+$var wire 1 I6 A1 $end
+$var wire 1 A% S $end
+$var supply1 1 W6 VPWR $end
+$var supply0 1 X6 VGND $end
+$var supply1 1 Y6 VPB $end
+$var supply0 1 Z6 VNB $end
 
 $scope module base $end
-$var wire 1 W6 X $end
-$var wire 1 V6 A0 $end
-$var wire 1 U6 A1 $end
-$var wire 1 C% S $end
-$var wire 1 g6 mux_2to10_out_X $end
+$var wire 1 K6 X $end
+$var wire 1 J6 A0 $end
+$var wire 1 I6 A1 $end
+$var wire 1 A% S $end
+$var wire 1 [6 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_91 $end
+$scope module BINV_R_87 $end
 $var wire 1 @$ Y $end
-$var wire 1 X6 A $end
-$var supply1 1 h6 VPWR $end
-$var supply0 1 i6 VGND $end
-$var supply1 1 j6 VPB $end
-$var supply0 1 k6 VNB $end
+$var wire 1 L6 A $end
+$var supply1 1 \6 VPWR $end
+$var supply0 1 ]6 VGND $end
+$var supply1 1 ^6 VPB $end
+$var supply0 1 _6 VNB $end
 
 $scope module base $end
 $var wire 1 @$ Y $end
-$var wire 1 X6 A $end
-$var wire 1 l6 not0_out_Y $end
+$var wire 1 L6 A $end
+$var wire 1 `6 not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_92 $end
-$var wire 1 X6 Y $end
-$var wire 1 W6 A $end
-$var supply1 1 m6 VPWR $end
-$var supply0 1 n6 VGND $end
-$var supply1 1 o6 VPB $end
-$var supply0 1 p6 VNB $end
+$scope module BINV_R_88 $end
+$var wire 1 L6 Y $end
+$var wire 1 K6 A $end
+$var supply1 1 a6 VPWR $end
+$var supply0 1 b6 VGND $end
+$var supply1 1 c6 VPB $end
+$var supply0 1 d6 VNB $end
 
 $scope module base $end
-$var wire 1 X6 Y $end
-$var wire 1 W6 A $end
-$var wire 1 q6 not0_out_Y $end
+$var wire 1 L6 Y $end
+$var wire 1 K6 A $end
+$var wire 1 e6 not0_out_Y $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -6161,494 +6129,493 @@ $scope module mux_left_track_25 $end
 $var wire 1 V# in [0] $end
 $var wire 1 |# in [1] $end
 $var wire 1 &$ in [2] $end
-$var wire 1 D% sram [0] $end
-$var wire 1 E% sram [1] $end
-$var wire 1 \& sram_inv [0] $end
-$var wire 1 ]& sram_inv [1] $end
+$var wire 1 B% sram [0] $end
+$var wire 1 C% sram [1] $end
+$var wire 1 [& sram_inv [0] $end
+$var wire 1 \& sram_inv [1] $end
 $var wire 1 H$ out [0] $end
-$var wire 1 s% p0 $end
-$var wire 1 r6 sky130_fd_sc_hd__mux2_1_0_X [0] $end
-$var wire 1 s6 sky130_fd_sc_hd__mux2_1_1_X [0] $end
-$var wire 1 t6 sky130_fd_sc_hd__mux2_1_2_X [0] $end
-$var wire 1 u6 BUF_net_94 $end
+$var wire 1 ;& p0 $end
+$var wire 1 f6 sky130_fd_sc_hd__mux2_1_0_X [0] $end
+$var wire 1 g6 sky130_fd_sc_hd__mux2_1_1_X [0] $end
+$var wire 1 h6 sky130_fd_sc_hd__mux2_1_2_X [0] $end
+$var wire 1 i6 BUF_net_90 $end
 
 $scope module mux_l1_in_0_ $end
-$var wire 1 r6 X $end
+$var wire 1 f6 X $end
 $var wire 1 |# A0 $end
 $var wire 1 V# A1 $end
-$var wire 1 D% S $end
-$var supply1 1 v6 VPWR $end
-$var supply0 1 w6 VGND $end
-$var supply1 1 x6 VPB $end
-$var supply0 1 y6 VNB $end
+$var wire 1 B% S $end
+$var supply1 1 j6 VPWR $end
+$var supply0 1 k6 VGND $end
+$var supply1 1 l6 VPB $end
+$var supply0 1 m6 VNB $end
 
 $scope module base $end
-$var wire 1 r6 X $end
+$var wire 1 f6 X $end
 $var wire 1 |# A0 $end
 $var wire 1 V# A1 $end
-$var wire 1 D% S $end
-$var wire 1 z6 mux_2to10_out_X $end
+$var wire 1 B% S $end
+$var wire 1 n6 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l1_in_1_ $end
-$var wire 1 s6 X $end
-$var wire 1 s% A0 $end
+$var wire 1 g6 X $end
+$var wire 1 ;& A0 $end
 $var wire 1 &$ A1 $end
-$var wire 1 D% S $end
-$var supply1 1 {6 VPWR $end
-$var supply0 1 |6 VGND $end
-$var supply1 1 }6 VPB $end
-$var supply0 1 ~6 VNB $end
+$var wire 1 B% S $end
+$var supply1 1 o6 VPWR $end
+$var supply0 1 p6 VGND $end
+$var supply1 1 q6 VPB $end
+$var supply0 1 r6 VNB $end
 
 $scope module base $end
-$var wire 1 s6 X $end
-$var wire 1 s% A0 $end
+$var wire 1 g6 X $end
+$var wire 1 ;& A0 $end
 $var wire 1 &$ A1 $end
-$var wire 1 D% S $end
-$var wire 1 !7 mux_2to10_out_X $end
+$var wire 1 B% S $end
+$var wire 1 s6 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module mux_l2_in_0_ $end
-$var wire 1 t6 X $end
-$var wire 1 s6 A0 $end
-$var wire 1 r6 A1 $end
-$var wire 1 E% S $end
-$var supply1 1 "7 VPWR $end
-$var supply0 1 #7 VGND $end
-$var supply1 1 $7 VPB $end
-$var supply0 1 %7 VNB $end
+$var wire 1 h6 X $end
+$var wire 1 g6 A0 $end
+$var wire 1 f6 A1 $end
+$var wire 1 C% S $end
+$var supply1 1 t6 VPWR $end
+$var supply0 1 u6 VGND $end
+$var supply1 1 v6 VPB $end
+$var supply0 1 w6 VNB $end
 
 $scope module base $end
-$var wire 1 t6 X $end
-$var wire 1 s6 A0 $end
-$var wire 1 r6 A1 $end
-$var wire 1 E% S $end
-$var wire 1 &7 mux_2to10_out_X $end
+$var wire 1 h6 X $end
+$var wire 1 g6 A0 $end
+$var wire 1 f6 A1 $end
+$var wire 1 C% S $end
+$var wire 1 x6 mux_2to10_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_93 $end
+$scope module BINV_R_89 $end
 $var wire 1 H$ Y $end
-$var wire 1 u6 A $end
-$var supply1 1 '7 VPWR $end
-$var supply0 1 (7 VGND $end
-$var supply1 1 )7 VPB $end
-$var supply0 1 *7 VNB $end
+$var wire 1 i6 A $end
+$var supply1 1 y6 VPWR $end
+$var supply0 1 z6 VGND $end
+$var supply1 1 {6 VPB $end
+$var supply0 1 |6 VNB $end
 
 $scope module base $end
 $var wire 1 H$ Y $end
-$var wire 1 u6 A $end
-$var wire 1 +7 not0_out_Y $end
+$var wire 1 i6 A $end
+$var wire 1 }6 not0_out_Y $end
 $upscope $end
 $upscope $end
 
-$scope module BINV_R_94 $end
-$var wire 1 u6 Y $end
-$var wire 1 t6 A $end
-$var supply1 1 ,7 VPWR $end
-$var supply0 1 -7 VGND $end
-$var supply1 1 .7 VPB $end
-$var supply0 1 /7 VNB $end
+$scope module BINV_R_90 $end
+$var wire 1 i6 Y $end
+$var wire 1 h6 A $end
+$var supply1 1 ~6 VPWR $end
+$var supply0 1 !7 VGND $end
+$var supply1 1 "7 VPB $end
+$var supply0 1 #7 VNB $end
 
 $scope module base $end
-$var wire 1 u6 Y $end
-$var wire 1 t6 A $end
-$var wire 1 07 not0_out_Y $end
+$var wire 1 i6 Y $end
+$var wire 1 h6 A $end
+$var wire 1 $7 not0_out_Y $end
 $upscope $end
 $upscope $end
 $upscope $end
 
 $scope module mem_bottom_track_25 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 =% ccff_head [0] $end
-$var wire 1 F% ccff_tail [0] $end
-$var wire 1 @% mem_out [0] $end
-$var wire 1 A% mem_out [1] $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 ;% ccff_head [0] $end
+$var wire 1 D% ccff_tail [0] $end
+$var wire 1 >% mem_out [0] $end
+$var wire 1 ?% mem_out [1] $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 @% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 =% D $end
-$var supply1 1 17 VPWR $end
-$var supply0 1 27 VGND $end
-$var supply1 1 37 VPB $end
-$var supply0 1 47 VNB $end
+$var wire 1 >% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 ;% D $end
+$var supply1 1 %7 VPWR $end
+$var supply0 1 &7 VGND $end
+$var supply1 1 '7 VPB $end
+$var supply0 1 (7 VNB $end
 
 $scope module base $end
-$var wire 1 @% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 =% D $end
-$var wire 1 57 buf_Q $end
+$var wire 1 >% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 ;% D $end
+$var wire 1 )7 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 A% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 @% D $end
-$var supply1 1 67 VPWR $end
-$var supply0 1 77 VGND $end
-$var supply1 1 87 VPB $end
-$var supply0 1 97 VNB $end
+$var wire 1 ?% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 >% D $end
+$var supply1 1 *7 VPWR $end
+$var supply0 1 +7 VGND $end
+$var supply1 1 ,7 VPB $end
+$var supply0 1 -7 VNB $end
 
 $scope module base $end
-$var wire 1 A% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 @% D $end
-$var wire 1 :7 buf_Q $end
+$var wire 1 ?% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 >% D $end
+$var wire 1 .7 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_33__32 $end
-$var wire 1 F% X $end
-$var wire 1 A% A $end
-$var supply1 1 ;7 VPWR $end
-$var supply0 1 <7 VGND $end
-$var supply1 1 =7 VPB $end
-$var supply0 1 >7 VNB $end
+$var wire 1 D% X $end
+$var wire 1 ?% A $end
+$var supply1 1 /7 VPWR $end
+$var supply0 1 07 VGND $end
+$var supply1 1 17 VPB $end
+$var supply0 1 27 VNB $end
 
 $scope module base $end
-$var wire 1 F% X $end
-$var wire 1 A% A $end
-$var wire 1 ?7 buf0_out_X $end
+$var wire 1 D% X $end
+$var wire 1 ?% A $end
+$var wire 1 37 buf0_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
 
 $scope module mem_left_track_9 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 X% ccff_head [0] $end
-$var wire 1 G% ccff_tail [0] $end
-$var wire 1 B% mem_out [0] $end
-$var wire 1 C% mem_out [1] $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 V% ccff_head [0] $end
+$var wire 1 E% ccff_tail [0] $end
+$var wire 1 @% mem_out [0] $end
+$var wire 1 A% mem_out [1] $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 B% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 X% D $end
-$var supply1 1 @7 VPWR $end
-$var supply0 1 A7 VGND $end
-$var supply1 1 B7 VPB $end
-$var supply0 1 C7 VNB $end
+$var wire 1 @% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 V% D $end
+$var supply1 1 47 VPWR $end
+$var supply0 1 57 VGND $end
+$var supply1 1 67 VPB $end
+$var supply0 1 77 VNB $end
 
 $scope module base $end
-$var wire 1 B% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 X% D $end
-$var wire 1 D7 buf_Q $end
+$var wire 1 @% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 V% D $end
+$var wire 1 87 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 C% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 B% D $end
-$var supply1 1 E7 VPWR $end
-$var supply0 1 F7 VGND $end
-$var supply1 1 G7 VPB $end
-$var supply0 1 H7 VNB $end
+$var wire 1 A% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 @% D $end
+$var supply1 1 97 VPWR $end
+$var supply0 1 :7 VGND $end
+$var supply1 1 ;7 VPB $end
+$var supply0 1 <7 VNB $end
 
 $scope module base $end
-$var wire 1 C% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 B% D $end
-$var wire 1 I7 buf_Q $end
+$var wire 1 A% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 @% D $end
+$var wire 1 =7 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_34__33 $end
-$var wire 1 G% X $end
-$var wire 1 C% A $end
-$var supply1 1 J7 VPWR $end
-$var supply0 1 K7 VGND $end
-$var supply1 1 L7 VPB $end
-$var supply0 1 M7 VNB $end
+$var wire 1 E% X $end
+$var wire 1 A% A $end
+$var supply1 1 >7 VPWR $end
+$var supply0 1 ?7 VGND $end
+$var supply1 1 @7 VPB $end
+$var supply0 1 A7 VNB $end
 
 $scope module base $end
-$var wire 1 G% X $end
-$var wire 1 C% A $end
-$var wire 1 N7 buf0_out_X $end
+$var wire 1 E% X $end
+$var wire 1 A% A $end
+$var wire 1 B7 buf0_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
 
 $scope module mem_left_track_25 $end
-$var wire 1 U$ prog_clk [0] $end
-$var wire 1 0% ccff_head [0] $end
-$var wire 1 H% ccff_tail [0] $end
-$var wire 1 D% mem_out [0] $end
-$var wire 1 E% mem_out [1] $end
+$var wire 1 S$ prog_clk [0] $end
+$var wire 1 .% ccff_head [0] $end
+$var wire 1 F% ccff_tail [0] $end
+$var wire 1 B% mem_out [0] $end
+$var wire 1 C% mem_out [1] $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_0_ $end
-$var wire 1 D% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 0% D $end
-$var supply1 1 O7 VPWR $end
-$var supply0 1 P7 VGND $end
-$var supply1 1 Q7 VPB $end
-$var supply0 1 R7 VNB $end
+$var wire 1 B% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 .% D $end
+$var supply1 1 C7 VPWR $end
+$var supply0 1 D7 VGND $end
+$var supply1 1 E7 VPB $end
+$var supply0 1 F7 VNB $end
 
 $scope module base $end
-$var wire 1 D% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 0% D $end
-$var wire 1 S7 buf_Q $end
+$var wire 1 B% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 .% D $end
+$var wire 1 G7 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module sky130_fd_sc_hd__dfxtp_1_1_ $end
-$var wire 1 E% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 D% D $end
-$var supply1 1 T7 VPWR $end
-$var supply0 1 U7 VGND $end
-$var supply1 1 V7 VPB $end
-$var supply0 1 W7 VNB $end
+$var wire 1 C% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 B% D $end
+$var supply1 1 H7 VPWR $end
+$var supply0 1 I7 VGND $end
+$var supply1 1 J7 VPB $end
+$var supply0 1 K7 VNB $end
 
 $scope module base $end
-$var wire 1 E% Q $end
-$var wire 1 U$ CLK $end
-$var wire 1 D% D $end
-$var wire 1 X7 buf_Q $end
+$var wire 1 C% Q $end
+$var wire 1 S$ CLK $end
+$var wire 1 B% D $end
+$var wire 1 L7 buf_Q $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_35__34 $end
-$var wire 1 H% X $end
-$var wire 1 E% A $end
-$var supply1 1 Y7 VPWR $end
-$var supply0 1 Z7 VGND $end
-$var supply1 1 [7 VPB $end
-$var supply0 1 \7 VNB $end
+$var wire 1 F% X $end
+$var wire 1 C% A $end
+$var supply1 1 M7 VPWR $end
+$var supply0 1 N7 VGND $end
+$var supply1 1 O7 VPB $end
+$var supply0 1 P7 VNB $end
 
 $scope module base $end
-$var wire 1 H% X $end
-$var wire 1 E% A $end
-$var wire 1 ]7 buf0_out_X $end
+$var wire 1 F% X $end
+$var wire 1 C% A $end
+$var wire 1 Q7 buf0_out_X $end
 $upscope $end
 $upscope $end
 $upscope $end
 
 $scope module prog_clk_0_FTB00 $end
-$var wire 1 U$ X $end
-$var wire 1 T$ A $end
-$var supply1 1 ^7 VPWR $end
-$var supply0 1 _7 VGND $end
-$var supply1 1 `7 VPB $end
-$var supply0 1 a7 VNB $end
+$var wire 1 S$ X $end
+$var wire 1 R$ A $end
+$var supply1 1 R7 VPWR $end
+$var supply0 1 S7 VGND $end
+$var supply1 1 T7 VPB $end
+$var supply0 1 U7 VNB $end
 
 $scope module base $end
-$var wire 1 U$ X $end
-$var wire 1 T$ A $end
-$var wire 1 b7 buf0_out_X $end
+$var wire 1 S$ X $end
+$var wire 1 R$ A $end
+$var wire 1 V7 buf0_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_36__35 $end
 $var wire 1 ;$ X $end
 $var wire 1 h# A $end
-$var supply1 1 c7 VPWR $end
-$var supply0 1 d7 VGND $end
-$var supply1 1 e7 VPB $end
-$var supply0 1 f7 VNB $end
+$var supply1 1 W7 VPWR $end
+$var supply0 1 X7 VGND $end
+$var supply1 1 Y7 VPB $end
+$var supply0 1 Z7 VNB $end
 
 $scope module base $end
 $var wire 1 ;$ X $end
 $var wire 1 h# A $end
-$var wire 1 g7 buf0_out_X $end
+$var wire 1 [7 buf0_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_37__36 $end
 $var wire 1 7$ X $end
 $var wire 1 x# A $end
-$var supply1 1 h7 VPWR $end
-$var supply0 1 i7 VGND $end
-$var supply1 1 j7 VPB $end
-$var supply0 1 k7 VNB $end
+$var supply1 1 \7 VPWR $end
+$var supply0 1 ]7 VGND $end
+$var supply1 1 ^7 VPB $end
+$var supply0 1 _7 VNB $end
 
 $scope module base $end
 $var wire 1 7$ X $end
 $var wire 1 x# A $end
-$var wire 1 l7 buf0_out_X $end
+$var wire 1 `7 buf0_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_38__37 $end
 $var wire 1 8$ X $end
 $var wire 1 y# A $end
-$var supply1 1 m7 VPWR $end
-$var supply0 1 n7 VGND $end
-$var supply1 1 o7 VPB $end
-$var supply0 1 p7 VNB $end
+$var supply1 1 a7 VPWR $end
+$var supply0 1 b7 VGND $end
+$var supply1 1 c7 VPB $end
+$var supply0 1 d7 VNB $end
 
 $scope module base $end
 $var wire 1 8$ X $end
 $var wire 1 y# A $end
-$var wire 1 q7 buf0_out_X $end
+$var wire 1 e7 buf0_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_39__38 $end
 $var wire 1 9$ X $end
 $var wire 1 z# A $end
-$var supply1 1 r7 VPWR $end
-$var supply0 1 s7 VGND $end
-$var supply1 1 t7 VPB $end
-$var supply0 1 u7 VNB $end
+$var supply1 1 f7 VPWR $end
+$var supply0 1 g7 VGND $end
+$var supply1 1 h7 VPB $end
+$var supply0 1 i7 VNB $end
 
 $scope module base $end
 $var wire 1 9$ X $end
 $var wire 1 z# A $end
-$var wire 1 v7 buf0_out_X $end
+$var wire 1 j7 buf0_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_40__39 $end
 $var wire 1 :$ X $end
 $var wire 1 {# A $end
-$var supply1 1 w7 VPWR $end
-$var supply0 1 x7 VGND $end
-$var supply1 1 y7 VPB $end
-$var supply0 1 z7 VNB $end
+$var supply1 1 k7 VPWR $end
+$var supply0 1 l7 VGND $end
+$var supply1 1 m7 VPB $end
+$var supply0 1 n7 VNB $end
 
 $scope module base $end
 $var wire 1 :$ X $end
 $var wire 1 {# A $end
-$var wire 1 {7 buf0_out_X $end
+$var wire 1 o7 buf0_out_X $end
 $upscope $end
 $upscope $end
 
 $scope module FTB_41__40 $end
-$var wire 1 R$ X $end
-$var wire 1 Q$ A $end
-$var supply1 1 |7 VPWR $end
-$var supply0 1 }7 VGND $end
-$var supply1 1 ~7 VPB $end
-$var supply0 1 !8 VNB $end
+$var wire 1 Q$ X $end
+$var wire 1 $ A $end
+$var supply1 1 p7 VPWR $end
+$var supply0 1 q7 VGND $end
+$var supply1 1 r7 VPB $end
+$var supply0 1 s7 VNB $end
 
 $scope module base $end
-$var wire 1 R$ X $end
-$var wire 1 Q$ A $end
-$var wire 1 "8 buf0_out_X $end
+$var wire 1 Q$ X $end
+$var wire 1 $ A $end
+$var wire 1 t7 buf0_out_X $end
 $upscope $end
 $upscope $end
 
-$scope module FTB_42__41 $end
-$var wire 1 S$ X $end
-$var wire 1 $ A $end
+$scope module optlc_94 $end
+$var wire 1 ;& HI $end
+$var wire 1 ]& LO $end
+$var supply1 1 u7 VPWR $end
+$var supply0 1 v7 VGND $end
+$var supply1 1 w7 VPB $end
+$var supply0 1 x7 VNB $end
+
+$scope module base $end
+$var wire 1 ;& HI $end
+$var wire 1 ]& LO $end
+$upscope $end
+$upscope $end
+
+$scope module optlc_96 $end
+$var wire 1 j% HI $end
+$var wire 1 ^& LO $end
+$var supply1 1 y7 VPWR $end
+$var supply0 1 z7 VGND $end
+$var supply1 1 {7 VPB $end
+$var supply0 1 |7 VNB $end
+
+$scope module base $end
+$var wire 1 j% HI $end
+$var wire 1 ^& LO $end
+$upscope $end
+$upscope $end
+
+$scope module optlc_98 $end
+$var wire 1 r% HI $end
+$var wire 1 _& LO $end
+$var supply1 1 }7 VPWR $end
+$var supply0 1 ~7 VGND $end
+$var supply1 1 !8 VPB $end
+$var supply0 1 "8 VNB $end
+
+$scope module base $end
+$var wire 1 r% HI $end
+$var wire 1 _& LO $end
+$upscope $end
+$upscope $end
+
+$scope module optlc_100 $end
+$var wire 1 ,& HI $end
+$var wire 1 `& LO $end
 $var supply1 1 #8 VPWR $end
 $var supply0 1 $8 VGND $end
 $var supply1 1 %8 VPB $end
 $var supply0 1 &8 VNB $end
 
 $scope module base $end
-$var wire 1 S$ X $end
-$var wire 1 $ A $end
-$var wire 1 '8 buf0_out_X $end
-$upscope $end
-$upscope $end
-
-$scope module optlc_97 $end
-$var wire 1 '& HI $end
-$var wire 1 ^& LO $end
-$var supply1 1 (8 VPWR $end
-$var supply0 1 )8 VGND $end
-$var supply1 1 *8 VPB $end
-$var supply0 1 +8 VNB $end
-
-$scope module base $end
-$var wire 1 '& HI $end
-$var wire 1 ^& LO $end
-$upscope $end
-$upscope $end
-
-$scope module optlc_99 $end
-$var wire 1 <& HI $end
-$var wire 1 _& LO $end
-$var supply1 1 ,8 VPWR $end
-$var supply0 1 -8 VGND $end
-$var supply1 1 .8 VPB $end
-$var supply0 1 /8 VNB $end
-
-$scope module base $end
-$var wire 1 <& HI $end
-$var wire 1 _& LO $end
-$upscope $end
-$upscope $end
-
-$scope module optlc_101 $end
-$var wire 1 s% HI $end
+$var wire 1 ,& HI $end
 $var wire 1 `& LO $end
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diff --git a/FPGA1212_SOFA_HD_PNR/Verification/fpga_tests.py b/FPGA1212_SOFA_HD_PNR/Verification/fpga_tests.py
new file mode 100644
index 0000000..382a240
--- /dev/null
+++ b/FPGA1212_SOFA_HD_PNR/Verification/fpga_tests.py
@@ -0,0 +1,330 @@
+import random
+import os
+import sys
+import glob
+import math
+import cocotb
+import logging
+import filecmp
+from logging.handlers import RotatingFileHandler
+from collections import OrderedDict
+from pprint import pprint
+from xml.dom import minidom
+from cocotb.binary import BinaryValue
+from cocotb.log import SimLogFormatter
+from cocotb.clock import Clock
+from cocotb import wavedrom
+from cocotb.handle import Force, Release, Deposit
+from cocotb.monitors import Monitor
+from cocotb.scoreboard import Scoreboard
+from cocotb.triggers import FallingEdge, RisingEdge, Timer, ClockCycles
+
+root_logger = logging.getLogger()
+
+
+file_handler = RotatingFileHandler(
+    "run.log", maxBytes=(5 * 1024 * 1024), backupCount=2)
+# file_handler.setFormatter(SimLogFormatter())
+root_logger.addHandler(file_handler)
+
+
+@cocotb.test()
+async def AutoConfigureTest(dut):
+
+    CFFPaths = CreateCCFFChainPaths(dut)
+    TB = cocotb.os.environ['TB']
+    BitFile = os.path.join(".", "TESTBENCH", TB, "fabric_bitstream.xml")
+    # Create a 10us period clock on port clk
+    clock = Clock(dut.prog_clk_pad, 10, units="ns")
+    cocotb.fork(clock.start())  # Start the clock
+
+    # Initializing Chip with reset
+    dut.pReset_pad <= 1
+    dut.Reset_pad <= 1
+    await FallingEdge(dut.prog_clk_pad)
+    await FallingEdge(dut.prog_clk_pad)
+
+    dut._log.info(f"Testbench {BitFile}")
+
+    # Initializing Chip with reset
+    dut.pReset_pad <= 0
+    dut.Reset_pad <= 0
+
+    AutoConfigure(dut, BitFile, CFFPaths)
+    await RisingEdge(dut.prog_clk_pad)
+    with open("AfterProgramming.data", "w") as fp:
+        for eachPath in CFFPaths:
+            val = eval(eachPath)
+            if "0" in val.value.binstr:
+                dut._log.error(f"Wrong path {eachPath} {val.value}")
+            val = "\n".join(list(val.value.binstr))
+            fp.write(val+"\n")
+    await ClockCycles(dut.prog_clk_pad, 1)
+
+
+@cocotb.test()
+async def FastConfigureAndResetTest(dut):
+    '''
+    This test configures the fabric with given bitstream and
+    then resets it for one clock cycle and checks for all paths for logice 0
+    '''
+
+    chainLength, CFFPaths = CreateCCFFChainPaths(dut)
+    TB = cocotb.os.environ['TB']
+    BitFile = os.path.join(".", "TESTBENCH", TB, "fabric_bitstream.bit")
+
+    #  Create a 10ns period clock on port clk
+    clock = Clock(dut.prog_clk_pad, 10, units="ns")
+    cocotb.fork(clock.start(start_high=True))  # Start the clock
+    SaveConfiguration(CFFPaths, "BeforeInit.data", style="adjusted")
+
+    # Initializing Chip with reset
+    dut.pReset_pad <= 1
+    dut.Reset_pad <= 1
+    await FallingEdge(dut.prog_clk_pad)
+    await FallingEdge(dut.prog_clk_pad)
+
+    # Initializing Chip with reset
+    dut.pReset_pad <= 0
+    dut.Reset_pad <= 0
+    dut.ccff_head_pad <= 0
+    SaveConfiguration(CFFPaths, "BeforeProgramming.data", style="adjusted")
+
+    await AutoConfigure(dut, BitFile, CFFPaths, chainLength)
+    # await ProgramPhase(dut, BitFile)
+
+    # await RisingEdge(dut.prog_clk_pad)
+    SaveConfiguration(CFFPaths, "AfterProgramming.data", style="adjusted")
+
+    for _ in range(8):
+        await FallingEdge(dut.prog_clk_pad)
+
+    SaveConfiguration(CFFPaths, "After10Clocks.data", style="adjusted")
+
+    # Reset device
+    dut.pReset_pad <= 1
+    await FallingEdge(dut.prog_clk_pad)
+    dut.pReset_pad <= 0
+
+    # Check if all FF are Reset
+    for _, eachModule in CFFPaths.items():
+        for eachPath in eachModule:
+            val = eachPath["obj"].value.binstr
+            if "1" in val:
+                dut._log.error(f"Failed to reset {val} {eachPath['name']}")
+                dut._log.error(eachPath["obj"].value)
+
+    SaveConfiguration(CFFPaths, "AfterReset.data", style="adjusted")
+    await RisingEdge(dut.prog_clk_pad)
+
+
+@cocotb.test()
+async def ConfigChainTestFull(dut):
+
+    DESIGN_NAME = os.environ.get('DESIGN_NAME', 'fpga_top')
+    ProgClockPort = dut.prog_clk_pad if DESIGN_NAME == 'fpga_top' else dut.prog_clk
+
+    # Create a 10us period clock on port clk
+    clock = Clock(ProgClockPort, 10, units="ns")
+    cocotb.fork(clock.start())  # Start the clock
+
+    # Initializing Chip with reset
+    dut.pReset_pad <= 1
+    dut.Reset_pad <= 1
+    await FallingEdge(ProgClockPort)
+    await FallingEdge(ProgClockPort)
+
+    # Initializing Chip with reset
+    dut.pReset_pad <= 0
+    dut.Reset_pad <= 0
+
+    # Push single bit in chain
+    dut.ccff_head_pad <= 1
+    await FallingEdge(ProgClockPort)
+    dut.ccff_head_pad <= 0
+
+    # Check CCFF_tail of each module in sequence
+    CCFFChain = CreateCCFFChain()
+    ChainTrack = 0
+    PrevCapture = 0
+    for i in range(sys.maxsize):
+        await FallingEdge(ProgClockPort)
+        if eval(CCFFChain[ChainTrack]) == 1:
+            dut._log.info(
+                f"{ChainTrack} Received at {CCFFChain[ChainTrack]}" +
+                f" after {i-PrevCapture} Clocks at [{i}]")
+            PrevCapture = i
+            ChainTrack += 1
+            if ChainTrack == len(CCFFChain):
+                break
+    dut._log.info(f"Total bitstream length {i} bits")
+
+
+# ###================================================================
+# = = = = = = = = = = Utils Functions = = = = = = = = = = = = = = = =
+# ###================================================================
+
+
+@cocotb.coroutine
+async def ProgramPhase(dut, BitFile, maxCycles=sys.maxsize):
+    dut.pReset_pad = 0
+    bitCount = 0
+    with open(BitFile, "r") as fp:
+        dut._log.info(f"Bitfile opened : {BitFile}")
+        while bitCount < maxCycles:
+            c = fp.read(1)
+            if not c in ["0", "1"]:
+                dut._log.info(f"Configured device with {bitCount} bits")
+                break
+            bitCount += 1
+            if (bitCount % 50) == 0:
+                dut._log.info(f"Writen {bitCount} bits")
+            dut.ccff_head_pad = int(c)
+            await FallingEdge(dut.prog_clk_pad)
+
+
+@cocotb.coroutine
+async def AutoConfigure(dut, BitFile, ccPaths, BitstreamLen):
+    TotalBitsCount = 0
+    PreviousSync = 0
+    # Locking Signal
+    with open(BitFile, "r") as fp:
+        dut._log.info(f"Bitfile opened {BitFile}")
+        syncPts = math.ceil(BitstreamLen/4800)
+        InitialBits = [int(i) for i in list(fp.read(syncPts+1))]
+        dut._log.info(f"Will make total {syncPts} sync {InitialBits}")
+        for inst, eachModule in ccPaths.items():
+            BitsCount = 0
+            for eachPath in eachModule:
+                size = eachPath["width"]
+                BitsCount += size
+                try:
+                    Stream = fp.read(size)
+                    bits = int(Stream, 2)
+                except:
+                    dut._log.info(f"Padding Zero")
+                    bits = 0
+                eachPath["obj"] <= Force(bits)
+            TotalBitsCount += BitsCount
+            dut._log.info(f"Configured {inst} with {BitsCount} bits ")
+    dut.ccff_head_pad <= InitialBits.pop()
+    await FallingEdge(dut.prog_clk_pad)
+
+    # Releasing Signals
+    PreviousSync = 0
+    TotalBitsCount = 0
+    for inst, eachModule in ccPaths.items():
+        for eachPath in eachModule:
+            eachPath["obj"] <= Release()
+            TotalBitsCount += eachPath["width"]
+            if (TotalBitsCount-PreviousSync) > 4800:
+                dut.ccff_head_pad <= InitialBits.pop()
+                await FallingEdge(dut.prog_clk_pad)
+                PreviousSync = TotalBitsCount
+        dut._log.info(f"Releasing config of {inst}")
+    dut.ccff_head_pad <= InitialBits.pop()
+    await FallingEdge(dut.prog_clk_pad)
+    dut._log.info(f"Configured {TotalBitsCount} bits")
+
+
+def SaveConfiguration(CFFPaths, filename, style="default"):
+    lineW = 0
+    with open(filename, "w") as fp:
+        for _, eachModule in CFFPaths.items():
+            for eachPath in eachModule:
+                val = eachPath["obj"].value.binstr
+                if style == 'default':
+                    val = "\n".join(list(val))
+                    fp.write(val+"\n")
+                elif style == "bitstream":
+                    fp.write(val)
+                elif style == "detailed":
+                    fp.write(f"{eachPath['name']} {val}\n")
+                elif style == "adjusted":
+                    for eachC in val:
+                        fp.write(eachC)
+                        lineW += 1
+                        if (lineW == 32):
+                            fp.write("\n")
+                            lineW = 0
+
+
+def CreateCCFFChain():
+    CCFFChain = []
+    mydoc = minidom.parse(
+        glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0])
+    items = mydoc.getElementsByTagName('key')
+    for elem in items:
+        inst = elem.attributes['alias'].value
+        CCFFChain.append(f"dut.fpga_core_uut.{inst}.ccff_tail")
+    return CCFFChain
+
+
+def returnPaths(Node, PathList):
+    Nodes = [e for e in Node.childNodes if not isinstance(e, minidom.Text)]
+    # pprint(Nodes)
+    for eachN in Nodes:
+        eachNChild = [
+            e for e in eachN.childNodes if not isinstance(e, minidom.Text)]
+        Bitstream = [e for e in eachNChild if e.tagName == "bitstream"]
+        if Bitstream:
+            Hier = eachN.getElementsByTagName("hierarchy")[0]
+            path = [each.attributes["name"].value
+                    for each in Hier.getElementsByTagName("instance")]
+            path = ".".join(path).replace('fpga_top', 'dut.fpga_core_uut')
+
+            bitEles = Bitstream[0].getElementsByTagName("bit")
+            ports = [path + "." + each.attributes["memory_port"].value.split("[")[0]
+                     for each in bitEles[:1]]
+            length = len(bitEles)
+            value = "".join([e.attributes["value"].value for e in bitEles])
+            PathList.append({
+                "name":  ports[0],
+                "width": length,
+                "value": value
+            })
+        elif eachN.tagName == "bitstream_block":
+            returnPaths(eachN, PathList)
+
+
+def get_modules():
+    FabricKey = minidom.parse(
+        glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0])
+    items = FabricKey.getElementsByTagName('key')
+    return [elem.attributes['alias'].value for elem in items]
+
+
+def CreateCCFFChainPaths(dut):
+    BitstreamXML = minidom.parse(
+        glob.glob("./TESTBENCH/top/fabric_indepenent_bitstream.xml")[0])
+
+    ModulesDict = {}
+    BT_BLocks = BitstreamXML.getElementsByTagName('bitstream_block')
+    for element in BT_BLocks:
+        if element.getAttribute('hierarchy_level') == "1":
+            ModulesDict[element.attributes['name'].value] = element
+
+    FabricKey = minidom.parse(
+        glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0])
+    items = FabricKey.getElementsByTagName('key')
+
+    pathList = OrderedDict()
+    chainLength = 0
+
+    for elem in items:
+        modulePaths = []
+        moduleLen = 0
+        inst = elem.attributes['alias'].value
+        returnPaths(ModulesDict[inst], modulePaths)
+        for eachEle in modulePaths:
+            eachEle["obj"] = eval(eachEle["name"])
+            moduleLen += eachEle["width"]
+        pathList[inst] = modulePaths
+        chainLength += moduleLen
+    return (chainLength, pathList)
+
+
+if __name__ == "__main__":
+    CC = CreateCCFFChainPaths(None)
+    pprint(CC["grid_clb_1__2_"][:5])
+    pprint(len(CC["grid_clb_1__2_"]))
diff --git a/FPGA1212_SOFA_HD_PNR/Verification/skywater_tests.py b/FPGA1212_SOFA_HD_PNR/Verification/skywater_tests.py
index 40a1e19..9e5ed4b 100644
--- a/FPGA1212_SOFA_HD_PNR/Verification/skywater_tests.py
+++ b/FPGA1212_SOFA_HD_PNR/Verification/skywater_tests.py
@@ -89,6 +89,7 @@ async def ConfigChainTestFull(dut):
                 TestFailure(
                     f"Expected 8 ticks on module {ModuleName} received {CLKTick}")
         end_ccff_time = get_sim_time(units='ns')
+        await ClockCycles(prog_clk, 10)
         TotalClock = math.ceil((end_ccff_time-start_ccff_time)/PCLK_PERIOD)
         dut._log.info(f"Simulation Finished in clocks {TotalClock}")
     except SimTimeoutError:
@@ -146,6 +147,7 @@ async def ScanChainTestFull(dut):
                         f"Expected 8 ticks on module {ModuleName} received {CLKTick}")
         end_scff_time = get_sim_time(units='ns')
         TotalClock = math.ceil((end_scff_time-start_scff_time)/CLK_PERIOD)
+        await ClockCycles(clk, 10)
         dut._log.info(f"Simulation Finished in clocks {TotalClock}")
         dut._log.info(f"Per Grid {TotalClock/(PConf['FPGA_SIZE_X']**2)}")
     except SimTimeoutError: