From fcee5f1c919c9f7269411da1aaf5b1d563d3b0d5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 18:02:26 -0700 Subject: [PATCH 01/24] [HDL] Typo fix in pin assignment description --- HDL/common/caravel_wrapper_pin_assignment_v1.0.json | 4 ++-- HDL/common/caravel_wrapper_pin_assignment_v1.1.json | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/HDL/common/caravel_wrapper_pin_assignment_v1.0.json b/HDL/common/caravel_wrapper_pin_assignment_v1.0.json index 24be77f..c8451d6 100644 --- a/HDL/common/caravel_wrapper_pin_assignment_v1.0.json +++ b/HDL/common/caravel_wrapper_pin_assignment_v1.0.json @@ -5,8 +5,8 @@ "caravel_logic_analyzer_input_name": "la_data_in", "caravel_logic_analyzer_output_name": "la_data_out", "caravel_logic_analyzer_direction_name": "la_oen", - "caravel_wishbone_clock_input_name": "wbs_clk_i", - "caravel_wishbone_reset_input_name": "wbs_rst_i", + "caravel_wishbone_clock_input_name": "wb_clk_i", + "caravel_wishbone_reset_input_name": "wb_rst_i", "caravel_wishbone_ack_output_name": "wbs_ack_o", "caravel_wishbone_cyc_input_name": "wbs_cyc_i", "caravel_wishbone_stb_input_name": "wbs_stb_i", diff --git a/HDL/common/caravel_wrapper_pin_assignment_v1.1.json b/HDL/common/caravel_wrapper_pin_assignment_v1.1.json index bec2e01..8100de6 100644 --- a/HDL/common/caravel_wrapper_pin_assignment_v1.1.json +++ b/HDL/common/caravel_wrapper_pin_assignment_v1.1.json @@ -5,8 +5,8 @@ "caravel_logic_analyzer_input_name": "la_data_in", "caravel_logic_analyzer_output_name": "la_data_out", "caravel_logic_analyzer_direction_name": "la_oen", - "caravel_wishbone_clock_input_name": "wbs_clk_i", - "caravel_wishbone_reset_input_name": "wbs_rst_i", + "caravel_wishbone_clock_input_name": "wb_clk_i", + "caravel_wishbone_reset_input_name": "wb_rst_i", "caravel_wishbone_ack_output_name": "wbs_ack_o", "caravel_wishbone_cyc_input_name": "wbs_cyc_i", "caravel_wishbone_stb_input_name": "wbs_stb_i", From 64ae33066e5d7db40b31f44fbdc189b763b70939 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 20:23:34 -0700 Subject: [PATCH 02/24] [Testbench] Add script to convert post-PnR testbench for wrapper testbench --- .../post_pnr_wrapper_testbench_converter.py | 282 ++++++++++++++++++ 1 file changed, 282 insertions(+) create mode 100644 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py diff --git a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py new file mode 100644 index 0000000..78a7d35 --- /dev/null +++ b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py @@ -0,0 +1,282 @@ +##################################################################### +# Python script to convert a post-PnR Verilog testbench +# to a post-PnR Verilog testbench based on Caravel Wrapper +# This script will +# - Replace the FPGA instance with a Caravel wrapper instance +# - Generate wrapper input ports based on a pin assignment json file +##################################################################### + +import os +from os.path import dirname, abspath, isfile +import shutil +import re +import argparse +import logging +import json + +##################################################################### +# Initialize logger +##################################################################### +logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.DEBUG) + +##################################################################### +# Parse the options +##################################################################### +parser = argparse.ArgumentParser(description='Converter for post-PnR wrapper Verilog testbench') +parser.add_argument('--post_pnr_testbench', required=True, + help='Specify the file path for the post-PnR Verilog testbench as input') +parser.add_argument('--pin_assignment_file', required=True, + help='Specify the file path to the pin assignment JSON description as input') +parser.add_argument('--wrapper_testbench', required=True, + help='Specify the file path for the post-PnR wrapper Verilog testbench to be outputted') +args = parser.parse_args() + +##################################################################### +# Check options: +# - Input file must be valid +# Otherwise, error out +# - Remove any output file if already exist +# TODO: give a warning when remove files +##################################################################### +if not isfile(args.post_pnr_testbench): + logging.error("Invalid pre-PnR testbench: " + args.post_pnr_testbench + "\nFile does not exist!\n") + exit(1) +if not isfile(args.pin_assignment_file): + logging.error("Invalid pin assignment file: " + args.pin_assignment_file + "\nFile does not exist!\n") + exit(1) +if isfile(args.wrapper_testbench): + logging.warn("Remove existing post-PnR testbench: " + args.wrapper_testbench + "!\n") + os.remove(args.wrapper_testbench) + +##################################################################### +# Parse the json file +##################################################################### +json_file = open(args.pin_assignment_file, "r") +pin_data = json.load(json_file) + +##################################################################### +# TODO: This is a duplicated function from the wrapper_lines_generator.py +# Should merge them and make it shareable between scripts + +# A function to parse pin range from json data +# JSON pin range format is LSB:MSB +# Return pin range format is [LSB, MSB] as a list +##################################################################### +def parse_json_pin_range(json_range) : + pin_range_str = json_range.split(':') + assert(2 == len(pin_range_str)) + # If the range is in decend order, we will decrease the MSB by 1 + if (int(pin_range_str[0]) > int(pin_range_str[1])) : + return range(int(pin_range_str[0]), int(pin_range_str[1]) - 1, -1) + # If the range is in acend order, we will increase the MSB by 1 + return range(int(pin_range_str[0]), int(pin_range_str[1]) + 1) + +##################################################################### +# Write the connections between wrapper ports and existing stimuli +# to the testbench file +##################################################################### +def write_testbench_wrapper_connection(tb_file, pin_data, mode_switch_io_index): + # Switch to the logic analyzer mode for io[25] which is reserved for mode-switch purpose + mode_switch_line = "assign " + pin_data['caravel_gpio_input_name'] + "[" + str(mode_switch_io_index) + "] = " \ + + "1b'0;"; + tb_file.write(" " + mode_switch_line + "\n") + + for pin_info in pin_data['pins']: + ####################################################### + # For FPGA INPUTs, + # wrapper inputs should be driven these existing wires + # For instance: + # assign wrapper_input = FPGA_INPUT; + # + # For FPGA OUTPUTs, + # wrapper outputs should drive these existing wires + # For instance: + # assign FPGA_OUTPUT = wrapper_output; + + # - FPGA I/O ports to Caravel GPIO + if (("io" == pin_info['fpga_pin_type']) \ + and (1 == len(pin_info['caravel_pin_type'])) \ + and ("gpio" == pin_info['caravel_pin_type'][0])): + # Should have only 1 port in caravel + assert(1 == len(pin_info['caravel_pin_type'])) + assert(1 == len(pin_info['caravel_pin_index'])) + # Get pin range + fpga_io_pin_range = parse_json_pin_range(pin_info['fpga_pin_index']) + caravel_io_pin_range = parse_json_pin_range(pin_info['caravel_pin_index'][0]) + assert(len(list(fpga_io_pin_range)) == len(list(caravel_io_pin_range))) + for indices in zip(list(fpga_io_pin_range), list(caravel_io_pin_range)) : + # FPGA input <- Caravel input + curr_line = "assign " + pin_data['caravel_gpio_input_name'] + "[" + str(indices[1]) + "] = " \ + + pin_data['fpga_gpio_input_name'] + "[" + str(indices[0]) + "];"; + tb_file.write(" " + curr_line + "\n") + # FPGA output -> Caravel output + curr_line = "assign " + pin_data['fpga_gpio_output_name'] + "[" + str(indices[0]) + "] = " \ + + pin_data['caravel_gpio_output_name'] + "[" + str(indices[1]) + "];"; + tb_file.write(" " + curr_line + "\n") + # FPGA direction -> Caravel direction + curr_line = "assign " + pin_data['fpga_gpio_direction_name'] + "[" + str(indices[0]) + "] = " \ + + pin_data['caravel_gpio_direction_name'] + "[" + str(indices[1]) + "];"; + tb_file.write(" " + curr_line + "\n") + + # - FPGA control input ports to Caravel GPIO + if (("io" != pin_info['fpga_pin_type']) \ + and (1 == len(pin_info['caravel_pin_type'])) \ + and ("input" == pin_info['caravel_pin_type'][0])): + # Should have only 1 port in caravel + assert(1 == len(pin_info['caravel_pin_type'])) + assert(1 == len(pin_info['caravel_pin_index'])) + # Get pin range + fpga_io_pin_range = parse_json_pin_range(pin_info['fpga_pin_index']) + caravel_io_pin_range = parse_json_pin_range(pin_info['caravel_pin_index'][0]) + assert(len(list(fpga_io_pin_range)) == len(list(caravel_io_pin_range))) + for indices in zip(list(fpga_io_pin_range), list(caravel_io_pin_range)) : + # Connect the FPGA input port to the Caravel input + curr_line = "assign " + pin_info['caravel_gpio_input_name'] + "[" + str(indices[1]) + "] = " \ + + pin_data['fpga_pin_type'] + "[" + str(indices[0]) + "];"; + tb_file.write(" " + curr_line + "\n") + + # - FPGA control output ports to Caravel GPIO + if (("io" != pin_info['fpga_pin_type']) \ + and (1 == len(pin_info['caravel_pin_type'])) \ + and ("output" == pin_info['caravel_pin_type'][0])): + # Should have only 1 port in caravel + assert(1 == len(pin_info['caravel_pin_type'])) + assert(1 == len(pin_info['caravel_pin_index'])) + # Get pin range + fpga_io_pin_range = parse_json_pin_range(pin_info['fpga_pin_index']) + caravel_io_pin_range = parse_json_pin_range(pin_info['caravel_pin_index'][0]) + assert(len(list(fpga_io_pin_range)) == len(list(caravel_io_pin_range))) + for indices in zip(list(fpga_io_pin_range), list(caravel_io_pin_range)) : + # Tie the Caravel input to logic '0' + curr_line = "assign " + pin_data['caravel_gpio_input_name'] + "[" + str(indices[1]) + "] = 1'b0;" + tb_file.write(" " + curr_line + "\n") + # Connect Caravel output port to FPGA control output + curr_line = "assign " + pin_data['fpga_pin_type'] + "[" + str(indices[0]) + "] = " \ + + pin_info['caravel_gpio_output_name'] + "[" + str(indices[1]) + "];"; + tb_file.write(" " + curr_line + "\n") + + # - We always try to use the logic analyzer to connect FPGA I/O ports + if (("io" == pin_info['fpga_pin_type']) \ + and ("logic_analyzer_io" == pin_info['caravel_pin_type'][0])): + # Get pin range + fpga_io_pin_range = parse_json_pin_range(pin_info['fpga_pin_index']) + caravel_io_pin_range = parse_json_pin_range(pin_info['caravel_pin_index'][0]) + assert(len(list(fpga_io_pin_range)) == len(list(caravel_io_pin_range))) + for indices in zip(list(fpga_io_pin_range), list(caravel_io_pin_range)) : + ############################################################## + # SOC INPUT will be directly driven by logic analyzer + # since this I/O is going to interface logic analyzer input only + curr_line = "assign " + pin_data['caravel_logic_analyzer_input_name'] + "[" + str(indices[1]) + "] = " \ + + pin_data['fpga_gpio_input_name'] + "[" + str(indices[0]) + "]" + ";" + tb_file.write(" " + curr_line + "\n") + ############################################################## + # SOC OUTPUT will directly drive logic analyzer + # since this I/O is going to interface logic analyzer output only + curr_line = "assign " + pin_data['fpga_gpio_output_name'] + "[" + str(indices[0]) + "]" \ + + " = " + pin_data['caravel_logic_analyzer_output_name'] + "[" + str(indices[1]) + "];" + tb_file.write(" " + curr_line + "\n") + +##################################################################### +# Open the post-pnr Verilog testbench and start modification +##################################################################### +logging.info("Converting post-PnR testbench:"+ args.post_pnr_testbench) +logging.info("To post-PnR wrapper testbench:"+ args.wrapper_pnr_testbench) +# Create output file handler +tb_file = open(args.wrapper_testbench, "w") + +################################# +# Control signals to output lines +# Skip current line: when raised, current line will not be outputted +skip_current_line = False +fpga_instance_lines = False + +# Read line by line from pre-PnR testbench +with open(args.post_pnr_testbench, "r") as wp: + template_netlist = wp.readlines() + for line_num, curr_line in enumerate(template_netlist): + # If the current line satisfy the following conditions + # It should be modified and outputted to post-PnR Verilog testbenches + # Other lines can be directly copied to post-PnR Verilog testbenches + line2output = curr_line \ + # + # Add post_pnr to top-level module name + if (curr_line.startswith("module")): + line2output = re.sub("autocheck_top_tb;$", "wrapper_autocheck_top_tb;", curr_line) + # Add the wires required by the wrapper + if (curr_line == "wire [0:0] sc_tail;\n"): + line2output = line2output \ + + "// ---- Wrapper I/O wires ----\n" \ + + "// ---- Power pins ----\n" \ + + "wire [0:0] vdda1;\n" \ + + "wire [0:0] vdda2;\n" \ + + "wire [0:0] vssa1;\n" \ + + "wire [0:0] vssa2;\n" \ + + "wire [0:0] vccd1;\n" \ + + "wire [0:0] vccd2;\n" \ + + "wire [0:0] vssd1;\n" \ + + "wire [0:0] vssd2;\n" \ + + "// ---- Wishbone pins ----\n" \ + + "wire [0:0] wb_clk_i;\n" \ + + "wire [0:0] wb_rst_i;\n" \ + + "wire [0:0] wbs_stb_i;\n" \ + + "wire [0:0] wbs_cyc_i;\n" \ + + "wire [0:0] wbs_we_i;\n" \ + + "wire [3:0] wbs_sel_i;\n" \ + + "wire [31:0] wbs_dat_i;\n" \ + + "wire [31:0] wbs_adr_i;\n" \ + + "wire [0:0] wbs_ack_o;\n" \ + + "wire [31:0] wbs_dat_o;\n" \ + + "// ---- Logic analyzer pins ----\n" \ + + "wire [127:0] la_data_in;\n" \ + + "wire [127:0] la_data_out;\n" \ + + "wire [127:0] la_oen;\n" \ + + "// ---- GPIO pins ----\n" \ + + "wire [`MRPJ_IO_PADS-1:0] io_in;\n" \ + + "wire [`MRPJ_IO_PADS-1:0] io_out;\n" \ + + "wire [`MRPJ_IO_PADS-1:0] io_oeb;\n" \ + + "// ---- Analog I/O pins ----\n" \ + + "wire [`MPRJ_IO_PADS-8:0] analog_io;\n" + + # Skip all the lines about FPGA instanciation + if (curr_line == "\tfpga_core FPGA_DUT (\n"): + skip_current_line = True + fpga_instance_lines = True + + # When FPGA instance are skipped, add the wrapper instance + if ((True == fpga_instance_lines) and (curr_line.endswith(");\n"))): + skip_current_line = False + line2output = "\tfpga_wrapper FPGA_DUT(\n" \ + + "\t\t\t.vdda1(vdda1),\n" \ + + "\t\t\t.vdda2(vdda2),\n" \ + + "\t\t\t.vssa1(vssa1),\n" \ + + "\t\t\t.vssa2(vssa2),\n" \ + + "\t\t\t.vccd1(vccd1),\n" \ + + "\t\t\t.vccd2(vccd2),\n" \ + + "\t\t\t.vssd1(vssd1),\n" \ + + "\t\t\t.vssd2(vssd2),\n" \ + + "\t\t\t.wb_clk_i(wb_clk_i),\n" \ + + "\t\t\t.wb_rst_i(wb_rst_i),\n" \ + + "\t\t\t.wbs_stb_i(wbs_stb_i),\n" \ + + "\t\t\t.wbs_cyc_i(wbs_cyc_i),\n" \ + + "\t\t\t.wbs_sel_i(wbs_sel_i),\n" \ + + "\t\t\t.wbs_dat_i(wbs_dat_i),\n" \ + + "\t\t\t.wbs_adr_i(wbs_adr_i),\n" \ + + "\t\t\t.wbs_ack_o(wbs_ack_o),\n" \ + + "\t\t\t.wbs_dat_o(wbs_dat_o),\n" \ + + "\t\t\t.la_data_in(la_data_in),\n" \ + + "\t\t\t.la_data_out(la_data_out),\n" \ + + "\t\t\t.la_oen(la_oen),\n" \ + + "\t\t\t.io_in(io_in),\n" \ + + "\t\t\t.io_out(io_out),\n" \ + + "\t\t\t.io_oeb(io_oeb),\n" \ + + "\t\t\t.analog_io(analog_io)\n" \ + + "\t\t\t);\n"; + + # Wire the stimuli according to pin assignment + write_testbench_wrapper_connection(tb_file, pin_data, 25) + + if (False == skip_current_line): + tb_file.write(line2output) + +tb_file.close() +logging.info("Done") From a414a600a69c64ada5f7206acf5050b716955679 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 20:31:19 -0700 Subject: [PATCH 03/24] [Testbench] Bug fixed in wrapper testbench generator --- .../post_pnr_wrapper_testbench_converter.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py index 78a7d35..f9e5051 100644 --- a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py +++ b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py @@ -131,8 +131,8 @@ def write_testbench_wrapper_connection(tb_file, pin_data, mode_switch_io_index): assert(len(list(fpga_io_pin_range)) == len(list(caravel_io_pin_range))) for indices in zip(list(fpga_io_pin_range), list(caravel_io_pin_range)) : # Connect the FPGA input port to the Caravel input - curr_line = "assign " + pin_info['caravel_gpio_input_name'] + "[" + str(indices[1]) + "] = " \ - + pin_data['fpga_pin_type'] + "[" + str(indices[0]) + "];"; + curr_line = "assign " + pin_data['caravel_gpio_input_name'] + "[" + str(indices[1]) + "] = " \ + + pin_info['fpga_pin_type'] + "[" + str(indices[0]) + "];"; tb_file.write(" " + curr_line + "\n") # - FPGA control output ports to Caravel GPIO @@ -151,8 +151,8 @@ def write_testbench_wrapper_connection(tb_file, pin_data, mode_switch_io_index): curr_line = "assign " + pin_data['caravel_gpio_input_name'] + "[" + str(indices[1]) + "] = 1'b0;" tb_file.write(" " + curr_line + "\n") # Connect Caravel output port to FPGA control output - curr_line = "assign " + pin_data['fpga_pin_type'] + "[" + str(indices[0]) + "] = " \ - + pin_info['caravel_gpio_output_name'] + "[" + str(indices[1]) + "];"; + curr_line = "assign " + pin_info['fpga_pin_type'] + "[" + str(indices[0]) + "] = " \ + + pin_data['caravel_gpio_output_name'] + "[" + str(indices[1]) + "];"; tb_file.write(" " + curr_line + "\n") # - We always try to use the logic analyzer to connect FPGA I/O ports @@ -180,7 +180,7 @@ def write_testbench_wrapper_connection(tb_file, pin_data, mode_switch_io_index): # Open the post-pnr Verilog testbench and start modification ##################################################################### logging.info("Converting post-PnR testbench:"+ args.post_pnr_testbench) -logging.info("To post-PnR wrapper testbench:"+ args.wrapper_pnr_testbench) +logging.info("To post-PnR wrapper testbench:"+ args.wrapper_testbench) # Create output file handler tb_file = open(args.wrapper_testbench, "w") @@ -245,6 +245,7 @@ with open(args.post_pnr_testbench, "r") as wp: # When FPGA instance are skipped, add the wrapper instance if ((True == fpga_instance_lines) and (curr_line.endswith(");\n"))): skip_current_line = False + fpga_instance_lines = False line2output = "\tfpga_wrapper FPGA_DUT(\n" \ + "\t\t\t.vdda1(vdda1),\n" \ + "\t\t\t.vdda2(vdda2),\n" \ @@ -271,9 +272,8 @@ with open(args.post_pnr_testbench, "r") as wp: + "\t\t\t.io_oeb(io_oeb),\n" \ + "\t\t\t.analog_io(analog_io)\n" \ + "\t\t\t);\n"; - - # Wire the stimuli according to pin assignment - write_testbench_wrapper_connection(tb_file, pin_data, 25) + # Wire the stimuli according to pin assignment + write_testbench_wrapper_connection(tb_file, pin_data, 25) if (False == skip_current_line): tb_file.write(line2output) From eeb904a3e3671b0bd2cb2ac5be127487c26db3a0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 20:32:59 -0700 Subject: [PATCH 04/24] [Testbench] Typo fix in wrapper testbench converter --- TESTBENCH/common/post_pnr_wrapper_testbench_converter.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py index f9e5051..d344b39 100644 --- a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py +++ b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py @@ -78,7 +78,7 @@ def parse_json_pin_range(json_range) : def write_testbench_wrapper_connection(tb_file, pin_data, mode_switch_io_index): # Switch to the logic analyzer mode for io[25] which is reserved for mode-switch purpose mode_switch_line = "assign " + pin_data['caravel_gpio_input_name'] + "[" + str(mode_switch_io_index) + "] = " \ - + "1b'0;"; + + "1'b0;"; tb_file.write(" " + mode_switch_line + "\n") for pin_info in pin_data['pins']: From 4ab69d925c0c87ad89b03fafd74edeb19a45ae5e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 20:46:50 -0700 Subject: [PATCH 05/24] [Testbench] Add include netlist for wrapper testbench --- .../verilog_testbench/and2_post_pnr_wrapper_include_netlists.v | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..f4ea781 --- /dev/null +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:fcc9a447188a16956ca8a53f0916e3b1763cd9aa376c522f51777ff8f8f840ab +size 1370 From e3efcebf2b7e3cb90bd7768ee7131de6e83f882c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 21:00:20 -0700 Subject: [PATCH 06/24] [Testbench] Bug fix in include netlist --- .../and2_post_pnr_wrapper_include_netlists.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v index f4ea781..40df803 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fcc9a447188a16956ca8a53f0916e3b1763cd9aa376c522f51777ff8f8f840ab -size 1370 +oid sha256:9f6df360605df5a436036afc2ccf3b950ce42b3c9ea396350cd4ebbb4d705b9d +size 1466 From 78addbe29465d62dbbf0fcbce89197f4d7e7a917 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 21:01:44 -0700 Subject: [PATCH 07/24] [HDL] Name fix to be compatible with testbench generation --- HDL/common/caravel_fpga_wrapper_hd_template.v | 2 +- HDL/common/caravel_wrapper_pin_assignment_v1.0.json | 4 ++-- HDL/common/caravel_wrapper_pin_assignment_v1.1.json | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/HDL/common/caravel_fpga_wrapper_hd_template.v b/HDL/common/caravel_fpga_wrapper_hd_template.v index 448d320..5c0d458 100644 --- a/HDL/common/caravel_fpga_wrapper_hd_template.v +++ b/HDL/common/caravel_fpga_wrapper_hd_template.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0970910e47d809b8748958d5828b580dca8735205da533069af7ce6cb5a8ba34 +oid sha256:f1a4fa593e880caa1e6b1c8dac904ae9c9718fcf9d3711bcb006455643e22f97 size 3246 diff --git a/HDL/common/caravel_wrapper_pin_assignment_v1.0.json b/HDL/common/caravel_wrapper_pin_assignment_v1.0.json index c8451d6..5fd7fdd 100644 --- a/HDL/common/caravel_wrapper_pin_assignment_v1.0.json +++ b/HDL/common/caravel_wrapper_pin_assignment_v1.0.json @@ -46,13 +46,13 @@ "caravel_pin_index": ["10:2"] }, { - "fpga_pin_type": "io_isol_n", + "fpga_pin_type": "IO_ISOL_N", "fpga_pin_index": "0:0", "caravel_pin_type": ["input"], "caravel_pin_index": ["1:1"] }, { - "fpga_pin_type": "test_en", + "fpga_pin_type": "Test_en", "fpga_pin_index": "0:0", "caravel_pin_type": ["input"], "caravel_pin_index": ["0:0"] diff --git a/HDL/common/caravel_wrapper_pin_assignment_v1.1.json b/HDL/common/caravel_wrapper_pin_assignment_v1.1.json index 8100de6..901ffb3 100644 --- a/HDL/common/caravel_wrapper_pin_assignment_v1.1.json +++ b/HDL/common/caravel_wrapper_pin_assignment_v1.1.json @@ -58,13 +58,13 @@ "caravel_pin_index": ["2:2"] }, { - "fpga_pin_type": "io_isol_n", + "fpga_pin_type": "IO_ISOL_N", "fpga_pin_index": "0:0", "caravel_pin_type": ["input"], "caravel_pin_index": ["1:1"] }, { - "fpga_pin_type": "test_en", + "fpga_pin_type": "Test_en", "fpga_pin_index": "0:0", "caravel_pin_type": ["input"], "caravel_pin_index": ["0:0"] From 951f5f84ee15c0a070f243c26f49690720e4e78a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 21:15:36 -0700 Subject: [PATCH 08/24] [Testbench] Typo fix --- TESTBENCH/common/post_pnr_wrapper_testbench_converter.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py index d344b39..6f2ebd8 100644 --- a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py +++ b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py @@ -231,9 +231,9 @@ with open(args.post_pnr_testbench, "r") as wp: + "wire [127:0] la_data_out;\n" \ + "wire [127:0] la_oen;\n" \ + "// ---- GPIO pins ----\n" \ - + "wire [`MRPJ_IO_PADS-1:0] io_in;\n" \ - + "wire [`MRPJ_IO_PADS-1:0] io_out;\n" \ - + "wire [`MRPJ_IO_PADS-1:0] io_oeb;\n" \ + + "wire [`MPRJ_IO_PADS-1:0] io_in;\n" \ + + "wire [`MPRJ_IO_PADS-1:0] io_out;\n" \ + + "wire [`MPRJ_IO_PADS-1:0] io_oeb;\n" \ + "// ---- Analog I/O pins ----\n" \ + "wire [`MPRJ_IO_PADS-8:0] analog_io;\n" From fec19ebc55d597bda09f1b891d8816164b07d9c6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 21:19:56 -0700 Subject: [PATCH 09/24] [Testbench] Typo fix --- TESTBENCH/common/post_pnr_wrapper_testbench_converter.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py index 6f2ebd8..2fcd170 100644 --- a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py +++ b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py @@ -246,7 +246,7 @@ with open(args.post_pnr_testbench, "r") as wp: if ((True == fpga_instance_lines) and (curr_line.endswith(");\n"))): skip_current_line = False fpga_instance_lines = False - line2output = "\tfpga_wrapper FPGA_DUT(\n" \ + line2output = "\tfpga_top FPGA_DUT(\n" \ + "\t\t\t.vdda1(vdda1),\n" \ + "\t\t\t.vdda2(vdda2),\n" \ + "\t\t\t.vssa1(vssa1),\n" \ From 5235424e83be008bc72763d947da97388952b5fc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 21:44:29 -0700 Subject: [PATCH 10/24] [Testbench] Adapt path for signal init in testbench converter --- TESTBENCH/common/post_pnr_wrapper_testbench_converter.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py index 2fcd170..c7c9c57 100644 --- a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py +++ b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py @@ -197,7 +197,7 @@ with open(args.post_pnr_testbench, "r") as wp: # If the current line satisfy the following conditions # It should be modified and outputted to post-PnR Verilog testbenches # Other lines can be directly copied to post-PnR Verilog testbenches - line2output = curr_line \ + line2output = curr_line # # Add post_pnr to top-level module name if (curr_line.startswith("module")): @@ -274,6 +274,10 @@ with open(args.post_pnr_testbench, "r") as wp: + "\t\t\t);\n"; # Wire the stimuli according to pin assignment write_testbench_wrapper_connection(tb_file, pin_data, 25) + + # Correct the path in signal initialization + if (re.search(r'\$deposit\(FPGA_DUT', curr_line)): + line2output = re.sub(r'\$deposit\(FPGA_DUT', '$deposit(FPGA_DUT.fpga_core_uut', curr_line) if (False == skip_current_line): tb_file.write(line2output) From 724696a661453c72ad832fede615eaa4daa835a0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 22:16:04 -0700 Subject: [PATCH 11/24] [Testbench] Add missing ports in the wrapper --- TESTBENCH/common/post_pnr_wrapper_testbench_converter.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py index c7c9c57..f181544 100644 --- a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py +++ b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py @@ -270,7 +270,8 @@ with open(args.post_pnr_testbench, "r") as wp: + "\t\t\t.io_in(io_in),\n" \ + "\t\t\t.io_out(io_out),\n" \ + "\t\t\t.io_oeb(io_oeb),\n" \ - + "\t\t\t.analog_io(analog_io)\n" \ + + "\t\t\t.analog_io(analog_io),\n" \ + + "\t\t\t.user_clock2(user_clock2)\n" \ + "\t\t\t);\n"; # Wire the stimuli according to pin assignment write_testbench_wrapper_connection(tb_file, pin_data, 25) From 4b681b88a6d183179465ef2eca4284b907667ae8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 22:17:10 -0700 Subject: [PATCH 12/24] [Testbench] Fix the unconnected wbs_we_i pin --- TESTBENCH/common/post_pnr_wrapper_testbench_converter.py | 1 + 1 file changed, 1 insertion(+) diff --git a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py index f181544..7733f04 100644 --- a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py +++ b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py @@ -258,6 +258,7 @@ with open(args.post_pnr_testbench, "r") as wp: + "\t\t\t.wb_clk_i(wb_clk_i),\n" \ + "\t\t\t.wb_rst_i(wb_rst_i),\n" \ + "\t\t\t.wbs_stb_i(wbs_stb_i),\n" \ + + "\t\t\t.wbs_we_i(wbs_we_i),\n" \ + "\t\t\t.wbs_cyc_i(wbs_cyc_i),\n" \ + "\t\t\t.wbs_sel_i(wbs_sel_i),\n" \ + "\t\t\t.wbs_dat_i(wbs_dat_i),\n" \ From 50089e11f957253bfeb8b5c069c18ee8666ff732 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 22:20:15 -0700 Subject: [PATCH 13/24] [Testbench] Bug fix --- TESTBENCH/common/post_pnr_wrapper_testbench_converter.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py index 7733f04..9fda09a 100644 --- a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py +++ b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py @@ -236,6 +236,8 @@ with open(args.post_pnr_testbench, "r") as wp: + "wire [`MPRJ_IO_PADS-1:0] io_oeb;\n" \ + "// ---- Analog I/O pins ----\n" \ + "wire [`MPRJ_IO_PADS-8:0] analog_io;\n" + + "// ---- User clock pin ----\n" \ + + "wire [0:0] user_clock2;\n" # Skip all the lines about FPGA instanciation if (curr_line == "\tfpga_core FPGA_DUT (\n"): From 12c3e157bf63aa6cd979f2e701e0405bf83ebd29 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 22:32:36 -0700 Subject: [PATCH 14/24] [Testbench] Add a tempo fix on the analog pins --- .../post_pnr_wrapper_testbench_converter.py | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py index 9fda09a..3102d5c 100644 --- a/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py +++ b/TESTBENCH/common/post_pnr_wrapper_testbench_converter.py @@ -235,9 +235,13 @@ with open(args.post_pnr_testbench, "r") as wp: + "wire [`MPRJ_IO_PADS-1:0] io_out;\n" \ + "wire [`MPRJ_IO_PADS-1:0] io_oeb;\n" \ + "// ---- Analog I/O pins ----\n" \ - + "wire [`MPRJ_IO_PADS-8:0] analog_io;\n" + + "wire [`MPRJ_IO_PADS-8:0] analog_io;\n" \ + "// ---- User clock pin ----\n" \ + "wire [0:0] user_clock2;\n" + # TODO: This is a temporary fix for the flattened analog io port + # SHOULD BE REMOVED ABOUT UPDATED WRAPPER + for ipin in range(31): + line2output += "wire [0:0] analog_io_" + str(ipin) + "_;\n" # Skip all the lines about FPGA instanciation if (curr_line == "\tfpga_core FPGA_DUT (\n"): @@ -273,9 +277,15 @@ with open(args.post_pnr_testbench, "r") as wp: + "\t\t\t.io_in(io_in),\n" \ + "\t\t\t.io_out(io_out),\n" \ + "\t\t\t.io_oeb(io_oeb),\n" \ - + "\t\t\t.analog_io(analog_io),\n" \ - + "\t\t\t.user_clock2(user_clock2)\n" \ - + "\t\t\t);\n"; + #+ "\t\t\t.analog_io(analog_io),\n" \ + #+ "\t\t\t);\n"; + # TODO: This is a temporary fix for the flattened analog io port + # SHOULD BE REMOVED ABOUT UPDATED WRAPPER + for ipin in range(31): + line2output += ".analog_io_" + str(ipin) + "_(analog_io_" + str(ipin) + "_),\n" + + line2output += "\t\t\t.user_clock2(user_clock2)\n" + line2output += "\t\t\t);\n"; # Wire the stimuli according to pin assignment write_testbench_wrapper_connection(tb_file, pin_data, 25) From 931b93b83d9b294f6d58d058b933564bf49c7405 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 22:38:16 -0700 Subject: [PATCH 15/24] [Testbench] Now wrapper testbench conversion can be batched --- .../common/generate_post_pnr_testbenches.py | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/TESTBENCH/common/generate_post_pnr_testbenches.py b/TESTBENCH/common/generate_post_pnr_testbenches.py index d43a62d..bf58cda 100644 --- a/TESTBENCH/common/generate_post_pnr_testbenches.py +++ b/TESTBENCH/common/generate_post_pnr_testbenches.py @@ -31,6 +31,8 @@ logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.DEBUG) parser = argparse.ArgumentParser(description='Generate post-PnR testbenches for a given directory') parser.add_argument('--pre_pnr_testbench_dir_name', required=True, help='Specify the directory path for the pre-PnR Verilog testbenches') +parser.add_argument('--pin_assignment_file', required=True, + help='Specify the file path to the pin assignment JSON description as input') args = parser.parse_args() ##################################################################### @@ -75,3 +77,22 @@ for curr_pre_pnr_testbench_file in pre_pnr_testbench_files: logging.info("Done") logging.info("\nConverted " + str(num_converted_testbenches) + " testbenches.") + +##################################################################### +# Convert post-PnR testbenches to wrapper testbenches +##################################################################### +logging.info("Converting pre-PnR testbench to post-PnR testbench..."); +for curr_pre_pnr_testbench_file in pre_pnr_testbench_files: + curr_post_pnr_testbench_file = re.sub("_autocheck_top_tb.v$", "_post_pnr_autocheck_top_tb.v", curr_pre_pnr_testbench_file) + curr_post_pnr_testbench_file = re.sub("\/prepnr\/", "\/postpnr\/", curr_post_pnr_testbench_file) + curr_wrapper_testbench_file = re.sub("_autocheck_top_tb.v$", "_wrapper_autocheck_top_tb.v", curr_pre_pnr_testbench_file) + logging.info("Processing " + curr_post_pnr_testbench_file + " testbench:") + cmd = "python3 ./post_pnr_wrapper_testbench_converter.py " \ + + " --post_pnr_testbench " + curr_post_pnr_testbench_file \ + + " --pin_assignment_file " + args.pin_assignment_file \ + + " --wrapper_testbench " + curr_wrapper_testbench_file + subprocess.run(cmd, shell=True, check=True) + num_converted_testbenches += 1 + logging.info("Done") + +logging.info("\nConverted " + str(num_converted_testbenches) + " testbenches.") From 0ccc18d84842ca7976104d5b34b4b9ac69a25e6a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 22:48:01 -0700 Subject: [PATCH 16/24] [Testbench] Bug fix in the paths to generate wrapper testbenches --- TESTBENCH/common/generate_post_pnr_testbenches.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/TESTBENCH/common/generate_post_pnr_testbenches.py b/TESTBENCH/common/generate_post_pnr_testbenches.py index bf58cda..962cdef 100644 --- a/TESTBENCH/common/generate_post_pnr_testbenches.py +++ b/TESTBENCH/common/generate_post_pnr_testbenches.py @@ -85,7 +85,7 @@ logging.info("Converting pre-PnR testbench to post-PnR testbench..."); for curr_pre_pnr_testbench_file in pre_pnr_testbench_files: curr_post_pnr_testbench_file = re.sub("_autocheck_top_tb.v$", "_post_pnr_autocheck_top_tb.v", curr_pre_pnr_testbench_file) curr_post_pnr_testbench_file = re.sub("\/prepnr\/", "\/postpnr\/", curr_post_pnr_testbench_file) - curr_wrapper_testbench_file = re.sub("_autocheck_top_tb.v$", "_wrapper_autocheck_top_tb.v", curr_pre_pnr_testbench_file) + curr_wrapper_testbench_file = re.sub("_autocheck_top_tb.v$", "_wrapper_autocheck_top_tb.v", curr_post_pnr_testbench_file) logging.info("Processing " + curr_post_pnr_testbench_file + " testbench:") cmd = "python3 ./post_pnr_wrapper_testbench_converter.py " \ + " --post_pnr_testbench " + curr_post_pnr_testbench_file \ From 0bf5a400e861b2816ce1fbe70e49f78ebbb2dff1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 22:48:25 -0700 Subject: [PATCH 17/24] [Testbench] Add include netlists for wrapper testbenches --- .../and2_latch_post_pnr_wrapper_include_netlists.v | 3 +++ .../and2_or2_post_pnr_wrapper_include_netlists.v | 3 +++ .../routing_test_post_pnr_wrapper_include_netlists.v | 3 +++ 3 files changed, 9 insertions(+) create mode 100644 TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v create mode 100644 TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v create mode 100644 TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..8851916 --- /dev/null +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:92f909b526ee576979b1a02b23171c242ff03e62d862f06413b6a5236e5377cb +size 1478 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..7354521 --- /dev/null +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:825a6a406d866bda71202b39eb897b967484f3dc7c3cf7a62aa18791e54df573 +size 1474 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..7139452 --- /dev/null +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3adff4e62fe53b8cef99dc752bab3ebc6890445d6263b3aad5fdec154f53fbcf +size 1482 From fc3eadaf29e48f0b030b39bf6baa7dd8a2264259 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 22:58:48 -0700 Subject: [PATCH 18/24] [Testbench] Add SCFF test for wrapper --- .../postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v | 3 +++ .../scff_test_post_pnr_wrapper_include_netlists.v | 3 +++ 2 files changed, 6 insertions(+) create mode 100644 TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v create mode 100644 TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v new file mode 100644 index 0000000..fa2dc67 --- /dev/null +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:aa307fe506d4107e78867547f28e9533691c57b6ccea22f24afb389b7d61ce5a +size 29307 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..8f290f1 --- /dev/null +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:33fd521a78b634170da832cd9e481ffd8005682dee862c51c359b5edc6978e7a +size 1391 From 2b40d5fb4bc603bd24835947350311fd0330ccf8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 30 Nov 2020 09:34:26 -0700 Subject: [PATCH 19/24] [HDL] Bug fix --- .../scff_test_post_pnr_wrapper_include_netlists.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v index 8f290f1..5694280 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:33fd521a78b634170da832cd9e481ffd8005682dee862c51c359b5edc6978e7a -size 1391 +oid sha256:c3b64adf49892e8d7e7263273e76b566cb1f0922d404c224d550136d43b49178 +size 1487 From c70d5ac4f0dbf622dd3317b67553986feb1f8231 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 30 Nov 2020 09:42:31 -0700 Subject: [PATCH 20/24] [Testbench] Add ccff test wrapper testbench and include netlist --- .../postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v | 3 +++ .../ccff_test_post_pnr_wrapper_include_netlists.v | 3 +++ 2 files changed, 6 insertions(+) create mode 100644 TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v create mode 100644 TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v new file mode 100644 index 0000000..fb366da --- /dev/null +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ed96f64d008f69b13c352cefea841509291d29edf65fdad1f8d5ae5f2a972499 +size 29471 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..838b868 --- /dev/null +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:06bb3d6a1ee52298d3ac59ad73f16132b268c013b3cb411d0dfe6f033f6aed36 +size 1488 From e63cb7ca89ffc45012c15a5b02b44a698c503040 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 30 Nov 2020 10:23:30 -0700 Subject: [PATCH 21/24] [Testbench] Rename testbench top module to be compatible with verification scripts --- .../postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v | 4 ++-- .../postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v index fb366da..8505896 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ed96f64d008f69b13c352cefea841509291d29edf65fdad1f8d5ae5f2a972499 -size 29471 +oid sha256:4536eee5498c65f120e49e23ad8f5659ecfdefe6693c673920255cb087b3bd5b +size 29488 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v index fa2dc67..b2c7c8c 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:aa307fe506d4107e78867547f28e9533691c57b6ccea22f24afb389b7d61ce5a -size 29307 +oid sha256:3d8fd9493ad2339e27c6723fb601dde18b0c3698534b6241dd05de0af6c1d7aa +size 29324 From a900cba5a59b8d8175283a1091fda1e1ebf0b54d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 30 Nov 2020 10:29:05 -0700 Subject: [PATCH 22/24] [HDL] Bug fix in the pin assignment due to the conflicts on sc_tail and ccff_tail --- HDL/common/caravel_wrapper_pin_assignment_v1.0.json | 2 +- HDL/common/caravel_wrapper_pin_assignment_v1.1.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/HDL/common/caravel_wrapper_pin_assignment_v1.0.json b/HDL/common/caravel_wrapper_pin_assignment_v1.0.json index 5fd7fdd..b9cb0ff 100644 --- a/HDL/common/caravel_wrapper_pin_assignment_v1.0.json +++ b/HDL/common/caravel_wrapper_pin_assignment_v1.0.json @@ -142,7 +142,7 @@ "caravel_pin_index": ["36:36"] }, { - "fpga_pin_type": "sc_tail", + "fpga_pin_type": "ccff_tail", "fpga_pin_index": "0:0", "caravel_pin_type": ["output"], "caravel_pin_index": ["35:35"] diff --git a/HDL/common/caravel_wrapper_pin_assignment_v1.1.json b/HDL/common/caravel_wrapper_pin_assignment_v1.1.json index 901ffb3..abbff5b 100644 --- a/HDL/common/caravel_wrapper_pin_assignment_v1.1.json +++ b/HDL/common/caravel_wrapper_pin_assignment_v1.1.json @@ -154,7 +154,7 @@ "caravel_pin_index": ["36:36"] }, { - "fpga_pin_type": "sc_tail", + "fpga_pin_type": "ccff_tail", "fpga_pin_index": "0:0", "caravel_pin_type": ["output"], "caravel_pin_index": ["35:35"] From c638edfc14428cb4d3630d4043033c99e5092280 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 30 Nov 2020 10:33:50 -0700 Subject: [PATCH 23/24] [Testbench] Regenerate ccff/scff testbenches for wrapper --- .../postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v | 4 ++-- .../postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v index 8505896..6473c64 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4536eee5498c65f120e49e23ad8f5659ecfdefe6693c673920255cb087b3bd5b -size 29488 +oid sha256:a57416e9c828ad9ea0e3b5adb2fbe27fcf910e68083a2159563921f4cf5f8d35 +size 29490 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v index b2c7c8c..fd0453d 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3d8fd9493ad2339e27c6723fb601dde18b0c3698534b6241dd05de0af6c1d7aa -size 29324 +oid sha256:cc555c2a0ddb8412c57c88ab89a2a5c7d6cb9c525484113f9ac219c763daf4d2 +size 29326 From c676db1fe4a8d8ca3e9ec2bf85262a31d6675190 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 30 Nov 2020 11:18:42 -0700 Subject: [PATCH 24/24] [Testbench] Bug fix in the ccff post-pnr testbench template --- TESTBENCH/common/ccff_test_post_pnr.v | 4 ++-- .../postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/TESTBENCH/common/ccff_test_post_pnr.v b/TESTBENCH/common/ccff_test_post_pnr.v index 2650ddd..a1ab2ec 100644 --- a/TESTBENCH/common/ccff_test_post_pnr.v +++ b/TESTBENCH/common/ccff_test_post_pnr.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:860cd964c5f2a9f8681960048ba65ff373e8c20e81ce5d0b85eabc1ebecd33d0 -size 5881 +oid sha256:b539cd91f8c0e2abca88387354c6cf211da149bf609b80671680fa9117611912 +size 5905 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v index 6473c64..195e68f 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a57416e9c828ad9ea0e3b5adb2fbe27fcf910e68083a2159563921f4cf5f8d35 -size 29490 +oid sha256:a48432026dba12e9c3a98dbbaa9f9166e975b92617e1718d338d4d28dd809179 +size 29505