diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v
new file mode 100644
index 0000000..8851916
--- /dev/null
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:92f909b526ee576979b1a02b23171c242ff03e62d862f06413b6a5236e5377cb
+size 1478
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v
new file mode 100644
index 0000000..7354521
--- /dev/null
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:825a6a406d866bda71202b39eb897b967484f3dc7c3cf7a62aa18791e54df573
+size 1474
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v
new file mode 100644
index 0000000..7139452
--- /dev/null
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:3adff4e62fe53b8cef99dc752bab3ebc6890445d6263b3aad5fdec154f53fbcf
+size 1482