mirror of https://github.com/lnis-uofu/SOFA.git
Merge pull request #33 from LNIS-Projects/xt_dev
Caravel Wrapper Update: Use Wishbone Clock as a Regular Input of FPGA
This commit is contained in:
ganeshgore
GitHub
commit
09c7dba92a
|
|
@ -1,6 +1,6 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
|
||||
<svg xmlns:xl="http://www.w3.org/1999/xlink" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns="http://www.w3.org/2000/svg" version="1.1" viewBox="156.75 679.5 703.8047 524.9336" width="703.8047" height="524.9336">
|
||||
<svg xmlns:xl="http://www.w3.org/1999/xlink" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns="http://www.w3.org/2000/svg" version="1.1" viewBox="156.75 679.5 703.8047 543.9336" width="703.8047" height="543.9336">
|
||||
<defs>
|
||||
<font-face font-family="Times" font-size="16" panose-1="0 0 8 0 0 0 0 2 0 0" units-per-em="1000" underline-position="-66.40625" underline-thickness="67.87109" slope="0" x-height="460.4492" cap-height="675.78125" ascent="750" descent="-250" font-weight="700">
|
||||
<font-face-src>
|
||||
|
|
@ -28,7 +28,7 @@
|
|||
</font-face-src>
|
||||
</font-face>
|
||||
</defs>
|
||||
<metadata> Produced by OmniGraffle 7.18\n2020-11-19 03:30:43 +0000</metadata>
|
||||
<metadata> Produced by OmniGraffle 7.18\n2020-11-21 01:25:48 +0000</metadata>
|
||||
<g id="wishbone_mode" fill="none" stroke="none" stroke-opacity="1" stroke-dasharray="none" fill-opacity="1">
|
||||
<title>wishbone_mode</title>
|
||||
<g id="wishbone_mode_base">
|
||||
|
|
@ -150,23 +150,18 @@
|
|||
</g>
|
||||
<g id="Graphic_453">
|
||||
<text transform="translate(161.75 947.5938)" fill="black">
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="4.878906" y="15">Caravel Wishbone rst_i</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="0" y="34">Caravel Wishbone ack_o</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.7773438" y="53">Caravel Wishbone cyc_i</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="3.5429688" y="72">Caravel Wishbone stb_i</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="3.1054688" y="15">Caravel Wishbone clk_i</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="4.878906" y="34">Caravel Wishbone rst_i</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="0" y="53">Caravel Wishbone ack_o</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.7773438" y="72">Caravel Wishbone cyc_i</tspan>
|
||||
</text>
|
||||
</g>
|
||||
<g id="Line_454">
|
||||
<line x1="381.40053" y1="972.6693" x2="381.70884" y2="985.5026" marker-end="url(#DimensionArrow_Marker)" marker-start="url(#DimensionArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
|
||||
</g>
|
||||
<g id="Graphic_459">
|
||||
<path d="M 331.6875 967.2734 L 331.6875 954.2734 L 357.57812 954.2734 L 357.57812 947.7734 L 370.57812 960.7734 L 357.57812 973.7734 L 357.57812 967.2734 Z" fill="#c0ffff"/>
|
||||
<path d="M 331.6875 967.2734 L 331.6875 954.2734 L 357.57812 954.2734 L 357.57812 947.7734 L 370.57812 960.7734 L 357.57812 973.7734 L 357.57812 967.2734 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
|
||||
</g>
|
||||
<g id="Graphic_460">
|
||||
<text transform="translate(339.41406 1013.6836)" fill="black">
|
||||
<tspan font-family="Times" font-size="16" font-style="italic" font-weight="400" fill="black" x="0" y="15">1 bit</tspan>
|
||||
</text>
|
||||
<path d="M 329.39062 982.2734 L 329.39062 969.2734 L 355.28125 969.2734 L 355.28125 962.7734 L 368.28125 975.7734 L 355.28125 988.7734 L 355.28125 982.2734 Z" fill="#c0ffff"/>
|
||||
<path d="M 329.39062 982.2734 L 329.39062 969.2734 L 355.28125 969.2734 L 355.28125 962.7734 L 368.28125 975.7734 L 355.28125 988.7734 L 355.28125 982.2734 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
|
||||
</g>
|
||||
<g id="Graphic_462">
|
||||
<path d="M 470.98047 1073.4336 L 456.48047 1073.4336 L 456.48047 1088.4336 L 449.23047 1088.4336 L 463.73047 1099.4336 L 478.23047 1088.4336 L 470.98047 1088.4336 Z" fill="#c0ffff"/>
|
||||
|
|
@ -210,11 +205,12 @@
|
|||
</g>
|
||||
<g id="Graphic_471">
|
||||
<text transform="translate(396.1709 1104.4336)" fill="black">
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="21.773438" y="15">Caravel Wishbone we_i</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.3359375" y="34">Caravel Wishbone adr_i[31:0]</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.7773438" y="53">Caravel Wishbone dat_i[31:0]</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="0" y="72">Caravel Wishbone dat_o[31:0]</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="6.6640625" y="91">Caravel Wishbone sel_i[3:0]</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="21.765625" y="15">Caravel Wishbone stb_i</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="21.773438" y="34">Caravel Wishbone we_i</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.3359375" y="53">Caravel Wishbone adr_i[31:0]</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.7773438" y="72">Caravel Wishbone dat_i[31:0]</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="0" y="91">Caravel Wishbone dat_o[31:0]</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="6.6640625" y="110">Caravel Wishbone sel_i[3:0]</tspan>
|
||||
</text>
|
||||
</g>
|
||||
<g id="Graphic_474">
|
||||
|
|
@ -223,7 +219,7 @@
|
|||
</g>
|
||||
<g id="Graphic_473">
|
||||
<text transform="translate(555.63965 1075.4688)" fill="black">
|
||||
<tspan font-family="Times" font-size="16" font-style="italic" font-weight="400" fill="black" x="0" y="15">69 bit</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-style="italic" font-weight="400" fill="black" x="0" y="15">70 bit</tspan>
|
||||
</text>
|
||||
</g>
|
||||
<g id="Graphic_476">
|
||||
|
|
@ -233,21 +229,26 @@
|
|||
</g>
|
||||
<g id="Graphic_478">
|
||||
<text transform="translate(571.9258 1025.5938)" fill="black">
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="2" y="15">gpio[31] </tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="2" y="15">gpio[30] </tspan>
|
||||
</text>
|
||||
</g>
|
||||
<g id="Line_479">
|
||||
<line x1="433.6461" y1="1058.5" x2="600.1" y2="1058.5" marker-end="url(#DimensionArrow_Marker)" marker-start="url(#DimensionArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
|
||||
</g>
|
||||
<g id="Graphic_480">
|
||||
<path d="M 368.28125 1003.6875 L 368.28125 990.6875 L 342.39062 990.6875 L 342.39062 984.1875 L 329.39062 997.1875 L 342.39062 1010.1875 L 342.39062 1003.6875 Z" fill="#c0ffff"/>
|
||||
<path d="M 368.28125 1003.6875 L 368.28125 990.6875 L 342.39062 990.6875 L 342.39062 984.1875 L 329.39062 997.1875 L 342.39062 1010.1875 L 342.39062 1003.6875 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
|
||||
</g>
|
||||
<g id="Graphic_481">
|
||||
<text transform="translate(331.66406 926.7305)" fill="black">
|
||||
<text transform="translate(331.66406 943.25)" fill="black">
|
||||
<tspan font-family="Times" font-size="16" font-style="italic" font-weight="400" fill="black" x="0" y="15">3 bit</tspan>
|
||||
</text>
|
||||
</g>
|
||||
<g id="Graphic_482">
|
||||
<path d="M 368.28125 1010.625 L 368.28125 997.625 L 342.39062 997.625 L 342.39062 991.125 L 329.39062 1004.125 L 342.39062 1017.125 L 342.39062 1010.625 Z" fill="#c0ffff"/>
|
||||
<path d="M 368.28125 1010.625 L 368.28125 997.625 L 342.39062 997.625 L 342.39062 991.125 L 329.39062 1004.125 L 342.39062 1017.125 L 342.39062 1010.625 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
|
||||
</g>
|
||||
<g id="Graphic_483">
|
||||
<text transform="translate(334.39062 1022.2266)" fill="black">
|
||||
<tspan font-family="Times" font-size="16" font-style="italic" font-weight="400" fill="black" x="0" y="15">1 bit</tspan>
|
||||
</text>
|
||||
</g>
|
||||
</g>
|
||||
</g>
|
||||
</svg>
|
||||
|
|
|
|||
|
Before Width: | Height: | Size: 16 KiB After Width: | Height: | Size: 17 KiB |
|
|
@ -1,6 +1,6 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
|
||||
<svg xmlns:xl="http://www.w3.org/1999/xlink" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns="http://www.w3.org/2000/svg" version="1.1" viewBox="90.77832 679.5 887.4385 701.1582" width="887.4385" height="701.1582">
|
||||
<svg xmlns:xl="http://www.w3.org/1999/xlink" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns="http://www.w3.org/2000/svg" version="1.1" viewBox="115.79736 679.5 862.4194 701.1582" width="862.4194" height="701.1582">
|
||||
<defs>
|
||||
<font-face font-family="Times" font-size="16" panose-1="0 0 5 0 0 0 0 2 0 0" units-per-em="1000" underline-position="-75.68359" underline-thickness="49.316406" slope="0" x-height="453.6133" cap-height="661.6211" ascent="750" descent="-250" font-weight="400">
|
||||
<font-face-src>
|
||||
|
|
@ -32,25 +32,12 @@
|
|||
<path d="M -1.8666667 0 L 0 .7 L 0 -.7 Z" fill="currentColor" stroke="currentColor" stroke-width="1"/>
|
||||
</g>
|
||||
</marker>
|
||||
<marker orient="auto" overflow="visible" markerUnits="strokeWidth" id="FilledArrow_Marker_2" stroke-linejoin="miter" stroke-miterlimit="10" viewBox="-1 -4 10 8" markerWidth="10" markerHeight="8" color="black">
|
||||
<g>
|
||||
<path d="M 8 0 L 0 -3 L 0 3 Z" fill="currentColor" stroke="currentColor" stroke-width="1"/>
|
||||
</g>
|
||||
</marker>
|
||||
<marker orient="auto" overflow="visible" markerUnits="strokeWidth" id="FilledArrow_Marker_3" stroke-linejoin="miter" stroke-miterlimit="10" viewBox="-4 -2 6 4" markerWidth="6" markerHeight="4" color="#ff2600">
|
||||
<g>
|
||||
<path d="M -2.4 0 L 0 .9 L 0 -.9 Z" fill="currentColor" stroke="currentColor" stroke-width="1"/>
|
||||
</g>
|
||||
</marker>
|
||||
</defs>
|
||||
<metadata> Produced by OmniGraffle 7.18\n2020-11-19 03:30:21 +0000</metadata>
|
||||
<metadata> Produced by OmniGraffle 7.18\n2020-11-21 01:05:14 +0000</metadata>
|
||||
<g id="switch" fill="none" stroke="none" stroke-opacity="1" stroke-dasharray="none" fill-opacity="1">
|
||||
<title>switch</title>
|
||||
<g id="switch_base">
|
||||
<title>base</title>
|
||||
<g id="Graphic_555">
|
||||
<path d="M 91.77832 975.25 L 289.93457 975.25 L 289.93457 1110.375 L 91.77832 1110.375 Z" stroke="#ff2600" stroke-linecap="round" stroke-linejoin="round" stroke-dasharray="8.0,8.0" stroke-width="2"/>
|
||||
</g>
|
||||
<g id="Graphic_535">
|
||||
<text transform="translate(120.79736 899.1797)" fill="black">
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="0" y="15">CCFF_TAIL -> Caravel GPIO[35]</tspan>
|
||||
|
|
@ -283,16 +270,17 @@
|
|||
<g id="Graphic_497"/>
|
||||
<g id="Graphic_496"/>
|
||||
<g id="Graphic_495">
|
||||
<text transform="translate(237.22656 1223.7031)" fill="black">
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="3.1015625" y="15">Caravel Wishbone rst_i</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.765625" y="34">Caravel Wishbone stb_i</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="0" y="53">Caravel Wishbone cyc_i</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.7734375" y="72">Caravel Wishbone we_i</tspan>
|
||||
<text transform="translate(231.3086 1205.0293)" fill="black">
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.328125" y="15">Caravel Wishbone clk_i</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="3.1015625" y="34">Caravel Wishbone rst_i</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.765625" y="53">Caravel Wishbone stb_i</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="0" y="72">Caravel Wishbone cyc_i</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.7734375" y="91">Caravel Wishbone we_i</tspan>
|
||||
</text>
|
||||
</g>
|
||||
<g id="Graphic_499">
|
||||
<path d="M 378.16797 1160.5625 L 392.66797 1178.7246 L 385 1178.7246 L 385 1202.1895 L 392.66797 1202.1895 L 378.16797 1220.3516 L 363.66797 1202.1895 L 371.33594 1202.1895 L 371.33594 1178.7246 L 363.66797 1178.7246 Z" fill="#ffc0c0"/>
|
||||
<path d="M 378.16797 1160.5625 L 392.66797 1178.7246 L 385 1178.7246 L 385 1202.1895 L 392.66797 1202.1895 L 378.16797 1220.3516 L 363.66797 1202.1895 L 371.33594 1202.1895 L 371.33594 1178.7246 L 363.66797 1178.7246 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
|
||||
<path d="M 399.19727 1161.1016 L 413.69727 1179.2637 L 406.0293 1179.2637 L 406.0293 1202.7285 L 413.69727 1202.7285 L 399.19727 1220.8906 L 384.69727 1202.7285 L 392.36523 1202.7285 L 392.36523 1179.2637 L 384.69727 1179.2637 Z" fill="#ffc0c0"/>
|
||||
<path d="M 399.19727 1161.1016 L 413.69727 1179.2637 L 406.0293 1179.2637 L 406.0293 1202.7285 L 413.69727 1202.7285 L 399.19727 1220.8906 L 384.69727 1202.7285 L 392.36523 1202.7285 L 392.36523 1179.2637 L 384.69727 1179.2637 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
|
||||
</g>
|
||||
<g id="Graphic_500">
|
||||
<text transform="translate(307.16846 1318.4707)" fill="#ff2600">
|
||||
|
|
@ -336,8 +324,8 @@
|
|||
</text>
|
||||
</g>
|
||||
<g id="Graphic_539">
|
||||
<text transform="translate(399.82812 1169.5566)" fill="black">
|
||||
<tspan font-family="Times" font-size="16" font-style="italic" font-weight="400" fill="black" x="0" y="15">105 bit</tspan>
|
||||
<text transform="translate(422.03906 1169.5566)" fill="black">
|
||||
<tspan font-family="Times" font-size="16" font-style="italic" font-weight="400" fill="black" x="0" y="15">106 bit</tspan>
|
||||
</text>
|
||||
</g>
|
||||
<g id="Graphic_540">
|
||||
|
|
@ -350,7 +338,7 @@
|
|||
<path d="M 532.4336 1132.9941 L 518.0664 1132.9941 L 518.0664 1078.7773 L 510.75 1078.7773 L 525.25 1063.8926 L 539.75 1078.7773 L 532.4336 1078.7773 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
|
||||
</g>
|
||||
<g id="Graphic_542">
|
||||
<text transform="translate(403.58594 1205.8574)" fill="black">
|
||||
<text transform="translate(409.6797 1205.0293)" fill="black">
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="6.6640625" y="15">Caravel Wishbone sel_i[3:0]</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.7773438" y="34">Caravel Wishbone dat_i[31:0]</tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.3359375" y="53">Caravel Wishbone adr_i[31:0]</tspan>
|
||||
|
|
@ -358,51 +346,6 @@
|
|||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="0" y="91">Caravel Wishbone dat_o[31:0]</tspan>
|
||||
</text>
|
||||
</g>
|
||||
<g id="Graphic_544">
|
||||
<path d="M 199.0205 1010.5215 L 199.0205 1104.959 L 219.97559 1086.0715 L 219.97559 1029.409 Z" fill="#c0ffc0"/>
|
||||
<path d="M 199.0205 1010.5215 L 199.0205 1104.959 L 219.97559 1086.0715 L 219.97559 1029.409 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
|
||||
</g>
|
||||
<g id="Graphic_545">
|
||||
<text transform="translate(96.77832 1005.2734)" fill="black">
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="9.246094" y="15">Caravel </tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="2" y="34">Wishbone </tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="18.125" y="53">clk_i</tspan>
|
||||
</text>
|
||||
</g>
|
||||
<g id="Graphic_546">
|
||||
<text transform="translate(252.93457 1048.2402)" fill="black">
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="0" y="15">CLK</tspan>
|
||||
</text>
|
||||
</g>
|
||||
<g id="Graphic_547">
|
||||
<text transform="translate(98.90332 1063.2402)" fill="black">
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="7.121094" y="15">Caravel </tspan>
|
||||
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="0" y="34">GPIO[36]</tspan>
|
||||
</text>
|
||||
</g>
|
||||
<g id="Line_549">
|
||||
<line x1="170.0205" y1="1030.3574" x2="189.12075" y2="1030.4912" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
|
||||
</g>
|
||||
<g id="Line_550">
|
||||
<line x1="171.06152" y1="1076.086" x2="190.16177" y2="1076.2197" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
|
||||
</g>
|
||||
<g id="Line_551">
|
||||
<line x1="219.97559" y1="1057.2402" x2="239.07583" y2="1057.374" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
|
||||
</g>
|
||||
<g id="Line_552">
|
||||
<line x1="214.0657" y1="1121.4717" x2="214.02285" y2="1102.9" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
|
||||
</g>
|
||||
<g id="Graphic_553">
|
||||
<path d="M 172.125 917.2021 L 351.60205 917.2021 L 351.60205 938.1572 L 172.125 938.1572 Z" stroke="#ff2600" stroke-linecap="round" stroke-linejoin="round" stroke-dasharray="8.0,8.0" stroke-width="2"/>
|
||||
</g>
|
||||
<g id="Line_554">
|
||||
<line x1="201.6689" y1="969.1761" x2="245.21422" y2="939.1572" marker-start="url(#FilledArrow_Marker_3)" stroke="#ff2600" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
|
||||
</g>
|
||||
<g id="Graphic_556">
|
||||
<text transform="translate(98.90332 980.25)" fill="#ff2600">
|
||||
<tspan font-family="Times" font-size="16" font-weight="700" fill="#ff2600" x="0" y="15">Clock Switch Circuitry</tspan>
|
||||
</text>
|
||||
</g>
|
||||
</g>
|
||||
</g>
|
||||
</svg>
|
||||
|
|
|
|||
|
Before Width: | Height: | Size: 29 KiB After Width: | Height: | Size: 25 KiB |
|
|
@ -39,7 +39,7 @@ Accelerator Mode
|
|||
When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor.
|
||||
:numref:`fig_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations.
|
||||
|
||||
.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[21:30] are not connected.
|
||||
.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[21:29] are not connected.
|
||||
|
||||
.. warning:: The FPGA does not contain a Wishbone slave IP. Users have to implement a soft Wishbone slave when use the FPGA as an accelerator.
|
||||
|
||||
|
|
|
|||
|
|
@ -112,251 +112,251 @@ module fpga_top (
|
|||
|
||||
// Wire-bond RIGHT, BOTTOM, LEFT side I/O of FPGA to BOTTOM-side of Caravel interface
|
||||
// Autogenerate code start
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX (.S(la_wb_switch), .A1(wb_rst_i), .A0(la_data_in[13]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX (.S(wb_la_switch), .A1(wb_clk_i), .A0(la_data_in[13]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135]));
|
||||
assign la_data_out[13] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] = la_data_in[14];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_134_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134]), .Z(wbs_ack_o));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_134_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134]), .Z(la_data_out[14]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_133_MUX (.S(la_wb_switch), .A1(wbs_cyc_i), .A0(la_data_in[15]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133]));
|
||||
assign la_data_out[15] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX (.S(la_wb_switch), .A1(wbs_stb_i), .A0(la_data_in[16]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX (.S(wb_la_switch), .A1(wb_rst_i), .A0(la_data_in[14]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134]));
|
||||
assign la_data_out[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[15];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(wbs_ack_o));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(la_data_out[15]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX (.S(wb_la_switch), .A1(wbs_cyc_i), .A0(la_data_in[16]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132]));
|
||||
assign la_data_out[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX (.S(la_wb_switch), .A1(wbs_we_i), .A0(la_data_in[17]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX (.S(wb_la_switch), .A1(wbs_stb_i), .A0(la_data_in[17]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131]));
|
||||
assign la_data_out[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX (.S(la_wb_switch), .A1(wbs_sel_i[0]), .A0(la_data_in[18]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX (.S(wb_la_switch), .A1(wbs_we_i), .A0(la_data_in[18]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130]));
|
||||
assign la_data_out[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX (.S(la_wb_switch), .A1(wbs_sel_i[1]), .A0(la_data_in[19]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX (.S(wb_la_switch), .A1(wbs_sel_i[0]), .A0(la_data_in[19]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129]));
|
||||
assign la_data_out[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX (.S(la_wb_switch), .A1(wbs_sel_i[2]), .A0(la_data_in[20]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX (.S(wb_la_switch), .A1(wbs_sel_i[1]), .A0(la_data_in[20]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128]));
|
||||
assign la_data_out[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX (.S(la_wb_switch), .A1(wbs_sel_i[3]), .A0(la_data_in[21]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX (.S(wb_la_switch), .A1(wbs_sel_i[2]), .A0(la_data_in[21]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127]));
|
||||
assign la_data_out[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX (.S(la_wb_switch), .A1(wbs_adr_i[0]), .A0(la_data_in[22]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX (.S(wb_la_switch), .A1(wbs_sel_i[3]), .A0(la_data_in[22]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126]));
|
||||
assign la_data_out[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX (.S(la_wb_switch), .A1(wbs_adr_i[1]), .A0(la_data_in[23]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX (.S(wb_la_switch), .A1(wbs_adr_i[0]), .A0(la_data_in[23]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125]));
|
||||
assign la_data_out[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX (.S(la_wb_switch), .A1(wbs_adr_i[2]), .A0(la_data_in[24]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX (.S(wb_la_switch), .A1(wbs_adr_i[1]), .A0(la_data_in[24]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124]));
|
||||
assign la_data_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX (.S(la_wb_switch), .A1(wbs_adr_i[3]), .A0(la_data_in[25]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX (.S(wb_la_switch), .A1(wbs_adr_i[2]), .A0(la_data_in[25]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123]));
|
||||
assign la_data_out[25] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX (.S(la_wb_switch), .A1(wbs_adr_i[4]), .A0(la_data_in[26]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX (.S(wb_la_switch), .A1(wbs_adr_i[3]), .A0(la_data_in[26]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122]));
|
||||
assign la_data_out[26] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX (.S(la_wb_switch), .A1(wbs_adr_i[5]), .A0(la_data_in[27]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX (.S(wb_la_switch), .A1(wbs_adr_i[4]), .A0(la_data_in[27]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121]));
|
||||
assign la_data_out[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX (.S(la_wb_switch), .A1(wbs_adr_i[6]), .A0(la_data_in[28]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX (.S(wb_la_switch), .A1(wbs_adr_i[5]), .A0(la_data_in[28]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120]));
|
||||
assign la_data_out[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX (.S(la_wb_switch), .A1(wbs_adr_i[7]), .A0(la_data_in[29]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX (.S(wb_la_switch), .A1(wbs_adr_i[6]), .A0(la_data_in[29]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119]));
|
||||
assign la_data_out[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX (.S(la_wb_switch), .A1(wbs_adr_i[8]), .A0(la_data_in[30]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX (.S(wb_la_switch), .A1(wbs_adr_i[7]), .A0(la_data_in[30]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118]));
|
||||
assign la_data_out[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX (.S(la_wb_switch), .A1(wbs_adr_i[9]), .A0(la_data_in[31]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX (.S(wb_la_switch), .A1(wbs_adr_i[8]), .A0(la_data_in[31]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117]));
|
||||
assign la_data_out[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX (.S(la_wb_switch), .A1(wbs_adr_i[10]), .A0(la_data_in[32]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX (.S(wb_la_switch), .A1(wbs_adr_i[9]), .A0(la_data_in[32]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116]));
|
||||
assign la_data_out[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX (.S(la_wb_switch), .A1(wbs_adr_i[11]), .A0(la_data_in[33]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX (.S(wb_la_switch), .A1(wbs_adr_i[10]), .A0(la_data_in[33]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115]));
|
||||
assign la_data_out[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX (.S(la_wb_switch), .A1(wbs_adr_i[12]), .A0(la_data_in[34]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX (.S(wb_la_switch), .A1(wbs_adr_i[11]), .A0(la_data_in[34]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114]));
|
||||
assign la_data_out[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX (.S(la_wb_switch), .A1(wbs_adr_i[13]), .A0(la_data_in[35]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX (.S(wb_la_switch), .A1(wbs_adr_i[12]), .A0(la_data_in[35]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113]));
|
||||
assign la_data_out[35] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX (.S(la_wb_switch), .A1(wbs_adr_i[14]), .A0(la_data_in[36]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX (.S(wb_la_switch), .A1(wbs_adr_i[13]), .A0(la_data_in[36]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112]));
|
||||
assign la_data_out[36] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX (.S(la_wb_switch), .A1(wbs_adr_i[15]), .A0(la_data_in[37]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX (.S(wb_la_switch), .A1(wbs_adr_i[14]), .A0(la_data_in[37]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111]));
|
||||
assign la_data_out[37] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX (.S(la_wb_switch), .A1(wbs_adr_i[16]), .A0(la_data_in[38]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX (.S(wb_la_switch), .A1(wbs_adr_i[15]), .A0(la_data_in[38]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110]));
|
||||
assign la_data_out[38] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX (.S(la_wb_switch), .A1(wbs_adr_i[17]), .A0(la_data_in[39]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX (.S(wb_la_switch), .A1(wbs_adr_i[16]), .A0(la_data_in[39]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109]));
|
||||
assign la_data_out[39] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX (.S(la_wb_switch), .A1(wbs_adr_i[18]), .A0(la_data_in[40]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX (.S(wb_la_switch), .A1(wbs_adr_i[17]), .A0(la_data_in[40]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108]));
|
||||
assign la_data_out[40] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX (.S(la_wb_switch), .A1(wbs_adr_i[19]), .A0(la_data_in[41]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX (.S(wb_la_switch), .A1(wbs_adr_i[18]), .A0(la_data_in[41]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107]));
|
||||
assign la_data_out[41] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX (.S(la_wb_switch), .A1(wbs_adr_i[20]), .A0(la_data_in[42]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX (.S(wb_la_switch), .A1(wbs_adr_i[19]), .A0(la_data_in[42]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106]));
|
||||
assign la_data_out[42] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX (.S(la_wb_switch), .A1(wbs_adr_i[21]), .A0(la_data_in[43]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX (.S(wb_la_switch), .A1(wbs_adr_i[20]), .A0(la_data_in[43]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105]));
|
||||
assign la_data_out[43] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX (.S(la_wb_switch), .A1(wbs_adr_i[22]), .A0(la_data_in[44]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX (.S(wb_la_switch), .A1(wbs_adr_i[21]), .A0(la_data_in[44]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104]));
|
||||
assign la_data_out[44] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX (.S(la_wb_switch), .A1(wbs_adr_i[23]), .A0(la_data_in[45]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX (.S(wb_la_switch), .A1(wbs_adr_i[22]), .A0(la_data_in[45]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103]));
|
||||
assign la_data_out[45] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX (.S(la_wb_switch), .A1(wbs_adr_i[24]), .A0(la_data_in[46]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX (.S(wb_la_switch), .A1(wbs_adr_i[23]), .A0(la_data_in[46]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102]));
|
||||
assign la_data_out[46] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX (.S(la_wb_switch), .A1(wbs_adr_i[25]), .A0(la_data_in[47]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX (.S(wb_la_switch), .A1(wbs_adr_i[24]), .A0(la_data_in[47]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101]));
|
||||
assign la_data_out[47] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX (.S(la_wb_switch), .A1(wbs_adr_i[26]), .A0(la_data_in[48]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX (.S(wb_la_switch), .A1(wbs_adr_i[25]), .A0(la_data_in[48]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100]));
|
||||
assign la_data_out[48] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX (.S(la_wb_switch), .A1(wbs_adr_i[27]), .A0(la_data_in[49]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX (.S(wb_la_switch), .A1(wbs_adr_i[26]), .A0(la_data_in[49]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99]));
|
||||
assign la_data_out[49] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX (.S(la_wb_switch), .A1(wbs_adr_i[28]), .A0(la_data_in[50]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX (.S(wb_la_switch), .A1(wbs_adr_i[27]), .A0(la_data_in[50]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98]));
|
||||
assign la_data_out[50] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX (.S(la_wb_switch), .A1(wbs_adr_i[29]), .A0(la_data_in[51]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX (.S(wb_la_switch), .A1(wbs_adr_i[28]), .A0(la_data_in[51]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97]));
|
||||
assign la_data_out[51] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX (.S(la_wb_switch), .A1(wbs_adr_i[30]), .A0(la_data_in[52]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX (.S(wb_la_switch), .A1(wbs_adr_i[29]), .A0(la_data_in[52]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96]));
|
||||
assign la_data_out[52] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX (.S(la_wb_switch), .A1(wbs_adr_i[31]), .A0(la_data_in[53]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX (.S(wb_la_switch), .A1(wbs_adr_i[30]), .A0(la_data_in[53]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95]));
|
||||
assign la_data_out[53] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX (.S(la_wb_switch), .A1(wbs_dat_i[0]), .A0(la_data_in[54]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX (.S(wb_la_switch), .A1(wbs_adr_i[31]), .A0(la_data_in[54]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94]));
|
||||
assign la_data_out[54] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX (.S(la_wb_switch), .A1(wbs_dat_i[1]), .A0(la_data_in[55]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX (.S(wb_la_switch), .A1(wbs_dat_i[0]), .A0(la_data_in[55]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93]));
|
||||
assign la_data_out[55] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX (.S(la_wb_switch), .A1(wbs_dat_i[2]), .A0(la_data_in[56]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX (.S(wb_la_switch), .A1(wbs_dat_i[1]), .A0(la_data_in[56]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92]));
|
||||
assign la_data_out[56] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX (.S(la_wb_switch), .A1(wbs_dat_i[3]), .A0(la_data_in[57]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX (.S(wb_la_switch), .A1(wbs_dat_i[2]), .A0(la_data_in[57]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91]));
|
||||
assign la_data_out[57] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX (.S(la_wb_switch), .A1(wbs_dat_i[4]), .A0(la_data_in[58]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX (.S(wb_la_switch), .A1(wbs_dat_i[3]), .A0(la_data_in[58]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90]));
|
||||
assign la_data_out[58] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX (.S(la_wb_switch), .A1(wbs_dat_i[5]), .A0(la_data_in[59]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX (.S(wb_la_switch), .A1(wbs_dat_i[4]), .A0(la_data_in[59]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89]));
|
||||
assign la_data_out[59] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX (.S(la_wb_switch), .A1(wbs_dat_i[6]), .A0(la_data_in[60]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX (.S(wb_la_switch), .A1(wbs_dat_i[5]), .A0(la_data_in[60]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88]));
|
||||
assign la_data_out[60] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX (.S(la_wb_switch), .A1(wbs_dat_i[7]), .A0(la_data_in[61]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX (.S(wb_la_switch), .A1(wbs_dat_i[6]), .A0(la_data_in[61]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87]));
|
||||
assign la_data_out[61] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX (.S(la_wb_switch), .A1(wbs_dat_i[8]), .A0(la_data_in[62]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX (.S(wb_la_switch), .A1(wbs_dat_i[7]), .A0(la_data_in[62]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86]));
|
||||
assign la_data_out[62] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX (.S(la_wb_switch), .A1(wbs_dat_i[9]), .A0(la_data_in[63]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX (.S(wb_la_switch), .A1(wbs_dat_i[8]), .A0(la_data_in[63]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85]));
|
||||
assign la_data_out[63] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX (.S(la_wb_switch), .A1(wbs_dat_i[10]), .A0(la_data_in[64]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX (.S(wb_la_switch), .A1(wbs_dat_i[9]), .A0(la_data_in[64]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84]));
|
||||
assign la_data_out[64] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX (.S(la_wb_switch), .A1(wbs_dat_i[11]), .A0(la_data_in[65]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX (.S(wb_la_switch), .A1(wbs_dat_i[10]), .A0(la_data_in[65]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83]));
|
||||
assign la_data_out[65] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX (.S(la_wb_switch), .A1(wbs_dat_i[12]), .A0(la_data_in[66]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX (.S(wb_la_switch), .A1(wbs_dat_i[11]), .A0(la_data_in[66]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82]));
|
||||
assign la_data_out[66] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX (.S(la_wb_switch), .A1(wbs_dat_i[13]), .A0(la_data_in[67]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX (.S(wb_la_switch), .A1(wbs_dat_i[12]), .A0(la_data_in[67]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81]));
|
||||
assign la_data_out[67] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX (.S(la_wb_switch), .A1(wbs_dat_i[14]), .A0(la_data_in[68]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX (.S(wb_la_switch), .A1(wbs_dat_i[13]), .A0(la_data_in[68]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80]));
|
||||
assign la_data_out[68] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX (.S(la_wb_switch), .A1(wbs_dat_i[15]), .A0(la_data_in[69]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX (.S(wb_la_switch), .A1(wbs_dat_i[14]), .A0(la_data_in[69]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79]));
|
||||
assign la_data_out[69] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX (.S(la_wb_switch), .A1(wbs_dat_i[16]), .A0(la_data_in[70]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX (.S(wb_la_switch), .A1(wbs_dat_i[15]), .A0(la_data_in[70]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78]));
|
||||
assign la_data_out[70] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX (.S(la_wb_switch), .A1(wbs_dat_i[17]), .A0(la_data_in[71]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX (.S(wb_la_switch), .A1(wbs_dat_i[16]), .A0(la_data_in[71]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77]));
|
||||
assign la_data_out[71] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX (.S(la_wb_switch), .A1(wbs_dat_i[18]), .A0(la_data_in[72]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX (.S(wb_la_switch), .A1(wbs_dat_i[17]), .A0(la_data_in[72]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76]));
|
||||
assign la_data_out[72] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX (.S(la_wb_switch), .A1(wbs_dat_i[19]), .A0(la_data_in[73]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX (.S(wb_la_switch), .A1(wbs_dat_i[18]), .A0(la_data_in[73]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75]));
|
||||
assign la_data_out[73] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX (.S(la_wb_switch), .A1(wbs_dat_i[20]), .A0(la_data_in[74]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX (.S(wb_la_switch), .A1(wbs_dat_i[19]), .A0(la_data_in[74]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74]));
|
||||
assign la_data_out[74] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX (.S(la_wb_switch), .A1(wbs_dat_i[21]), .A0(la_data_in[75]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX (.S(wb_la_switch), .A1(wbs_dat_i[20]), .A0(la_data_in[75]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73]));
|
||||
assign la_data_out[75] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX (.S(la_wb_switch), .A1(wbs_dat_i[22]), .A0(la_data_in[76]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX (.S(wb_la_switch), .A1(wbs_dat_i[21]), .A0(la_data_in[76]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72]));
|
||||
assign la_data_out[76] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX (.S(la_wb_switch), .A1(wbs_dat_i[23]), .A0(la_data_in[77]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX (.S(wb_la_switch), .A1(wbs_dat_i[22]), .A0(la_data_in[77]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71]));
|
||||
assign la_data_out[77] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX (.S(la_wb_switch), .A1(wbs_dat_i[24]), .A0(la_data_in[78]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX (.S(wb_la_switch), .A1(wbs_dat_i[23]), .A0(la_data_in[78]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70]));
|
||||
assign la_data_out[78] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX (.S(la_wb_switch), .A1(wbs_dat_i[25]), .A0(la_data_in[79]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX (.S(wb_la_switch), .A1(wbs_dat_i[24]), .A0(la_data_in[79]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69]));
|
||||
assign la_data_out[79] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX (.S(la_wb_switch), .A1(wbs_dat_i[26]), .A0(la_data_in[80]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX (.S(wb_la_switch), .A1(wbs_dat_i[25]), .A0(la_data_in[80]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68]));
|
||||
assign la_data_out[80] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX (.S(la_wb_switch), .A1(wbs_dat_i[27]), .A0(la_data_in[81]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX (.S(wb_la_switch), .A1(wbs_dat_i[26]), .A0(la_data_in[81]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67]));
|
||||
assign la_data_out[81] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX (.S(la_wb_switch), .A1(wbs_dat_i[28]), .A0(la_data_in[82]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX (.S(wb_la_switch), .A1(wbs_dat_i[27]), .A0(la_data_in[82]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66]));
|
||||
assign la_data_out[82] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX (.S(la_wb_switch), .A1(wbs_dat_i[29]), .A0(la_data_in[83]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX (.S(wb_la_switch), .A1(wbs_dat_i[28]), .A0(la_data_in[83]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65]));
|
||||
assign la_data_out[83] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX (.S(la_wb_switch), .A1(wbs_dat_i[30]), .A0(la_data_in[84]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX (.S(wb_la_switch), .A1(wbs_dat_i[29]), .A0(la_data_in[84]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64]));
|
||||
assign la_data_out[84] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX (.S(la_wb_switch), .A1(wbs_dat_i[31]), .A0(la_data_in[85]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX (.S(wb_la_switch), .A1(wbs_dat_i[30]), .A0(la_data_in[85]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63]));
|
||||
assign la_data_out[85] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] = la_data_in[86];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_62_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62]), .Z(wbs_dat_o[0]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_62_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62]), .Z(la_data_out[86]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX (.S(wb_la_switch), .A1(wbs_dat_i[31]), .A0(la_data_in[86]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62]));
|
||||
assign la_data_out[86] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[87];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(wbs_dat_o[1]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(la_data_out[87]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(wbs_dat_o[0]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(la_data_out[87]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[88];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(wbs_dat_o[2]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(la_data_out[88]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(wbs_dat_o[1]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(la_data_out[88]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[89];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(wbs_dat_o[3]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(la_data_out[89]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(wbs_dat_o[2]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(la_data_out[89]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[90];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(wbs_dat_o[4]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(la_data_out[90]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(wbs_dat_o[3]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(la_data_out[90]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[91];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(wbs_dat_o[5]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(la_data_out[91]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(wbs_dat_o[4]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(la_data_out[91]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[92];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(wbs_dat_o[6]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(la_data_out[92]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(wbs_dat_o[5]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(la_data_out[92]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[93];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(wbs_dat_o[7]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(la_data_out[93]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(wbs_dat_o[6]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(la_data_out[93]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[94];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(wbs_dat_o[8]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(la_data_out[94]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(wbs_dat_o[7]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(la_data_out[94]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[95];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(wbs_dat_o[9]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(la_data_out[95]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(wbs_dat_o[8]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(la_data_out[95]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[96];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(wbs_dat_o[10]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(la_data_out[96]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(wbs_dat_o[9]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(la_data_out[96]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[97];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(wbs_dat_o[11]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(la_data_out[97]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(wbs_dat_o[10]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(la_data_out[97]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[98];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(wbs_dat_o[12]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(la_data_out[98]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(wbs_dat_o[11]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(la_data_out[98]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[99];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(wbs_dat_o[13]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(la_data_out[99]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(wbs_dat_o[12]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(la_data_out[99]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[100];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(wbs_dat_o[14]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(la_data_out[100]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(wbs_dat_o[13]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(la_data_out[100]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[101];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(wbs_dat_o[15]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(la_data_out[101]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(wbs_dat_o[14]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(la_data_out[101]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[102];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(wbs_dat_o[16]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(la_data_out[102]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(wbs_dat_o[15]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(la_data_out[102]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[103];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(wbs_dat_o[17]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(la_data_out[103]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(wbs_dat_o[16]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(la_data_out[103]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[104];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(wbs_dat_o[18]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(la_data_out[104]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(wbs_dat_o[17]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(la_data_out[104]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[105];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(wbs_dat_o[19]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(la_data_out[105]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(wbs_dat_o[18]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(la_data_out[105]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[106];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(wbs_dat_o[20]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(la_data_out[106]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(wbs_dat_o[19]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(la_data_out[106]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[107];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(wbs_dat_o[21]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(la_data_out[107]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(wbs_dat_o[20]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(la_data_out[107]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[108];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(wbs_dat_o[22]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(la_data_out[108]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(wbs_dat_o[21]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(la_data_out[108]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[109];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(wbs_dat_o[23]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(la_data_out[109]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(wbs_dat_o[22]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(la_data_out[109]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[110];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(wbs_dat_o[24]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(la_data_out[110]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(wbs_dat_o[23]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(la_data_out[110]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[111];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(wbs_dat_o[25]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(la_data_out[111]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(wbs_dat_o[24]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(la_data_out[111]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[112];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(wbs_dat_o[26]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(la_data_out[112]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(wbs_dat_o[25]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(la_data_out[112]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[113];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(wbs_dat_o[27]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(la_data_out[113]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(wbs_dat_o[26]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(la_data_out[113]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[114];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(wbs_dat_o[28]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(la_data_out[114]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(wbs_dat_o[27]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(la_data_out[114]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[115];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(wbs_dat_o[29]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(la_data_out[115]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(wbs_dat_o[28]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(la_data_out[115]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[116];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(wbs_dat_o[30]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(la_data_out[116]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(wbs_dat_o[29]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(la_data_out[116]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[117];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB (.TE_B(la_wb_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(wbs_dat_o[31]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA (.TE_B(la_wb_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(la_data_out[117]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(wbs_dat_o[30]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(la_data_out[117]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[118];
|
||||
assign la_data_out[118] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(wbs_dat_o[31]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(la_data_out[118]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[119];
|
||||
assign la_data_out[119] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[120];
|
||||
|
|
@ -383,7 +383,7 @@ module fpga_top (
|
|||
assign io_oeb[37] = 1'b1;
|
||||
|
||||
// FPGA clock port can be driven by either wishbone clock or an GPIO
|
||||
sky130_fd_sc_hd__mux2_1 FPGA_CLK_MUX (.S(la_wb_switch), .A1(wb_clk_i), .A0(io_in[36]), .X(clk));
|
||||
assign clk = io_in[36];
|
||||
assign io_out[36] = 1'b0;
|
||||
assign io_oeb[36] = 1'b1;
|
||||
|
||||
|
|
|
|||
|
|
@ -120,7 +120,7 @@ module fpga_top (
|
|||
assign io_oeb[37] = 1'b1;
|
||||
|
||||
// FPGA clock port can be driven by either wishbone clock or an GPIO
|
||||
sky130_fd_sc_hd__mux2_1 FPGA_CLK_MUX (.S(la_wb_switch), .A1(wb_clk_i), .A0(io_in[36]), .X(clk));
|
||||
assign clk = io_in[36];
|
||||
assign io_out[36] = 1'b0;
|
||||
assign io_oeb[36] = 1'b1;
|
||||
|
||||
|
|
|
|||
|
|
@ -35,7 +35,8 @@ args = parser.parse_args()
|
|||
# The list start from left-side of the wrapper to the right side
|
||||
# Target FPGA gpio start from 135, 134 ...
|
||||
#####################################################################
|
||||
wishbone_pins = ['wb_rst_i', 'wbs_ack_o', 'wbs_cyc_i',
|
||||
wishbone_pins = ['wb_clk_i', 'wb_rst_i',
|
||||
'wbs_ack_o', 'wbs_cyc_i',
|
||||
'wbs_stb_i', 'wbs_we_i']
|
||||
|
||||
wishbone_pins.extend([f"wbs_sel_i[{i}]" for i in range(4)])
|
||||
|
|
@ -79,8 +80,8 @@ for ipin in range(0, num_gpio_pins):
|
|||
# - the Wishbone input
|
||||
# or
|
||||
# - the logic analyzer input
|
||||
# through a multiplexer controlled by the signal 'la_wb_switch
|
||||
curr_line = " " + "sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_" + str(135 - ipin) + "_MUX (.S(la_wb_switch), .A1(" + str(
|
||||
# through a multiplexer controlled by the signal 'wb_la_switch
|
||||
curr_line = " " + "sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_" + str(135 - ipin) + "_MUX (.S(wb_la_switch), .A1(" + str(
|
||||
wishbone_pins[ipin]) + "), .A0(" + str(logic_analyzer_pins[ipin][0]) + "), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[" + str(135 - ipin) + "]));"
|
||||
netlist_lines.append(curr_line + "\n")
|
||||
##############################################################
|
||||
|
|
@ -99,18 +100,18 @@ for ipin in range(0, num_gpio_pins):
|
|||
netlist_lines.append(curr_line + "\n")
|
||||
##############################################################
|
||||
# SOC OUTPUT will drive the Wishbone output through a tri-state buffer
|
||||
# As the buffer is enabled by logic '0', we use the inverted 'la_wb_switch'
|
||||
# As the buffer is enabled by logic '0', we use the inverted 'wb_la_switch'
|
||||
curr_line = " " + "sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_" + str(135 - ipin) + "_DEMUX_WB (" + \
|
||||
".TE_B(la_wb_switch_b), " + \
|
||||
".TE_B(wb_la_switch_b), " + \
|
||||
".A(" + "gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[" + str(135 - ipin) + "]), " + \
|
||||
".Z(" + str(wishbone_pins[ipin]) + ")" + \
|
||||
");"
|
||||
netlist_lines.append(curr_line + "\n")
|
||||
##############################################################
|
||||
# SOC OUTPUT will also drive the Logic Analyzer output through a tri-state buffer
|
||||
# As the buffer is enabled by logic '0', we use the 'la_wb_switch'
|
||||
# As the buffer is enabled by logic '0', we use the 'wb_la_switch'
|
||||
curr_line = " " + "sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_" + str(135 - ipin) + "_DEMUX_LA (" + \
|
||||
".TE_B(la_wb_switch), " + \
|
||||
".TE_B(wb_la_switch), " + \
|
||||
".A(" + "gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[" + str(135 - ipin) + "]), " + \
|
||||
".Z(" + str(logic_analyzer_pins[ipin][1]) + ")" + \
|
||||
");"
|
||||
|
|
|
|||
Loading…
Reference in New Issue