diff --git a/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml index 82c1658..fc8e81d 100644 --- a/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml +++ b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml @@ -22,5 +22,5 @@ LUT3_DELAY: 2.31e-9 LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9 LUT4_DELAY: 2.6e-9 LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9 -REGIN_TO_FF0_DELAY: 1.12e-9 +REGIN_TO_FF0_DELAY: 0.58e-9 FF0_TO_FF1_DELAY: 0.56e-9 diff --git a/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch_timing.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch_timing.svg new file mode 100644 index 0000000..78d1013 --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch_timing.svg @@ -0,0 +1,328 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.4\n2021-04-02 20:32:49 +0000 + + frac_lut4_timing_points + + 图层 1 + + + + + + + + + + + + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + + + + + FF + [0] + + + + + + + + + + + + + + + + + + + + + + + out[0] + + + + + + + + + M + U + X + + + + + + + + + + + + + + + FF + [1] + + + + + + + + + + + + + + + + + + + + + + + out[1] + + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + scin + + + + + + + + + + + scout + + + + + + + + + + + + + + + + + + + + regin + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + + + regout + + + + + CLK + + + + + + + + + + + + + + + + + + + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + + + + A + + + + + diff --git a/DOC/source/datasheet/sofa_hd/figures/sofa_hd_routing_arch.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_routing_arch.svg new file mode 100644 index 0000000..c8464f2 --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_routing_arch.svg @@ -0,0 +1,365 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.4\n2021-04-03 00:25:42 +0000 + + Canvas 1 + + Layer 1 + + + + + + + + + + + Input Pin + + + + + Output Pin + + + + + + + + + + + + + SB MUX + + + + + CB MUX + + + + + Track + + + + + + + + + + CLB + [2][1] + + + + + + + + + + + + + + + + + + + + + + + + + CLB + [1][1] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CLB + [3][1] + + + + + + + + + + + + + + + + + + + + + CLB + [4][1] + + + + + + + + + + + + + + + + + + CLB + [5][1] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + L4 Wire + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + L2 Wire + + + + + L1 Wire + + + + + A + + + + + B + + + + + + + + + C + + + + + D + + + + + E + + + + + diff --git a/DOC/source/datasheet/sofa_hd/index.rst b/DOC/source/datasheet/sofa_hd/index.rst index 8bff100..3b82f44 100644 --- a/DOC/source/datasheet/sofa_hd/index.rst +++ b/DOC/source/datasheet/sofa_hd/index.rst @@ -14,3 +14,5 @@ SOFA HD sofa_hd_clb_arch sofa_hd_circuit_design + + sofa_hd_timing diff --git a/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst b/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst index 5f503c9..26340a9 100644 --- a/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst +++ b/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst @@ -59,6 +59,50 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra | | | cells. | +------+----------+----------------------------------------------+ +.. _sofa_hd_fpga_arch_routing_arch: + +Routing Architecture +^^^^^^^^^^^^^^^^^^^^ + +The routing architecture is based on uni-directional routing tracks, which are interconnected by routing multiplexers. +:numref:`fig_sofa_hd_routing_arch` illustrates the detailed organization of the routing architecture. + +.. _fig_sofa_hd_routing_arch: + +.. figure:: ./figures/sofa_hd_routing_arch.svg + :width: 80% + :alt: Detailed routing architecture + + Detailed routing architecture + +The routing architecture consists the following type of routing tracks: + +- Length-1 wires (``L1 wires``), which hop over 1 logic block (including I/O block) +- Length-2 wires (``L2 wires``), which hop over 2 logic block (including I/O block) +- Length-4 wires (``L4 wires``), which hop over 4 logic block (including I/O block) + +Each tile includes two routing channels, i.e., the X-direction routing channel and the Y-direction routing channel, providing horizental and vertical connections to adjacent tiles. +Each routing channel consists of 40 routing tracks. See details in :numref:`table_sofa_hd_fpga_arch_routing_track_distribution`. + +.. _table_sofa_hd_fpga_arch_routing_track_distribution: + +.. table:: Routing track distribution of SOFA HD FPGA + + +------------+------------------------------+ + | Track type | Number of tracks per channel | + +============+==============================+ + | Length-1 | 6 (10%) | + +------------+------------------------------+ + | Length-2 | 6 (10%) | + +------------+------------------------------+ + | Length-4 | 28 (80%) | + +------------+------------------------------+ + | Total | 40 | + +------------+------------------------------+ + + + + .. _sofa_hd_fpga_arch_scan_chain: Scan-chain diff --git a/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst b/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst new file mode 100644 index 0000000..12b2ea0 --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst @@ -0,0 +1,108 @@ +.. _sofa_hd_timing: + +Timing Annotation +----------------- + +.. _sofa_hd_timing_clb: + +Configurable Logic Block +^^^^^^^^^^^^^^^^^^^^^^^^ + +The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`. + +.. _fig_sofa_hd_fle_arch_timing: + +.. figure:: ./figures/sofa_hd_fle_arch_timing.svg + :scale: 30% + :alt: Schematic of a logic element used in SOFA HD FPGA + + Schematic of a logic element used in SOFA HD FPGA + +.. _table_sofa_hd_fle_arch_timing: + +.. table:: Path delays of logic element in the SOFA HD FPGA + + +-------------------------+------------------------------+ + | Path / Delay | TT (unit: ns) | + +=========================+==============================+ + | in0 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in1 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in2 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in0 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in1 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in2 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in0 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in1 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in2 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in3 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | LUT3_out[0] -> A | 0.56 | + +-------------------------+------------------------------+ + | LUT4_out[0] -> A | 0.58 | + +-------------------------+------------------------------+ + | A -> out[0] | 0.88 | + +-------------------------+------------------------------+ + | A -> FF[0] | 0.56 | + +-------------------------+------------------------------+ + | FF[0] -> out[0] | 0.88 | + +-------------------------+------------------------------+ + | LUT3_out[1] -> out[1] | 0.89 | + +-------------------------+------------------------------+ + | LUT3_out[1] -> FF[1] | 0.56 | + +-------------------------+------------------------------+ + | FF[1] -> out[1] | 0.89 | + +-------------------------+------------------------------+ + | regin -> FF[0] | 0.58 | + +-------------------------+------------------------------+ + | FF[0] -> FF[1] | 0.56 | + +-------------------------+------------------------------+ + +.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques. + +I/O Block +^^^^^^^^^ + +The path delays in :numref:`fig_sofa_hd_embedded_io_schematic` are listed in :numref:`table_sofa_hd_io_timing`. + +.. _table_sofa_hd_io_timing: + +.. table:: Path delays of I/O circuit in the SOFA HD FPGA + + +-------------------------+------------------------------+ + | Path / Delay | TT (unit: ns) | + +=========================+==============================+ + | SOC_IN -> FPGA_IN | 0.11 | + +-------------------------+------------------------------+ + | FPGA_OUT -> SOC_OUT | 0.11 | + +-------------------------+------------------------------+ + +Routing Architecture +^^^^^^^^^^^^^^^^^^^^ + +The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`table_sofa_hd_routing_arch_timing`. + +.. _table_sofa_hd_routing_arch_timing: + +.. table:: Path delays of routing blocks in the SOFA HD FPGA + + +---------------------------+------------------------------+ + | Path / Delay | TT (unit: ns) | + +===========================+==============================+ + | A -> B | 1.61 | + +---------------------------+------------------------------+ + | A -> C | 1.61 | + +---------------------------+------------------------------+ + | A -> D | 1.61 | + +---------------------------+------------------------------+ + | B -> E | 1.38 | + +---------------------------+------------------------------+ +