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[Architecture] Create template architecture for openfpga

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tangxifan 2020-10-09 17:28:14 -06:00
parent a2b42c2e5f
commit 069c36cbfc
1 changed files with 9 additions and 9 deletions
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18
ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml → ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml
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@ -28,7 +28,7 @@
</variation_library> </variation_library>
</technology_library> </technology_library>
<circuit_library> <circuit_library>
<circuit_model type="inv_buf" name="scs8ms_inv_1" prefix="scs8ms_inv_1" is_default="true" verilog_netlist="/research/ece/lnis/CAD_TOOLS/DKITS/skywater/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_inv_1.v"> <circuit_model type="inv_buf" name="scs8ms_inv_1" prefix="scs8ms_inv_1" is_default="true" verilog_netlist="${SKYWATER_PDK_HOME}/scs8ms/V0.0.1/verilog/scs8ms_inv_1.v">
<design_technology type="cmos" topology="inverter" size="1"/> <design_technology type="cmos" topology="inverter" size="1"/>
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/> <port type="input" prefix="in" lib_name="A" size="1"/>
@ -40,7 +40,7 @@
10e-12 10e-12
</delay_matrix> </delay_matrix>
</circuit_model> </circuit_model>
<circuit_model type="inv_buf" name="scs8ms_buf_2" prefix="scs8ms_buf_2" is_default="false" verilog_netlist="/research/ece/lnis/CAD_TOOLS/DKITS/skywater/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_buf_2.v"> <circuit_model type="inv_buf" name="scs8ms_buf_2" prefix="scs8ms_buf_2" is_default="false" verilog_netlist="${SKYWATER_PDK_HOME}/scs8ms/V0.0.1/verilog/scs8ms_buf_2.v">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/> <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/> <port type="input" prefix="in" lib_name="A" size="1"/>
@ -52,7 +52,7 @@
10e-12 10e-12
</delay_matrix> </delay_matrix>
</circuit_model> </circuit_model>
<circuit_model type="inv_buf" name="scs8ms_buf_4" prefix="scs8ms_buf_4" is_default="false" verilog_netlist="/research/ece/lnis/CAD_TOOLS/DKITS/skywater/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_buf_4.v"> <circuit_model type="inv_buf" name="scs8ms_buf_4" prefix="scs8ms_buf_4" is_default="false" verilog_netlist="${SKYWATER_PDK_HOME}/scs8ms/V0.0.1/verilog/scs8ms_buf_4.v">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/> <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/> <port type="input" prefix="in" lib_name="A" size="1"/>
@ -64,7 +64,7 @@
10e-12 10e-12
</delay_matrix> </delay_matrix>
</circuit_model> </circuit_model>
<circuit_model type="inv_buf" name="scs8ms_inv_2" prefix="scs8ms_inv_2" is_default="false" verilog_netlist="/research/ece/lnis/CAD_TOOLS/DKITS/skywater/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_inv_2.v"> <circuit_model type="inv_buf" name="scs8ms_inv_2" prefix="scs8ms_inv_2" is_default="false" verilog_netlist="${SKYWATER_PDK_HOME}/scs8ms/V0.0.1/verilog/scs8ms_inv_2.v">
<design_technology type="cmos" topology="buffer" size="1"/> <design_technology type="cmos" topology="buffer" size="1"/>
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/> <port type="input" prefix="in" lib_name="A" size="1"/>
@ -76,7 +76,7 @@
10e-12 10e-12
</delay_matrix> </delay_matrix>
</circuit_model> </circuit_model>
<circuit_model type="gate" name="scs8ms_or2_1" prefix="scs8ms_or2_1" is_default="true" verilog_netlist="/research/ece/lnis/CAD_TOOLS/DKITS/skywater/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_or2_1.v"> <circuit_model type="gate" name="scs8ms_or2_1" prefix="scs8ms_or2_1" is_default="true" verilog_netlist="${SKYWATER_PDK_HOME}/scs8ms/V0.0.1/verilog/scs8ms_or2_1.v">
<design_technology type="cmos" topology="OR"/> <design_technology type="cmos" topology="OR"/>
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
@ -98,7 +98,7 @@
If your standard cell provider does not offer the exact truth table, If your standard cell provider does not offer the exact truth table,
you can simply swap the inputs as shown in the example below you can simply swap the inputs as shown in the example below
--> -->
<circuit_model type="gate" name="scs8ms_mux2_1" prefix="scs8ms_mux2_1" verilog_netlist="/research/ece/lnis/CAD_TOOLS/DKITS/skywater/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_mux2_1.v"> <circuit_model type="gate" name="scs8ms_mux2_1" prefix="scs8ms_mux2_1" verilog_netlist="${SKYWATER_PDK_HOME}/scs8ms/V0.0.1/verilog/scs8ms_mux2_1.v">
<design_technology type="cmos" topology="MUX2"/> <design_technology type="cmos" topology="MUX2"/>
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
@ -143,7 +143,7 @@
<port type="sram" prefix="sram" size="1"/> <port type="sram" prefix="sram" size="1"/>
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="scs8ms_sdfrtp_1" prefix="scs8ms_sdfrtp_1" verilog_netlist="/research/ece/lnis/CAD_TOOLS/DKITS/skywater/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_sdfrtp_1.v"> <circuit_model type="ff" name="scs8ms_sdfrtp_1" prefix="scs8ms_sdfrtp_1" verilog_netlist="${SKYWATER_PDK_HOME}/scs8ms/V0.0.1/verilog/scs8ms_sdfrtp_1.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="scs8ms_inv_1"/> <input_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>
<output_buffer exist="true" circuit_model_name="scs8ms_inv_1"/> <output_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>
@ -169,7 +169,7 @@
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="scs8ms_dfrbp_1" default_val="1"/> <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="scs8ms_dfrbp_1" default_val="1"/>
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="scs8ms_dfrbp_1" prefix="scs8ms_dfrbp_1" verilog_netlist="/research/ece/lnis/CAD_TOOLS/DKITS/skywater/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_dfrbp_1.v"> <circuit_model type="ccff" name="scs8ms_dfrbp_1" prefix="scs8ms_dfrbp_1" verilog_netlist="${SKYWATER_PDK_HOME}/scs8ms/V0.0.1/verilog/scs8ms_dfrbp_1.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="scs8ms_inv_1"/> <input_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>
<output_buffer exist="true" circuit_model_name="scs8ms_inv_1"/> <output_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>
@ -188,7 +188,7 @@
<port type="input" prefix="outpad" lib_name="A" size="1"/> <port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/> <port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="scs8ms_fah_1" prefix="scs8ms_fah_1" is_default="true" verilog_netlist="/research/ece/lnis/CAD_TOOLS/DKITS/skywater/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_fah_1.v"> <circuit_model type="hard_logic" name="scs8ms_fah_1" prefix="scs8ms_fah_1" is_default="true" verilog_netlist="${SKYWATER_PDK_HOME}/scs8ms/V0.0.1/verilog/scs8ms_fah_1.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="scs8ms_inv_1"/> <input_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>
<output_buffer exist="true" circuit_model_name="scs8ms_inv_1"/> <output_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>