From 06731e092e82e1bae3693fcf230b63610110a506 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 2 Dec 2020 13:46:40 -0700
Subject: [PATCH] [Arch] Patch reset port name to be consistent with post-PnR
 netlist

---
 ...ter_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
index 97989e2..06558f6 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -230,7 +230,7 @@
   </direct_connection>
   <tile_annotations>
     <global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
-    <global_port name="reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
+    <global_port name="Reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
   </tile_annotations>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->