From 062120ffd9c9e6e301a20425c90a8ddd06232055 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 1 Apr 2021 16:39:19 -0600
Subject: [PATCH] [Arch] Update timing for SOFA architecture

---
 ...n_chain_nonLR_caravel_io_skywater130nm.xml | 189 +++++++-----------
 1 file changed, 75 insertions(+), 114 deletions(-)

diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index 21f4189..622dd8b 100644
--- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -11,6 +11,9 @@
       - 80% L = 4, fc_in = 0.15, Fc_out = 0.10
       - 100 routing tracks per channel
 
+  - The timing is extracted from a TT corner (1.8V, 25C)
+  - TODO: Add multi-corners, in particular, SS corner
+
   Authors: Xifan Tang
 -->
 <architecture>
@@ -186,21 +189,6 @@
     </fixed_layout>
   </layout>
   <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
     <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
     <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
      	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
@@ -214,41 +202,32 @@
     <connection_block input_switch_name="ipin_cblock"/>
   </device>
   <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-	       book area formula. This means the mux transistors are about 5x minimum drive strength.
-	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-	       2.5x when looking up in Jeff's tables.
-	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!-- Give uniform delays for all the MUXes driving different length of wires
+         TODO: Can be more accurate once the report timing strategies are elaborated
+       -->
+    <switch type="mux" name="L1_mux" R="0" Cin="0" Cout="0" Tdel="1.61e-9" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <switch type="mux" name="L2_mux" R="0" Cin="0" Cout="0" Tdel="1.61e-9" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <switch type="mux" name="L4_mux" R="0" Cin="0" Cout="0" Tdel="1.61e-9" mux_trans_size="2.630740" buf_size="27.645901"/>
     <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+    <switch type="mux" name="ipin_cblock" R="0" Cout="0." Cin="0" Tdel="1.38e-9" mux_trans_size="1.222260" buf_size="auto"/>
   </switchlist>
   <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!--- The wire delay is around 0.1ns in post PnR netlist.
+          Create a pair of RC value so that R * C = 0.1ns
+          This is o.k. because other RC values are all zero
+      -->
     <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
-    <segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+    <segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="100" Cmetal="1e-12">
       <mux name="L1_mux"/>
       <sb type="pattern">1 1</sb>
       <cb type="pattern">1</cb>
     </segment>
-    <segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+    <segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="100" Cmetal="1e-12">
       <mux name="L2_mux"/>
       <sb type="pattern">1 1 1</sb>
       <cb type="pattern">1 1</cb>
     </segment>
-    <segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+    <segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="100" Cmetal="1e-12">
       <mux name="L4_mux"/>
       <sb type="pattern">1 1 1 1 1</sb>
       <cb type="pattern">1 1 1 1</cb>
@@ -277,18 +256,17 @@
         </pb_type>
         <interconnect>
           <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+            <delay_constant max="0.11e-9" in_port="io.outpad" out_port="iopad.outpad"/>
           </direct>
           <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+            <delay_constant max="0.11e-9" in_port="iopad.inpad" out_port="io.inpad"/>
           </direct>
         </interconnect>
       </mode>
 
       <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
+	       The Embedded I/O timing is 0.11ns
+           FIXME: the timing may include the GPIO timing!!!
 	     -->
       <mode name="inpad">
         <pb_type name="inpad" blif_model=".input" num_pb="1">
@@ -296,7 +274,7 @@
         </pb_type>
         <interconnect>
           <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+            <delay_constant max="0.11e-9" in_port="inpad.inpad" out_port="io.inpad"/>
           </direct>
         </interconnect>
       </mode>
@@ -306,7 +284,7 @@
         </pb_type>
         <interconnect>
           <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+            <delay_constant max="0.11e-9" in_port="io.outpad" out_port="outpad.outpad"/>
           </direct>
         </interconnect>
       </mode>
@@ -386,9 +364,9 @@
               <input name="DI" num_pins="1"/>
               <output name="Q" num_pins="1"/>
               <clock name="clk" num_pins="1"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_setup value="66e-12" port="ff.DI" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              <T_setup value="0.39e-9" port="ff.D" clock="clk"/>
+              <T_setup value="0.39e-9" port="ff.DI" clock="clk"/>
+              <T_clock_to_Q max="0.43e-9" port="ff.Q" clock="clk"/>
             </pb_type>         
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
@@ -398,22 +376,22 @@
               <direct name="direct5" input="ff[1].Q" output="fabric.reg_out"/>
               <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
               <mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
-                <delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
-                <delay_constant max="45e-12" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
+                <delay_constant max="1.14e-9" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
+                <delay_constant max="1.14e-9" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
               </mux>
               <mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D">
-                <delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
-                <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
+                <delay_constant max="0.56e-9" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
+                <delay_constant max="0.56e-9" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
               </mux>
               <mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
-                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+                <delay_constant max="0.89e-9" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="0.88e-9" in_port="ff[0].Q" out_port="fabric.out[0]"/>
               </mux>
               <mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
-                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+                <delay_constant max="0.78e-9" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="0.89e-9" in_port="ff[1].Q" out_port="fabric.out[1]"/>
               </mux>
             </interconnect>
           </pb_type>
@@ -443,18 +421,10 @@
                 <input name="in" num_pins="3" port_class="lut_in"/>
                 <output name="out" num_pins="1" port_class="lut_out"/>
                 <!-- LUT timing using delay matrix -->
-                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                           we instead take the average of these numbers to get more stable results
-                      82e-12
-                      173e-12
-                      261e-12
-                      263e-12
-                      398e-12
-                      -->
                 <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
-                  235e-12
-                  235e-12
-                  235e-12
+                  2.31e-9
+                  2.31e-9
+                  2.31e-9
                 </delay_matrix>
               </pb_type>
               <!-- Define the flip-flop -->
@@ -462,20 +432,22 @@
                 <input name="D" num_pins="1" port_class="D"/>
                 <output name="Q" num_pins="1" port_class="Q"/>
                 <clock name="clk" num_pins="1" port_class="clock"/>
-                <T_setup value="66e-12" port="ff.D" clock="clk"/>
-                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                <T_setup value="0.39e-9" port="ff.D" clock="clk"/>
+                <T_clock_to_Q max="0.43e-9" port="ff.Q" clock="clk"/>
               </pb_type>
               <interconnect>
                 <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
                 <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
                   <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
                   <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
+                  <!-- Consider the delay of the MUX between LUT3 and FF -->
+                  <delay_constant max="1.14e-9" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
                 </direct>
                 <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
                 <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
-                  <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                  <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
-                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
+                  <!-- Combine the delay of LUT4/LUT3 output MUX and fabric output mux -->
+                  <delay_constant max="2.03e-9" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
+                  <delay_constant max="0.89e-9" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
                 </mux>
               </interconnect>
             </pb_type>
@@ -505,20 +477,11 @@
               <input name="in" num_pins="4" port_class="lut_in"/>
               <output name="out" num_pins="1" port_class="lut_out"/>
               <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
               <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                261e-12
-                261e-12
-                261e-12
-                261e-12
+                2.6e-9
+                2.6e-9
+                2.6e-9
+                2.6e-9
               </delay_matrix>
             </pb_type>
             <!-- Define flip-flop -->
@@ -526,20 +489,22 @@
               <input name="D" num_pins="1" port_class="D"/>
               <output name="Q" num_pins="1" port_class="Q"/>
               <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              <T_setup value="0.39e-9" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="0.43e-9" port="ff.Q" clock="clk"/>
             </pb_type>
             <interconnect>
               <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
               <direct name="direct2" input="lut4.out" output="ff.D">
                 <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
                 <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
+                  <!-- Consider the delay of the MUX between LUT4 and FF -->
+                <delay_constant max="1.14e-9" in_port="lut4.out" out_port="ff.D"/>
               </direct>
               <direct name="direct3" input="ble4.clk" output="ff.clk"/>
               <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
+                <!-- Combine the delay of LUT4/LUT3 output MUX and fabric output mux -->
+                <delay_constant max="2.03e-9" in_port="lut4.out" out_port="ble4.out"/>
+                <delay_constant max="0.89e-9" in_port="ff.Q" out_port="ble4.out"/>
               </mux>
             </interconnect>
           </pb_type>
@@ -561,15 +526,27 @@
               <input name="D" num_pins="1" port_class="D"/>
               <output name="Q" num_pins="1" port_class="Q"/>
               <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              <T_setup value="0.39e-9" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="0.43e-9" port="ff.Q" clock="clk"/>
             </pb_type>
             <interconnect>
-              <direct name="direct1" input="shift_reg.reg_in" output="ff[0].D"/>
-              <direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
+              <direct name="direct1" input="shift_reg.reg_in" output="ff[0].D">
+                <!-- Consider the delay of the MUX between LUT4 and FF -->
+                <delay_constant max="1.12e-9" in_port="shift_reg.reg_in" out_port="ff[0].D"/>
+              </direct>
+              <direct name="direct2" input="ff[0].Q" output="ff[1].D">
+                <!-- Consider the delay of the MUX between LUT4 and FF -->
+                <delay_constant max="0.56e-9" in_port="ff[0].Q" out_port="ff[1].D"/>
+              </direct>
               <direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/>
-              <direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]"/>
-              <direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]"/>
+              <direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]">
+                <!-- Consider the delay of the MUX between LUT4 and FF -->
+                <delay_constant max="0.88e-9" in_port="ff[0].Q" out_port="shift_reg.ff_out[0:0]"/>
+              </direct>
+              <direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]">
+                <!-- Consider the delay of the MUX between LUT4 and FF -->
+                <delay_constant max="0.89e-9" in_port="ff[1].Q" out_port="shift_reg.ff_out[1:1]"/>
+              </direct>
               <complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
             </interconnect>
           </pb_type>
@@ -591,52 +568,36 @@
                     I[0] should be connected to in[0]
           -->
         <direct name="direct_fle0" input="clb.I0[0:2]" output="fle[0:0].in[0:2]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle0i" input="clb.I0i" output="fle[0:0].in[3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle1" input="clb.I1[0:2]" output="fle[1:1].in[0:2]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle1i" input="clb.I1i" output="fle[1:1].in[3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle2" input="clb.I2[0:2]" output="fle[2:2].in[0:2]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle2i" input="clb.I2i" output="fle[2:2].in[3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle3" input="clb.I3[0:2]" output="fle[3:3].in[0:2]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle3i" input="clb.I3i" output="fle[3:3].in[3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle4" input="clb.I4[0:2]" output="fle[4:4].in[0:2]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle4i" input="clb.I4i" output="fle[4:4].in[3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle5" input="clb.I5[0:2]" output="fle[5:5].in[0:2]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle5i" input="clb.I5i" output="fle[5:5].in[3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle6" input="clb.I6[0:2]" output="fle[6:6].in[0:2]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle6i" input="clb.I6i" output="fle[6:6].in[3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle7" input="clb.I7[0:2]" output="fle[7:7].in[0:2]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle7i" input="clb.I7i" output="fle[7:7].in[3]">
-          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <complete name="clks" input="clb.clk" output="fle[7:0].clk">
         </complete>
@@ -650,7 +611,7 @@
         <!-- Shift register chain links -->
         <direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
           <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
+          <delay_constant max="0e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
           <!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
         </direct>
         <direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
@@ -662,7 +623,7 @@
         <!-- Scan chain links -->
         <direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
           <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
+          <delay_constant max="0e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
         </direct>
         <direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
         </direct>