Merge pull request #1 from LNIS-Projects/xt_dev

Documentation addition

ARCH/README.md

@@ -0,0 +1,13 @@
+# FPGA architecture description
+This directory contains the FPGA architecture description files for OpenFPGA tool suites.
+All the FPGA architecture description are binded to the opensource skywater 130nm PDK
+
+* Keep this folder clean and organized as follows
+  - **vpr\_arch**: FPGA architecture description for VPR
+  - **openfpga_arch_template**: template FPGA architecture description for OpenFPGA.
+  - **openfpga_arch**: adapted FPGA architecture description for OpenFPGA which are converted from the templates.
+
+* Note: 
+  - Please **ONLY** place folders under this directory
+    README should be the ONLY file under this directory
+  - VPR and OpenFPGA architecture files should be placed in separated directories

ARCH/openfpga_arch/README.md

@@ -0,0 +1,6 @@
+# Adapted OpenFPGA architecture description
+This directory contains the FPGA architecture description files for OpenFPGA tool suites.
+All the FPGA architecture description are binded to the opensource skywater 130nm PDK
+
+* Note: 
+  - Please do **NOT** add any architecture file to this directory. All the architecture files will be automatically generated from the template architecture files by scripts

ARCH/openfpga_arch_template/README.md

@@ -0,0 +1,28 @@
+# Naming convention for OpenFPGA architecture files
+Please reveal the following architecture features in the names to help quickly spot architecture files.
+Note that an OpenFPGA architecture can be applied to multiple VPR architecture files.
+
+- k<lut\_size>: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size.
+- frac: If fracturable LUT is used or not.
+- N<le\_size>: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number.
+- adder\_chain: If hard adder/carry chain is used inside CLBs
+- register\_chain: If shift register chain is used inside CLBs
+- scan\_chain: If scan chain testing infrastructure is used inside CLBs
+- mem<mem\_size>: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword wide is to specify if the BRAM spanns more than 1 column.
+- aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os.
+- <bank\|cc\|frame\|standalone>: specify the type of configuration protocol used in the architecture.
+  - `bank` refers to the memory bank
+  - `cc` refers to the configuration chain
+  - `frame` refers to the frame-based organization
+  - `standalone` referes to the vanilla organization
+- fixed\_sim: fixed clock frequencies in simulation settings. If auto clock frequencies are used, there is no need to appear in the naming
+- intermediate buffer: If intermediate buffers are used in LUT designs.
+- behavioral: If behavioral Verilog modeling is specified
+- local\_encoder: If local encoders are used in routing multiplexer design
+- spyio/spypad: If spy I/Os are used
+- stdcell: If circuit designs are built with standard cells only
+- tree\_mux: If routing multiplexers are built with a tree-like structure
+- <feature_size>: The technology node which the delay numbers are extracted from.
+- powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating.
+
+Other features are used in naming should be listed here.

ARCH/vpr_arch/README.md

@@ -0,0 +1,17 @@
+# Naming convention for VPR architecture files
+Please reveal the following architecture features in the names to help quickly spot architecture files.
+
+- k<lut\_size>\_<frac>: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size. The keyword 'frac' is to specify if fracturable LUT is used or not.
+- N<le\_size>: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number.
+- tileable: If the routing architecture is tileable or not.
+- adder\_chain: If hard adder/carry chain is used inside CLBs
+- register\_chain: If shift register chain is used inside CLBs
+- scan\_chain: If scan chain testing infrastructure is used inside CLBs
+- <wide>\_<frac>\_mem<mem\_size>: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword 'wide' is to specify if the BRAM spans more than 1 column. The keyword 'frac' is to specify if the BRAM is fracturable to operate in different modes.
+- <wide>\_<frac>\_dsp<dsp\_size>: If Digital Signal Processor (DSP) is used or not. If used, the input size should be clarified here. The keyword 'wide' is to specify if the DSP spans more than 1 column. The keyword 'frac' is to specify if the DSP is fracturable to operate in different modes.
+- aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os.
+- multi\_io\_capacity: If I/O capacity is different on each side of FPGAs.
+- reduced\_io: If I/Os only appear a certain or multiple sides of FPGAs 
+- <feature\_size>: The technology node which the delay numbers are extracted from.
+
+Other features are used in naming should be listed here.

README.md

@@ -2,19 +2,19 @@
 FPGA tape-outs using the open-source Skywater 130nm PDK and OpenFPGA
 
 * Keep this folder clean and organized as follows
-  - DOC: documentation of the project
-  - ARCH: Architecture XML and other input files which OpenFPGA requires to generate Verilog netlists
-  - BENCHMARK: Benchmarks to be tested on the FPGA fabric
-  - HDL: Hardware description netlists for the FPGA fabrics
-  - SDC: design constraints
-  - SCRIPT: Scripts to setup, run OpenFPGA etc.
-  - TESTBENCH: Verilog testbenches generated by OpenFPGA 
-  - PDK: Technology files linked from skywater opensource pdk
-  - SNPS\_ICC2: scripts and workspace of Synopsys IC Compiler 2
-                Keep a README inside the folder about the ICC2 version and how-to-use.
-  - MSIM: scripts and workspace of verification using Mentor ModelSim
+  - **DOC**: documentation of the project
+  - **ARCH**: Architecture XML and other input files which OpenFPGA requires to generate Verilog netlists
+  - **BENCHMARK**: Benchmarks to be tested on the FPGA fabric
+  - **HDL**: Hardware description netlists for the FPGA fabrics
+  - **SDC**: design constraints
+  - **SCRIPT**: Scripts to setup, run OpenFPGA etc.
+  - **TESTBENCH**: Verilog testbenches generated by OpenFPGA 
+  - **PDK**: Technology files linked from skywater opensource pdk
+  - **SNPS\_ICC2**: workspace of Synopsys IC Compiler 2
+                    Keep a README inside the folder about the ICC2 version and how-to-use.
+  - **MSIM**: workspace of verification using Mentor ModelSim
 
 * Note: 
-  - Please **ONLY** place folders under this directory
-    README should be the ONLY file under this directory
-  - Each EDA tool should have independent workspace in a separated directory
+  - Please **ONLY** place folders under this directory.
+    README should be the **ONLY** file under this directory
+  - Each EDA tool should have **independent** workspace in separated directories

SCRIPT/repo_setup.py

@@ -29,6 +29,9 @@ print("\nAdapting architecture templates...");
 num_arch_file_processed = 0;
 for root, dirs, files in os.walk(openfpga_arch_template_dirpath):
   for src_file in files:
+    # Only focus on XML file
+    if not src_file.endswith(".xml"):
+      continue;
     # Copy the file
     des_file = openfpga_arch_adapted_dirpath + os.path.basename(src_file); 
     shutil.copy(openfpga_arch_template_dirpath + src_file, des_file);