2021-04-01 16:58:54 -05:00
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#####################################################################
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# A template script to report timing for A CLB from post-PnR results
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# using Synopsys PrimeTime
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#####################################################################
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##################################
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# Ensure a clean start
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remove_design -all
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remove_lib -all
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##################################
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# Define environment variables
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set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
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set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
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set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
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set DEVICE_NAME "SOFA"
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set TIMING_REPORT_HOME "../TIMING_REPORTS/";
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# Enable preprocessing in Verilog parser
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set_app_var svr_enable_vpp true
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# Enable reporting ALL the timing paths even those are NOT constrained
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set_app_var timing_report_unconstrained_paths tr
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set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
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set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
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set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
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##################################
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# Read timing libraries
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read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
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##################################
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# Read post-PnR netlists
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read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
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# Top-level module name
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2021-04-01 16:59:33 -05:00
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# May sweep for all the io modules
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2021-04-01 16:58:54 -05:00
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set DESIGN_NAME "cbx_1__0__logical_tile_io_mode_physical__iopad_0";
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link_design ${DESIGN_NAME}
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#########################################
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# Setup constraints to break combinational loops
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set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q
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#
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##########################################
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## Setup constraints for clocks
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##########################################
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## Setup constraints for paths
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##################################
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# Read post-PnR parasitics
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read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
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##################################
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# Report timing of Connect block
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# Inpad -> FPGA timing
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report_timing -from gfpga_pad_EMBEDDED_IO_HD_SOC_IN -to iopad_inpad > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
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report_timing -from iopad_outpad -to gfpga_pad_EMBEDDED_IO_HD_SOC_OUT >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
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##################################
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# Finish and quit
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# Comment it out if you want to debug
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exit
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