mirror of https://github.com/lnis-uofu/SOFA.git
256 lines
12 KiB
Coq
256 lines
12 KiB
Coq
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//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Verilog modules for physical tile: clb]
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// Author: Xifan TANG
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// Organization: University of Utah
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// Date: Sun Feb 19 10:53:27 2023
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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// ----- BEGIN Grid Verilog module: grid_clb -----
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//----- Default net type -----
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`default_nettype none
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// ----- Verilog module for grid_clb -----
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module grid_clb(pReset,
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prog_clk,
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Test_en,
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top_width_0_height_0_subtile_0__pin_I0_0_,
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top_width_0_height_0_subtile_0__pin_I0_1_,
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top_width_0_height_0_subtile_0__pin_I0i_0_,
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top_width_0_height_0_subtile_0__pin_I0i_1_,
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top_width_0_height_0_subtile_0__pin_I1_0_,
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top_width_0_height_0_subtile_0__pin_I1_1_,
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top_width_0_height_0_subtile_0__pin_I1i_0_,
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top_width_0_height_0_subtile_0__pin_I1i_1_,
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top_width_0_height_0_subtile_0__pin_I2_0_,
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top_width_0_height_0_subtile_0__pin_I2_1_,
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top_width_0_height_0_subtile_0__pin_I2i_0_,
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top_width_0_height_0_subtile_0__pin_I2i_1_,
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top_width_0_height_0_subtile_0__pin_I3_0_,
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top_width_0_height_0_subtile_0__pin_I3_1_,
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top_width_0_height_0_subtile_0__pin_I3i_0_,
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top_width_0_height_0_subtile_0__pin_I3i_1_,
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top_width_0_height_0_subtile_0__pin_reg_in_0_,
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top_width_0_height_0_subtile_0__pin_sc_in_0_,
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top_width_0_height_0_subtile_0__pin_cin_0_,
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right_width_0_height_0_subtile_0__pin_I4_0_,
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right_width_0_height_0_subtile_0__pin_I4_1_,
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right_width_0_height_0_subtile_0__pin_I4i_0_,
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right_width_0_height_0_subtile_0__pin_I4i_1_,
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right_width_0_height_0_subtile_0__pin_I5_0_,
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right_width_0_height_0_subtile_0__pin_I5_1_,
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right_width_0_height_0_subtile_0__pin_I5i_0_,
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right_width_0_height_0_subtile_0__pin_I5i_1_,
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right_width_0_height_0_subtile_0__pin_I6_0_,
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right_width_0_height_0_subtile_0__pin_I6_1_,
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right_width_0_height_0_subtile_0__pin_I6i_0_,
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right_width_0_height_0_subtile_0__pin_I6i_1_,
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right_width_0_height_0_subtile_0__pin_I7_0_,
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right_width_0_height_0_subtile_0__pin_I7_1_,
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right_width_0_height_0_subtile_0__pin_I7i_0_,
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right_width_0_height_0_subtile_0__pin_I7i_1_,
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left_width_0_height_0_subtile_0__pin_reset_0_,
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left_width_0_height_0_subtile_0__pin_clk_0_,
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ccff_head,
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top_width_0_height_0_subtile_0__pin_O_0_,
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top_width_0_height_0_subtile_0__pin_O_1_,
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top_width_0_height_0_subtile_0__pin_O_2_,
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top_width_0_height_0_subtile_0__pin_O_3_,
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top_width_0_height_0_subtile_0__pin_O_4_,
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top_width_0_height_0_subtile_0__pin_O_5_,
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top_width_0_height_0_subtile_0__pin_O_6_,
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top_width_0_height_0_subtile_0__pin_O_7_,
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right_width_0_height_0_subtile_0__pin_O_8_,
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right_width_0_height_0_subtile_0__pin_O_9_,
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right_width_0_height_0_subtile_0__pin_O_10_,
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right_width_0_height_0_subtile_0__pin_O_11_,
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right_width_0_height_0_subtile_0__pin_O_12_,
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right_width_0_height_0_subtile_0__pin_O_13_,
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right_width_0_height_0_subtile_0__pin_O_14_,
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right_width_0_height_0_subtile_0__pin_O_15_,
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bottom_width_0_height_0_subtile_0__pin_reg_out_0_,
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bottom_width_0_height_0_subtile_0__pin_sc_out_0_,
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bottom_width_0_height_0_subtile_0__pin_cout_0_,
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ccff_tail);
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//----- GLOBAL PORTS -----
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input [0:0] pReset;
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//----- GLOBAL PORTS -----
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input [0:0] prog_clk;
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//----- GLOBAL PORTS -----
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input [0:0] Test_en;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_I0_0_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_I0_1_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_I0i_0_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_I0i_1_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_I1_0_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_I1_1_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_I1i_0_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_I1i_1_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_I2_0_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_I2_1_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_I2i_0_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_I2i_1_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_I3_0_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_I3_1_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_I3i_0_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_I3i_1_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_reg_in_0_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_sc_in_0_;
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//----- INPUT PORTS -----
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input [0:0] top_width_0_height_0_subtile_0__pin_cin_0_;
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//----- INPUT PORTS -----
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input [0:0] right_width_0_height_0_subtile_0__pin_I4_0_;
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//----- INPUT PORTS -----
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input [0:0] right_width_0_height_0_subtile_0__pin_I4_1_;
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//----- INPUT PORTS -----
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input [0:0] right_width_0_height_0_subtile_0__pin_I4i_0_;
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//----- INPUT PORTS -----
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input [0:0] right_width_0_height_0_subtile_0__pin_I4i_1_;
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//----- INPUT PORTS -----
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input [0:0] right_width_0_height_0_subtile_0__pin_I5_0_;
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//----- INPUT PORTS -----
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input [0:0] right_width_0_height_0_subtile_0__pin_I5_1_;
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//----- INPUT PORTS -----
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input [0:0] right_width_0_height_0_subtile_0__pin_I5i_0_;
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//----- INPUT PORTS -----
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input [0:0] right_width_0_height_0_subtile_0__pin_I5i_1_;
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//----- INPUT PORTS -----
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input [0:0] right_width_0_height_0_subtile_0__pin_I6_0_;
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//----- INPUT PORTS -----
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input [0:0] right_width_0_height_0_subtile_0__pin_I6_1_;
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//----- INPUT PORTS -----
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input [0:0] right_width_0_height_0_subtile_0__pin_I6i_0_;
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//----- INPUT PORTS -----
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input [0:0] right_width_0_height_0_subtile_0__pin_I6i_1_;
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//----- INPUT PORTS -----
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input [0:0] right_width_0_height_0_subtile_0__pin_I7_0_;
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//----- INPUT PORTS -----
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input [0:0] right_width_0_height_0_subtile_0__pin_I7_1_;
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//----- INPUT PORTS -----
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input [0:0] right_width_0_height_0_subtile_0__pin_I7i_0_;
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//----- INPUT PORTS -----
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input [0:0] right_width_0_height_0_subtile_0__pin_I7i_1_;
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//----- INPUT PORTS -----
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input [0:0] left_width_0_height_0_subtile_0__pin_reset_0_;
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//----- INPUT PORTS -----
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input [0:0] left_width_0_height_0_subtile_0__pin_clk_0_;
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//----- INPUT PORTS -----
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input [0:0] ccff_head;
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//----- OUTPUT PORTS -----
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output [0:0] top_width_0_height_0_subtile_0__pin_O_0_;
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//----- OUTPUT PORTS -----
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output [0:0] top_width_0_height_0_subtile_0__pin_O_1_;
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//----- OUTPUT PORTS -----
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output [0:0] top_width_0_height_0_subtile_0__pin_O_2_;
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//----- OUTPUT PORTS -----
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output [0:0] top_width_0_height_0_subtile_0__pin_O_3_;
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//----- OUTPUT PORTS -----
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output [0:0] top_width_0_height_0_subtile_0__pin_O_4_;
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//----- OUTPUT PORTS -----
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output [0:0] top_width_0_height_0_subtile_0__pin_O_5_;
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//----- OUTPUT PORTS -----
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output [0:0] top_width_0_height_0_subtile_0__pin_O_6_;
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//----- OUTPUT PORTS -----
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output [0:0] top_width_0_height_0_subtile_0__pin_O_7_;
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//----- OUTPUT PORTS -----
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output [0:0] right_width_0_height_0_subtile_0__pin_O_8_;
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//----- OUTPUT PORTS -----
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output [0:0] right_width_0_height_0_subtile_0__pin_O_9_;
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//----- OUTPUT PORTS -----
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output [0:0] right_width_0_height_0_subtile_0__pin_O_10_;
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//----- OUTPUT PORTS -----
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output [0:0] right_width_0_height_0_subtile_0__pin_O_11_;
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//----- OUTPUT PORTS -----
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output [0:0] right_width_0_height_0_subtile_0__pin_O_12_;
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//----- OUTPUT PORTS -----
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output [0:0] right_width_0_height_0_subtile_0__pin_O_13_;
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//----- OUTPUT PORTS -----
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output [0:0] right_width_0_height_0_subtile_0__pin_O_14_;
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//----- OUTPUT PORTS -----
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output [0:0] right_width_0_height_0_subtile_0__pin_O_15_;
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//----- OUTPUT PORTS -----
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output [0:0] bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
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//----- OUTPUT PORTS -----
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output [0:0] bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
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//----- OUTPUT PORTS -----
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output [0:0] bottom_width_0_height_0_subtile_0__pin_cout_0_;
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//----- OUTPUT PORTS -----
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output [0:0] ccff_tail;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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// ----- END Local output short connections -----
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logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 (
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.pReset(pReset),
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.prog_clk(prog_clk),
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.Test_en(Test_en),
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.clb_I0({top_width_0_height_0_subtile_0__pin_I0_0_, top_width_0_height_0_subtile_0__pin_I0_1_}),
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.clb_I0i({top_width_0_height_0_subtile_0__pin_I0i_0_, top_width_0_height_0_subtile_0__pin_I0i_1_}),
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.clb_I1({top_width_0_height_0_subtile_0__pin_I1_0_, top_width_0_height_0_subtile_0__pin_I1_1_}),
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.clb_I1i({top_width_0_height_0_subtile_0__pin_I1i_0_, top_width_0_height_0_subtile_0__pin_I1i_1_}),
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.clb_I2({top_width_0_height_0_subtile_0__pin_I2_0_, top_width_0_height_0_subtile_0__pin_I2_1_}),
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.clb_I2i({top_width_0_height_0_subtile_0__pin_I2i_0_, top_width_0_height_0_subtile_0__pin_I2i_1_}),
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.clb_I3({top_width_0_height_0_subtile_0__pin_I3_0_, top_width_0_height_0_subtile_0__pin_I3_1_}),
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.clb_I3i({top_width_0_height_0_subtile_0__pin_I3i_0_, top_width_0_height_0_subtile_0__pin_I3i_1_}),
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.clb_I4({right_width_0_height_0_subtile_0__pin_I4_0_, right_width_0_height_0_subtile_0__pin_I4_1_}),
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.clb_I4i({right_width_0_height_0_subtile_0__pin_I4i_0_, right_width_0_height_0_subtile_0__pin_I4i_1_}),
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.clb_I5({right_width_0_height_0_subtile_0__pin_I5_0_, right_width_0_height_0_subtile_0__pin_I5_1_}),
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.clb_I5i({right_width_0_height_0_subtile_0__pin_I5i_0_, right_width_0_height_0_subtile_0__pin_I5i_1_}),
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.clb_I6({right_width_0_height_0_subtile_0__pin_I6_0_, right_width_0_height_0_subtile_0__pin_I6_1_}),
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.clb_I6i({right_width_0_height_0_subtile_0__pin_I6i_0_, right_width_0_height_0_subtile_0__pin_I6i_1_}),
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.clb_I7({right_width_0_height_0_subtile_0__pin_I7_0_, right_width_0_height_0_subtile_0__pin_I7_1_}),
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.clb_I7i({right_width_0_height_0_subtile_0__pin_I7i_0_, right_width_0_height_0_subtile_0__pin_I7i_1_}),
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.clb_reg_in(top_width_0_height_0_subtile_0__pin_reg_in_0_),
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.clb_sc_in(top_width_0_height_0_subtile_0__pin_sc_in_0_),
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.clb_cin(top_width_0_height_0_subtile_0__pin_cin_0_),
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.clb_reset(left_width_0_height_0_subtile_0__pin_reset_0_),
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.clb_clk(left_width_0_height_0_subtile_0__pin_clk_0_),
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.ccff_head(ccff_head),
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.clb_O({top_width_0_height_0_subtile_0__pin_O_0_, top_width_0_height_0_subtile_0__pin_O_1_, top_width_0_height_0_subtile_0__pin_O_2_, top_width_0_height_0_subtile_0__pin_O_3_, top_width_0_height_0_subtile_0__pin_O_4_, top_width_0_height_0_subtile_0__pin_O_5_, top_width_0_height_0_subtile_0__pin_O_6_, top_width_0_height_0_subtile_0__pin_O_7_, right_width_0_height_0_subtile_0__pin_O_8_, right_width_0_height_0_subtile_0__pin_O_9_, right_width_0_height_0_subtile_0__pin_O_10_, right_width_0_height_0_subtile_0__pin_O_11_, right_width_0_height_0_subtile_0__pin_O_12_, right_width_0_height_0_subtile_0__pin_O_13_, right_width_0_height_0_subtile_0__pin_O_14_, right_width_0_height_0_subtile_0__pin_O_15_}),
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.clb_reg_out(bottom_width_0_height_0_subtile_0__pin_reg_out_0_),
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.clb_sc_out(bottom_width_0_height_0_subtile_0__pin_sc_out_0_),
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.clb_cout(bottom_width_0_height_0_subtile_0__pin_cout_0_),
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.ccff_tail(ccff_tail));
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endmodule
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// ----- END Verilog module for grid_clb -----
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//----- Default net type -----
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`default_nettype none
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// ----- END Grid Verilog module: grid_clb -----
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