mirror of https://github.com/lnis-uofu/SOFA.git
37 lines
1.4 KiB
ReStructuredText
37 lines
1.4 KiB
ReStructuredText
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.. _qlsofa_hd_circuit_design:
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Circuit Designs
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---------------
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.. _qlsofa_hd_circuit_design_io:
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I/O Circuit
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^^^^^^^^^^^
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As shown in :numref:`fig_qlsofa_hd_embedded_io_schematic`, the I/O circuit used in the I/O tiles of the FPGA fabric (see :numref:`fig_qlsofa_hd_fpga_arch`) is an digital I/O cell with
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- An **active-low** I/O isolation signal ``IO_ISOL_N`` to set the I/O in input mode. This is to avoid any unexpected output signals to damage circuits outside the FPGA due to configurable memories are not properly initialized.
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.. warning:: This feature may not be needed if the configurable memory cell has a built-in set/reset functionality!
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- An internal protection circuitry to ensure clean signals at all the SOC I/O ports. This is to avoid
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- ``SOC_OUT`` port outputs any random signal when the I/O is in input mode
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- ``FPGA_IN`` port is driven by any random signal when the I/O is output mode
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- An internal configurable memory element to control the direction of I/O cell
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The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where
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- When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode
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- When configuration bit (FF output) is logic ``0``, the I/O cell is in output mode
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.. _fig_qlsofa_hd_embedded_io_schematic:
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.. figure:: ./figures/qlsofa_hd_embedded_io_schematic.svg
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:scale: 30%
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:alt: Schematic of embedded I/O cell used in FPGA
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Schematic of embedded I/O cell used in FPGA
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