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SOFA/SynRepoConfig/sync_files_sofa_chd.csv

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[Sync] Updated sync file list
2020-12-14 16:29:41 -06:00
SrcLoc, DestLoc
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/,OpenFPGA_task
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
[CI] Precheck related updates
2020-12-17 16:01:49 -06:00
FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v