mirror of https://github.com/lnis-uofu/SOFA.git
48 lines
2.1 KiB
Bash
48 lines
2.1 KiB
Bash
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# = = = = = = = = = = = = = = Variables Sections = = = = = = = = = = = = = = =
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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export PROJ_NAME=FPGA1212_FLAT_HD_SKY # Project Name
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export FPGA_SIZE_X=12 # Grid X Size
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export FPGA_SIZE_Y=12 # Grid Y Size
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# Design Style [hier/flat], mostly hier
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export DESIGN_STYLE=hier
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export TECHNOLOGY="skywater"
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# Complete Chip (fpga_top) or eFPGA (fpga_core)
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export DESIGN_NAME=fpga_core
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# Pin Information Source Automatic or Sheet
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export PIN_MAP=Automatic
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export PIN_MAP_CSV_SPREADSHEET_LINK="" # Required only if PIN_MAP==Sheet
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# Core Dimension, requires if DESIGN_NAME=fpga_core
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# if DESIGN_NAME=fpga_top its Optional if defined it overrides the
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# Calculated DIE_DIMENSION
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export DIE_DIMENSION=2800
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Derived Or Fixed Variables
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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export OPENFPGA_ENGINE_PATH=/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip
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export TASK_DIR_NAME=${PROJ_NAME}_task
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export VERILOG_PROJ_DIR=${PROJ_NAME}_Verilog
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export SPY_HACK_FILE=${TASK_DIR_NAME}/spy_hack.txt
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export POST_OPENFPGA_SCRIPT=./PostOpenFPGAScript.sh
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export RESTRUCT_NETLIST=../utils/RestructureNetlistSkywater.py
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Restructure Netlist Varaibles
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# export RESTRUCTURE_skipClockRestructure=""
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# export RESTRUCTURE_Skeleton=""
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# PNR RELATED FLOW
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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export INIT_DESIGN_INPUT="ASCII"
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Extra variables availble during flow (suuffix FLOWVAR_)
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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export FLOWVAR_STANDARD_CELLS="sc_hd"
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