2020-11-09 20:17:15 -06:00
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commit 520e54d7abecebf75310bb901ce702532148d686
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Merge: 4a53640c 056b7c0c
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2020-11-08 02:06:13 -06:00
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Author: Laboratory for Nano Integrated Systems (LNIS) <40280375+LNIS-Projects@users.noreply.github.com>
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2020-11-09 20:17:15 -06:00
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Date: Fri Nov 6 13:25:29 2020 -0700
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2020-10-27 00:59:20 -05:00
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2020-11-09 20:17:15 -06:00
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Merge pull request #118 from LNIS-Projects/dev
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2020-11-08 02:06:13 -06:00
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2020-11-09 20:17:15 -06:00
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Remove the restrictions on requiring two outputs for configurable memory circuits
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2020-10-27 00:59:20 -05:00
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2020-11-09 20:17:15 -06:00
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commit 056b7c0c7997d2d12473f2fc4b7915e25ff74820
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2020-10-27 00:59:20 -05:00
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Author: tangxifan <tangxifan@gmail.com>
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2020-11-09 20:17:15 -06:00
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Date: Fri Nov 6 12:22:22 2020 -0700
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2020-10-27 00:59:20 -05:00
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2020-11-09 20:17:15 -06:00
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[Doc] Update documentation about CCFF circuit model examples
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2020-10-27 00:59:20 -05:00
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2020-11-09 20:17:15 -06:00
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commit 70734abc35347dbc27113200908858c9a66e9945
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2020-10-27 00:59:20 -05:00
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Author: tangxifan <tangxifan@gmail.com>
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2020-11-09 20:17:15 -06:00
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Date: Fri Nov 6 11:20:13 2020 -0700
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2020-10-27 00:59:20 -05:00
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2020-11-09 20:17:15 -06:00
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[Arch] Remove QN from stdcell arch
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2020-10-27 00:59:20 -05:00
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2020-11-09 20:17:15 -06:00
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commit 1a79a556467ae8d9d4d791b94462e168e15635ca
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2020-10-27 00:59:20 -05:00
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Author: tangxifan <tangxifan@gmail.com>
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2020-11-09 20:17:15 -06:00
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Date: Fri Nov 6 11:19:19 2020 -0700
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2020-10-27 00:59:20 -05:00
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2020-11-09 20:17:15 -06:00
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[HDL] Add DFF cell with reset but only 1 output
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2020-10-27 00:59:20 -05:00
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2020-11-09 20:17:15 -06:00
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commit 0a273ffab65b1f503d6e63da59c93644375dc3b1
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2020-10-27 00:59:20 -05:00
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Author: tangxifan <tangxifan@gmail.com>
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2020-11-09 20:17:15 -06:00
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Date: Fri Nov 6 11:16:46 2020 -0700
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2020-10-27 00:59:20 -05:00
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2020-11-09 20:17:15 -06:00
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[Tool] Bug fix in the tight requirements on CCFF circuit model
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2020-11-08 02:06:13 -06:00
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On branch master
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Your branch is up to date with 'origin/master'.
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2020-10-27 00:59:20 -05:00
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Untracked files:
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(use "git add <file>..." to include in what will be committed)
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openfpga/openfpga
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2020-11-08 02:06:13 -06:00
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openfpga_flow/tasks/FPGA1212_FC_HD_SKY_task
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openfpga_flow/tasks/FPGA1212_HIER_SKY_SC_MS_task
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2020-10-27 00:59:20 -05:00
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openfpga_flow/tasks/FPGA128128_FLAT_task
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openfpga_flow/tasks/FPGA1616_FLAT_task
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openfpga_flow/tasks/FPGA22_FLAT_task
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openfpga_flow/tasks/FPGA22_FRAME_task
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2020-11-08 02:06:13 -06:00
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openfpga_flow/tasks/FPGA22_HIER_SKY_SC_MS_task
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2020-10-27 00:59:20 -05:00
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openfpga_flow/tasks/FPGA22_HIER_SKY_task
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openfpga_flow/tasks/FPGA22_HIER_task
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openfpga_flow/tasks/FPGA22_MB_task
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openfpga_flow/tasks/FPGA22_MODULAR_task
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openfpga_flow/tasks/FPGA22_SPY_task
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openfpga_flow/tasks/FPGA3232_FLAT_task
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openfpga_flow/tasks/FPGA44_FLAT_task
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openfpga_flow/tasks/FPGA6464_FLAT_task
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openfpga_flow/tasks/FPGA66_FLAT_task
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openfpga_flow/tasks/FPGA88_FLAT_task
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openfpga_flow/tasks/routing_test/
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openfpga_flow/tasks/skywater_openfpga_task
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vpr/vpr
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nothing added to commit but untracked files present (use "git add" to track)
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